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// TI File $Revision: /main/3 $
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// Checkin $Date: April 17, 2008 11:08:27 $
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//###########################################################################
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//
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// FILE: DSP2833x_Spi.h
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//
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// TITLE: DSP2833x Device SPI Register Definitions.
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//
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//###########################################################################
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// $TI Release: 2833x/2823x Header Files V1.32 $
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// $Release Date: June 28, 2010 $
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// $Copyright:
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// Copyright (C) 2009-2024 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef DSP2833x_SPI_H
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#define DSP2833x_SPI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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//
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// SPI Individual Register Bit Definitions
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//
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//
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// SPI FIFO Transmit register bit definitions
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//
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struct SPIFFTX_BITS { // bit description
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Uint16 TXFFIL:5; // 4:0 Interrupt level
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Uint16 TXFFIENA:1; // 5 Interrupt enable
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Uint16 TXFFINTCLR:1; // 6 Clear INT flag
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Uint16 TXFFINT:1; // 7 INT flag
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Uint16 TXFFST:5; // 12:8 FIFO status
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Uint16 TXFIFO:1; // 13 FIFO reset
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Uint16 SPIFFENA:1; // 14 Enhancement enable
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Uint16 SPIRST:1; // 15 Reset SPI
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};
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union SPIFFTX_REG {
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Uint16 all;
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struct SPIFFTX_BITS bit;
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};
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//
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// SPI FIFO recieve register bit definitions
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//
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struct SPIFFRX_BITS { // bits description
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Uint16 RXFFIL:5; // 4:0 Interrupt level
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Uint16 RXFFIENA:1; // 5 Interrupt enable
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Uint16 RXFFINTCLR:1; // 6 Clear INT flag
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Uint16 RXFFINT:1; // 7 INT flag
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Uint16 RXFFST:5; // 12:8 FIFO status
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Uint16 RXFIFORESET:1; // 13 FIFO reset
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Uint16 RXFFOVFCLR:1; // 14 Clear overflow
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Uint16 RXFFOVF:1; // 15 FIFO overflow
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};
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union SPIFFRX_REG {
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Uint16 all;
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struct SPIFFRX_BITS bit;
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};
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//
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// SPI FIFO control register bit definitions
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//
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struct SPIFFCT_BITS { // bits description
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Uint16 TXDLY:8; // 7:0 FIFO transmit delay
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Uint16 rsvd:8; // 15:8 reserved
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};
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union SPIFFCT_REG {
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Uint16 all;
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struct SPIFFCT_BITS bit;
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};
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//
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// SPI configuration register bit definitions
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//
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struct SPICCR_BITS { // bits description
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Uint16 SPICHAR:4; // 3:0 Character length control
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Uint16 SPILBK:1; // 4 Loop-back enable/disable
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Uint16 rsvd1:1; // 5 reserved
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Uint16 CLKPOLARITY:1; // 6 Clock polarity
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Uint16 SPISWRESET:1; // 7 SPI SW Reset
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Uint16 rsvd2:8; // 15:8 reserved
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};
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union SPICCR_REG {
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Uint16 all;
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struct SPICCR_BITS bit;
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};
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//
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// SPI operation control register bit definitions
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//
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struct SPICTL_BITS { // bits description
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Uint16 SPIINTENA:1; // 0 Interrupt enable
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Uint16 TALK:1; // 1 Master/Slave transmit enable
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Uint16 MASTER_SLAVE:1; // 2 Network control mode
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Uint16 CLK_PHASE:1; // 3 Clock phase select
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Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable
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Uint16 rsvd:11; // 15:5 reserved
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};
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union SPICTL_REG {
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Uint16 all;
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struct SPICTL_BITS bit;
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};
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//
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// SPI status register bit definitions
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//
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struct SPISTS_BITS { // bits description
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Uint16 rsvd1:5; // 4:0 reserved
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Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag
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Uint16 INT_FLAG:1; // 6 SPI interrupt flag
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Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag
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Uint16 rsvd2:8; // 15:8 reserved
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};
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union SPISTS_REG {
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Uint16 all;
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struct SPISTS_BITS bit;
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};
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//
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// SPI priority control register bit definitions
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//
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struct SPIPRI_BITS { // bits description
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Uint16 rsvd1:4; // 3:0 reserved
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Uint16 FREE:1; // 4 Free emulation mode control
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Uint16 SOFT:1; // 5 Soft emulation mode control
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Uint16 rsvd2:1; // 6 reserved
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Uint16 rsvd3:9; // 15:7 reserved
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};
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union SPIPRI_REG {
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Uint16 all;
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struct SPIPRI_BITS bit;
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};
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//
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// SPI Register File
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//
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struct SPI_REGS {
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union SPICCR_REG SPICCR; // Configuration register
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union SPICTL_REG SPICTL; // Operation control register
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union SPISTS_REG SPISTS; // Status register
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Uint16 rsvd1; // reserved
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Uint16 SPIBRR; // Baud Rate
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Uint16 rsvd2; // reserved
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Uint16 SPIRXEMU; // Emulation buffer
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Uint16 SPIRXBUF; // Serial input buffer
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Uint16 SPITXBUF; // Serial output buffer
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Uint16 SPIDAT; // Serial data
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union SPIFFTX_REG SPIFFTX; // FIFO transmit register
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union SPIFFRX_REG SPIFFRX; // FIFO recieve register
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union SPIFFCT_REG SPIFFCT; // FIFO control register
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Uint16 rsvd3[2]; // reserved
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union SPIPRI_REG SPIPRI; // FIFO Priority control
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};
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//
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// SPI External References & Function Declarations
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//
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extern volatile struct SPI_REGS SpiaRegs;
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#ifdef __cplusplus
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}
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#endif /* extern "C" */
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#endif // end of DSP2833x_SPI_H definition
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//
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// End of file
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//
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