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CCS-COMM_BOARD/DSP28335/EPWM.cpp

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Modbus still working here
4 weeks ago
/*
* EPWM.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/EPWM.h"
namespace DSP28335
{
//CONSTRUCTOR
EPWMConfigModificator::EPWMConfigModificator():
m_config(),
modify(true)
{}//CONSTRUCTOR
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_config(EPWMConfiguration& refconfig)
{
if(m_config.fpwm != refconfig.fpwm)
{
m_config.fpwm = refconfig.fpwm;
modify = true;
}//
if(m_config.pulse_sync != refconfig.pulse_sync)
{
m_config.pulse_sync = refconfig.pulse_sync;
modify = true;
}//
if(m_config.pulse_adc_soc != refconfig.pulse_adc_soc)
{
m_config.pulse_adc_soc = refconfig.pulse_adc_soc;
modify = true;
}//
//
if(m_config.adc_soc_offset != refconfig.adc_soc_offset)
{
m_config.adc_soc_offset = refconfig.adc_soc_offset;
modify = true;
}//
//
if(m_config.adc_soc_quantity != refconfig.adc_soc_quantity)
{
m_config.adc_soc_quantity = refconfig.adc_soc_quantity;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
EPWMConfiguration EPWMConfigModificator::get_config()
{
return m_config;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::reset()
{
modify = false;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_pwm_frquency(float fpwm)
{
if(m_config.fpwm != fpwm)
{
m_config.fpwm = fpwm;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_pulse_sync(float pulse_sync)
{
if(m_config.pulse_sync != pulse_sync)
{
m_config.pulse_sync = pulse_sync;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_pulse_adc_soc(float pulse_adc_soc)
{
if(m_config.pulse_adc_soc != pulse_adc_soc)
{
m_config.pulse_adc_soc = pulse_adc_soc;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_adc_soc_offset(float adc_soc_offset)
{
if(m_config.adc_soc_offset != adc_soc_offset)
{
m_config.adc_soc_offset = adc_soc_offset;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_adc_soc_quantity(Uint16 adc_soc_quantity)
{
if(m_config.adc_soc_quantity != adc_soc_quantity)
{
m_config.adc_soc_quantity = adc_soc_quantity;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_pwm_frquency()
{
return m_config.fpwm;
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_pulse_sync()
{
return m_config.pulse_sync;
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_pulse_adc_soc()
{
return m_config.pulse_adc_soc;
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_adc_soc_offset()
{
return m_config.adc_soc_offset;
}//
//
// #pragma CODE_SECTION("ramfuncs");
Uint16 EPWMConfigModificator::get_adc_soc_quantity()
{
return m_config.adc_soc_quantity;
}//
//
//CONSTRUCTOR
EPWM::EPWM():
DSP28335::CPUBase(),
m_configuration_current(),
m_configuration_new(),
m_fcpu(150.0e6),
m_timer_period(FP_ZERO),
m_timer_step(FP_ZERO),
m_time_sample_adc(FP_ZERO),
m_clock_prescale_list(),
m_high_speed_clock_prescale(),
m_tbprd(FP_ZERO),
m_clkdiv(0),
m_hspclkdiv(0),
m_cmpr_sync(0),
m_cmpr_adc_offset(0),
m_cmpr_adc_start(0),
m_cmpr_adc_stop(0),
m_cmpr_adc_width(0),
m_cmpr_adc_step(0),
m_adc_soc_quantity(0),
m_adc_soc_counter(0),
_epwm2_adc_drive(0),
status(),
_gpio_setup(0)
//
{
m_clock_prescale_list[0] = 1.0;
m_clock_prescale_list[1] = 2.0;
m_clock_prescale_list[2] = 4.0;
m_clock_prescale_list[3] = 8.0;
m_clock_prescale_list[4] = 16.0;
m_clock_prescale_list[5] = 32.0;
m_clock_prescale_list[6] = 64.0;
m_clock_prescale_list[7] = 128.0;
//
m_high_speed_clock_prescale[0] = 1.0;
m_high_speed_clock_prescale[1] = 2.0;
m_high_speed_clock_prescale[2] = 4.0;
m_high_speed_clock_prescale[3] = 6.0;
m_high_speed_clock_prescale[4] = 8.0;
m_high_speed_clock_prescale[5] = 10.0;
m_high_speed_clock_prescale[6] = 12.0;
m_high_speed_clock_prescale[7] = 14.0;
//
}//end CONSTRUCTOR
void EPWM::setup(const EPWMSetup& setup)
{
m_status = true;
//m_status &= m_mode == DSP28335::EPWM::UNDEFINED ? true : false;
m_status &= setup.parameters.fpwm > (float)(5.0) ? true : false;
m_status &= setup.parameters.pulse_sync != FP_ZERO ? true : false;
m_status &= setup.parameters.pulse_adc_soc != FP_ZERO ? true : false;
m_status &= setup.parameters.adc_soc_offset >= FP_ZERO ? true : false;
m_status &= setup.parameters.adc_soc_quantity >= 1 ? true : false;
m_status &= setup.gpio_setup != 0 ? true : false;
//
if(m_status)
{
m_configuration_current = setup.parameters;
m_tbprd = 0;
m_clkdiv = 0;
m_hspclkdiv = 0;
m_cmpr_sync = 0;
//
m_cmpr_adc_start = 0;
m_cmpr_adc_stop = 0;
m_cmpr_adc_width = 0;
m_cmpr_adc_step = 0;
//
m_adc_soc_quantity = setup.parameters.adc_soc_quantity;
m_adc_soc_counter = 0;
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/setup.parameters.fpwm;
//
while(m_timer_period>(float)(32767.0))
{
m_clkdiv++;
if(m_clkdiv >= 8)
{
m_clkdiv = 0;
m_hspclkdiv++;
//
}//if
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/setup.parameters.fpwm;
//
}//while
//
m_timer_step = (m_clock_prescale_list[m_clkdiv] * m_high_speed_clock_prescale[m_hspclkdiv])/m_fcpu;
m_tbprd = (Uint16)m_timer_period;
m_cmpr_sync = m_tbprd - (Uint16)(setup.parameters.pulse_sync/m_timer_step);
m_cmpr_adc_width = (Uint16)((float)(setup.parameters.pulse_adc_soc/m_timer_step));
m_cmpr_adc_step = (Uint16)((float)((float)m_timer_period/((float)setup.parameters.adc_soc_quantity)));
m_cmpr_adc_offset = (Uint16)((float)(m_timer_period * setup.parameters.adc_soc_offset));
m_time_sample_adc = m_timer_step * ((float)m_cmpr_adc_step);
status.all = 0;
//
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
// Setup TBCLK
EPwm1Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //
EPwm1Regs.TBCTL.bit.PHSEN = 0x0; //
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm1Regs.TBCTL.bit.CLKDIV = m_clkdiv;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm1Regs.AQCTLB.all = 0;
EPwm1Regs.AQSFRC.bit.ACTSFA = 0;
EPwm1Regs.AQSFRC.bit.ACTSFB = 0;
EPwm1Regs.AQSFRC.bit.OTSFA = 0;
EPwm1Regs.AQSFRC.bit.OTSFB = 0;
EPwm1Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm1Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm1Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm1Regs.DBCTL.bit.POLSEL = 0; // Active High complementary
EPwm1Regs.DBCTL.bit.IN_MODE = 0; //
EPwm1Regs.DBFED = 0;
EPwm1Regs.DBRED = 0;
// Set Compare values
EPwm1Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm1Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
//EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA; // Select INT on equal to CMPA
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
//EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // SOCA equal to zero: 1-zero; 2-period
//EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Disable INT EPWMxSOCA
//EPwm1Regs.ETSEL.bit.SOCBSEL = 2 // SOCB equal to period
//EPwm1Regs.ETSEL.bit.SOCBEN = 0; // Disable INT EPWMxSOCB
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; //
EPwm1Regs.ETPS.bit.INTCNT = 0;
// PWM-Chopper
EPwm1Regs.PCCTL.all = 0; // PWM-Chopper Control Register
// Trip-Zone Submodule
EPwm1Regs.TZSEL.all = 0; // Trip-Zone Select Register
EPwm1Regs.TZCTL.all = 0; // Trip-Zone Control Register
EPwm1Regs.TZEINT.all = 0; // Trip-Zone Enable Interrupt Register
//EPwm1Regs.TZFLG.all = 0; // Trip-Zone Flag Register
//EPwm1Regs.TZCLR.all = 0; // Trip-Zone Clear Register
//EPwm1Regs.TZFRC.all = 0; // Trip-Zone Force Register
// Setup TBCLK
EPwm2Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //
EPwm2Regs.TBCTL.bit.PHSEN = 0x0; //
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm2Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm2Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm2Regs.AQCTLB.all = 0;
EPwm2Regs.AQSFRC.bit.ACTSFA = 0;
EPwm2Regs.AQSFRC.bit.ACTSFB = 0;
EPwm2Regs.AQSFRC.bit.OTSFA = 0;
EPwm2Regs.AQSFRC.bit.OTSFB = 0;
EPwm2Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm2Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm2Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm2Regs.DBCTL.bit.POLSEL = 0; // Active High complementary
EPwm2Regs.DBCTL.bit.IN_MODE = 0; //
EPwm2Regs.DBFED = 0;
EPwm2Regs.DBRED = 0;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_offset; // Set compare A value
EPwm2Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA; //
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
//EPwm2Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // SOCA equal to zero: 1-zero; 2-period
//EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Disable INT EPWMxSOCA
//EPwm2Regs.ETSEL.bit.SOCBSEL = 2 // SOCB equal to period
//EPwm2Regs.ETSEL.bit.SOCBEN = 0; // Disable INT EPWMxSOCB
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; //
EPwm2Regs.ETPS.bit.INTCNT = 0;
// Setup TBCLK
EPwm5Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm5Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;// Count up/down
EPwm5Regs.TBCTL.bit.PHSEN = 0x0; // Disable phase loading
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm5Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm5Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm5Regs.CMPCTL.bit.LOADAMODE = 0; // Load on Zero
EPwm5Regs.CMPCTL.bit.LOADBMODE = 0;
// Set actions
EPwm5Regs.AQCTLA.all = 0;
EPwm5Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm5Regs.AQCTLB.bit.PRD = AQ_CLEAR;
EPwm5Regs.AQSFRC.bit.ACTSFA = 0;
EPwm5Regs.AQSFRC.bit.ACTSFB = 0;
EPwm5Regs.AQSFRC.bit.OTSFA = 0;
EPwm5Regs.AQSFRC.bit.OTSFB = 0;
EPwm5Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm5Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm5Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm5Regs.DBCTL.bit.POLSEL = 0; // Active Hi complementary
EPwm5Regs.DBCTL.bit.IN_MODE = 0; //
EPwm5Regs.DBFED = 0;
EPwm5Regs.DBRED = 0;
// Set Compare values
EPwm5Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm5Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
EPwm5Regs.ETSEL.all = 0;
EPwm5Regs.ETPS.all = 0;
// PWM-Chopper
EPwm5Regs.PCCTL.all = 0; // PWM-Chopper Control Register
// Trip-Zone Submodule
EPwm5Regs.TZSEL.all = 0; // Trip-Zone Select Register
EPwm5Regs.TZCTL.all = 0; // Trip-Zone Control Register
EPwm5Regs.TZEINT.all = 0; // Trip-Zone Enable Interrupt Register
// Setup TBCLK
EPwm6Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm6Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;// Count up/down
EPwm6Regs.TBCTL.bit.PHSEN = 0x0; // Disable phase loading
EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm6Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm6Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm6Regs.CMPCTL.bit.LOADAMODE = 0; // Load on Zero
EPwm6Regs.CMPCTL.bit.LOADBMODE = 0;
// Set actions
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count
EPwm6Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm6Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm6Regs.AQCTLB.bit.PRD = AQ_CLEAR;
EPwm6Regs.AQSFRC.bit.ACTSFA = 0;
EPwm6Regs.AQSFRC.bit.ACTSFB = 0;
EPwm6Regs.AQSFRC.bit.OTSFA = 0;
EPwm6Regs.AQSFRC.bit.OTSFB = 0;
EPwm6Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm6Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm6Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm6Regs.DBCTL.bit.POLSEL = 0; // Active Hi complementary
EPwm6Regs.DBCTL.bit.IN_MODE = 0; //
EPwm6Regs.DBFED = 0;
EPwm6Regs.DBRED = 0;
// Set Compare values
EPwm6Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm6Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
EPwm6Regs.ETSEL.all = 0;
//EPwm6Regs.ETPS.bit.INTPRD = 0; //
EPwm6Regs.ETPS.all = 0;
// PWM-Chopper
EPwm6Regs.PCCTL.all = 0; // PWM-Chopper Control Register
// Trip-Zone Submodule
EPwm6Regs.TZSEL.all = 0; // Trip-Zone Select Register
EPwm6Regs.TZCTL.all = 0; // Trip-Zone Control Register
EPwm6Regs.TZEINT.all = 0; // Trip-Zone Enable Interrupt Register
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_start;
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
m_mode = DSP28335::EPWM::OPERATIONAL;
//
}
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::configure(const EPWMConfiguration& config)
{
m_status = true;
m_status &= config.fpwm > (float)(5.0) ? true : false;
m_status &= config.pulse_sync != FP_ZERO ? true : false;
m_status &= config.pulse_adc_soc != FP_ZERO ? true : false;
m_status &= config.adc_soc_offset >= FP_ZERO ? true : false;
m_status &= config.adc_soc_quantity >= 1 ? true : false;
//
if(m_status)
{
m_configuration_current = config;
m_tbprd = 0;
m_clkdiv = 0;
m_hspclkdiv = 0;
m_cmpr_sync = 0;
//
m_cmpr_adc_start = 0;
m_cmpr_adc_stop = 0;
m_cmpr_adc_width = 0;
m_cmpr_adc_step = 0;
//
m_adc_soc_quantity = config.adc_soc_quantity;
m_adc_soc_counter = 0;
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/config.fpwm;
//
while(m_timer_period>(float)(32767.0))
{
m_clkdiv++;
if(m_clkdiv >= 8)
{
m_clkdiv = 0;
m_hspclkdiv++;
//
}//if
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/config.fpwm;
//
}//while
//
m_timer_step = (m_clock_prescale_list[m_clkdiv] * m_high_speed_clock_prescale[m_hspclkdiv])/m_fcpu;
m_tbprd = (Uint16)m_timer_period;
m_cmpr_sync = m_tbprd - (Uint16)(config.pulse_sync/m_timer_step);
m_cmpr_adc_width = (Uint16)((float)(config.pulse_adc_soc/m_timer_step));
//m_cmpr_adc_step = (Uint16)(m_tbprd/config.adc_soc_quantity);
m_cmpr_adc_step = (Uint16)((float)((float)m_timer_period/((float)config.adc_soc_quantity)));
m_cmpr_adc_offset = (Uint16)((float)(m_timer_period * config.adc_soc_offset));
m_time_sample_adc = m_timer_step * ((float)m_cmpr_adc_step);
status.all = 0x0001;
//
//
EPwm1Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm1Regs.TBCTL.bit.CLKDIV = m_clkdiv;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
EPwm1Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm2Regs.TBPRD = m_tbprd;
EPwm2Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
// EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_offset; // Set compare A value
EPwm5Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm5Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
EPwm5Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
// Setup TBCLK
EPwm6Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm6Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
EPwm6Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
//
}
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::set_actions()
{
// Set EPWM1 actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;
//EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on event A, up count
//EPwm1Regs.AQCTLA.bit.PRD = AQ_SET;
//
// Set EPWM5 actions
EPwm5Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm5Regs.AQCTLB.bit.PRD = AQ_CLEAR;
//EPwm5Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2B on event B, up count
//EPwm5Regs.AQCTLB.bit.PRD = AQ_SET;
//
// Set EPWM6 actions
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count
EPwm6Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm6Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm6Regs.AQCTLB.bit.PRD = AQ_CLEAR;
//EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on event A, up count
//EPwm6Regs.AQCTLA.bit.PRD = AQ_SET;
//EPwm6Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2B on event B, up count
//EPwm6Regs.AQCTLB.bit.PRD = AQ_SET;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::clear_actions()
{
// Clear actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
EPwm1Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
//
// Set EPWM5 actions
EPwm5Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
EPwm5Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
//
// Set EPWM6 actions
EPwm6Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
EPwm6Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
EPwm6Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
EPwm6Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWM::get_time_sample_adc()
{
return m_time_sample_adc;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm1_adc_drive()
{
m_adc_soc_counter = 0;
m_cmpr_adc_start = m_cmpr_adc_offset;
m_cmpr_adc_stop = m_cmpr_adc_offset + m_cmpr_adc_width;
//
//new_cycle = 1;
//adc_soc = 0;
//adc_ready = 0;
status.all = 0x001;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_start; // Set compare A value
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_start;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm2_adc_drive()
{
(this->*_epwm2_adc_drive)();
//
}//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::_epwm2_adc_drive_mode_start()
{
//new_cycle = 0;
//adc_soc = 1;
//adc_ready = 0;
status.all = 0x002;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_stop; // Set compare A value
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_stop;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::_epwm2_adc_drive_mode_stop()
{
m_adc_soc_counter++;
m_cmpr_adc_start += m_cmpr_adc_step;
m_cmpr_adc_stop += m_cmpr_adc_step;
//new_cycle = 0;
//adc_soc = 0;
//adc_ready = 1;
status.all = 0x004;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_start; // Set compare A value
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_start;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm1_interrupt_ack()
{
EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm2_interrupt_ack()
{
EPwm2Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//
}//
//
} /* namespace DSP28335 */