diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..2e1311c --- /dev/null +++ b/.cproject @@ -0,0 +1,215 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/.gitignore b/.gitignore index b7c6d2b..e437788 100644 --- a/.gitignore +++ b/.gitignore @@ -26,5 +26,5 @@ SysConfig/ *.bak # Файлы проекта (опционально) -.project -.cproject \ No newline at end of file +# .project +# .cproject \ No newline at end of file diff --git a/.project b/.project new file mode 100644 index 0000000..ee0fcf2 --- /dev/null +++ b/.project @@ -0,0 +1,41 @@ + + + CCS-Students + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + CCS_Libs + $%7BTI_PRODUCTS_DIR__TIREX%7D/controlSUITE/libs + + + FAST_FPU32 + $%7BTI_PRODUCTS_DIR__TIREX%7D/controlSUITE/libs/math/FPUfastRTS/V100/lib + + + TMS320F_2833x_HEADERS + $%7BCOM_TI_C2000WARE_INSTALL_DIR%7D/device_support/f2833x + + + diff --git a/DSP28335/CPUBase.cpp b/DSP28335/CPUBase.cpp new file mode 100644 index 0000000..c35f429 --- /dev/null +++ b/DSP28335/CPUBase.cpp @@ -0,0 +1,34 @@ +/* + * CPUBase.cpp + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + + +#include "DSP28335/CPUBase.h" + +namespace DSP28335 +{ + +//CONSTRUCTOR +CPUBase::CPUBase(): + m_mode(DSP28335::CPUBase::UNDEFINED), + m_status(false) +// +{}//end CONSTRUCTOR +// +DSP28335::CPUBase::mode_t DSP28335::CPUBase::get_mode() const +{ + + return m_mode; + // +}//end +// +bool DSP28335::CPUBase::compare(DSP28335::CPUBase::mode_t mode) const +{ + return m_mode == mode; + // +}//end +// +} /* namespace DSP28335 */ diff --git a/DSP28335/CPUBase.h b/DSP28335/CPUBase.h new file mode 100644 index 0000000..d6278b4 --- /dev/null +++ b/DSP28335/CPUBase.h @@ -0,0 +1,50 @@ +/* + * CPUBase.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include +#include +// +#include "F28335/DSP28x_Project.h" + + +#include "RUDRIVEFRAMEWORK/DataType.h" +#include "RUDRIVEFRAMEWORK/SystemDefinitions.h" + + +#ifndef DSP28335_CPUBase_H_ +#define DSP28335_CPUBase_H_ + +namespace DSP28335 +{ + +struct CPUBaseSetup +{ + pGPIO_FUNCTION gpio_setup; + CPUBaseSetup(): + gpio_setup(0) + {} +};//CPUBaseSetup + + +class CPUBase +{ +public: + enum mode_t {UNDEFINED=0, OPERATIONAL=1}; +protected: + mode_t m_mode; + bool m_status; +public: + CPUBase(); +public: + mode_t get_mode() const; + bool compare(mode_t mode) const; + // +};// class + +} /* namespace DSP28335 */ + +#endif /* DSP28335_CPUBase_H_ */ diff --git a/DSP28335/CPUTimers.cpp b/DSP28335/CPUTimers.cpp new file mode 100644 index 0000000..9d8355a --- /dev/null +++ b/DSP28335/CPUTimers.cpp @@ -0,0 +1,48 @@ +/* + * CPUTimers.cpp + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "DSP28335/CPUTimers.h" + +namespace DSP28335 +{ +//CONSTRUCTOR +CPUTimers::CPUTimers(CPUTIMER_VARS& CPUTimer): + DSP28335::CPUBase(), + CPUTimer(CPUTimer) +// +{}//end CONSTRUCTOR + +void CPUTimers::setup(const CPUTimersSetup& setup) +{ + if(m_mode == DSP28335::CPUBase::UNDEFINED) + { + InitCpuTimers(); + ConfigCpuTimer(&CPUTimer, setup.frequency, setup.period); // 1ms + // + m_mode = DSP28335::CPUBase::OPERATIONAL; + // + }//end if + // +}//end +// +// #pragma CODE_SECTION("ramfuncs"); +void CPUTimers::start() +{ + // + CPUTimer.RegsAddr->TCR.bit.TSS = 0; + // +}//end +// +// #pragma CODE_SECTION("ramfuncs"); +void CPUTimers::interrupt_ack() +{ + // Acknowledge this interrupt to receive more interrupts from group 1 + PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; + // +}//end +// +} /* namespace DSP28335 */ diff --git a/DSP28335/CPUTimers.h b/DSP28335/CPUTimers.h new file mode 100644 index 0000000..3a843db --- /dev/null +++ b/DSP28335/CPUTimers.h @@ -0,0 +1,45 @@ +/* + * CPUTimers.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + + +#include "F28335/DSP28x_Project.h" + +#include "DSP28335/CPUBase.h" + +#ifndef DSP28335_CPUTIMERS_H_ +#define DSP28335_CPUTIMERS_H_ + +namespace DSP28335 +{ + +struct CPUTimersSetup +{ + float frequency; + float period; + CPUTimersSetup(): + frequency(150.0), + period(1000.0) + {} +};//end CPUTimersSetup + + +class CPUTimers: public DSP28335::CPUBase +{ +public: + CPUTIMER_VARS& CPUTimer; +public: + CPUTimers(CPUTIMER_VARS& CPUTimer); + void setup(const CPUTimersSetup& setup); +public: + void start(); + void interrupt_ack(); + // +};//end class CPUTimers + +} /* namespace DSP28335 */ + +#endif /* DSP28335_CPUTIMERS_H_ */ diff --git a/DSP28335/GPIO.cpp b/DSP28335/GPIO.cpp new file mode 100644 index 0000000..cd04eb1 --- /dev/null +++ b/DSP28335/GPIO.cpp @@ -0,0 +1,796 @@ +/* + * GPIO.cpp + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "DSP28335/GPIO.h" + +namespace DSP28335 +{ + +//CONSTRUCTOR +GPIO::GPIO(): + DSP28335::CPUBase() +// +{}//end CONSTRUCTOR + + + + +//EPWM +// #pragma CODE_SECTION("ramfuncs"); +void GPIO::gpio_epwm_setup() +{ + EALLOW; + // + // General Synchronization Signal GENSYNC - EPWM1A - GPIO0 + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A) + GpioDataRegs.GPACLEAR.bit.GPIO0 = 1; // Clear EPWM1A + GpioCtrlRegs.GPADIR.bit.GPIO0 = 0; // Output - EPWM1A + // + // Phase A (U) Synchronization Signal - EPWM5B - GPIO9 + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Disable pull-up on GPIO9 (EPWM5B) + GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; // Clear EPWM5B + GpioCtrlRegs.GPADIR.bit.GPIO9 = 0; // Output - EPWM5B + // + // Phase B (V) Synchronization Signal - EPWM6A - GPIO10 + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Disable pull-up on GPIO10 (EPWM6A) + GpioDataRegs.GPACLEAR.bit.GPIO10 = 1; // Clear EPWM6A + GpioCtrlRegs.GPADIR.bit.GPIO10 = 0; // Output - EPWM6A + // + // Phase C (W) Synchronization Signal - EPWM6B - GPIO11 + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO9 as EPWM6B + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Disable pull-up on GPIO11 (EPWM6B) + GpioDataRegs.GPACLEAR.bit.GPIO11 = 1; // Clear EPWM6B + GpioCtrlRegs.GPADIR.bit.GPIO11 = 0; // Output - EPWM6B + // + EDIS; + // +}//end +// + +//CAN Inteface +void GPIO::gpio_cana_setup() +{ + EALLOW; + // + // Enable CANA on GPIO18, CPIO19 + // CANRXA - GPIO18 + // CANTXA - GPIO19 + // + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pullup on GPIO18 + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // GPIO18 = CANRXA + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input + GpioCtrlRegs.GPADIR.bit.GPIO18 = 0; // GPIO18 = 0/1 - input/output + GpioDataRegs.GPASET.bit.GPIO18 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO18 = 0; // Clear output + // + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pullup on GPIO19 + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // GPIO19 = CANTXA + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 0; // Asynch input + GpioCtrlRegs.GPADIR.bit.GPIO19 = 0; // GPIO19 = 0/1 - input/output + GpioDataRegs.GPASET.bit.GPIO19 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO19 = 0; // Clear output + // + EDIS; + // +}//end +// +void GPIO::gpio_canb_setup() +{ + EALLOW; + // + // Enable CANB on GPIO16, CPIO17 + // CANTXB - GPIO16 + // CANRXB - GPIO17 + // + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16 + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // GPIO16 = CANTXA + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 0; // Asynch input + GpioCtrlRegs.GPADIR.bit.GPIO16 = 0; // GPIO16 = 0/1 - input/output + GpioDataRegs.GPASET.bit.GPIO16 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO16 = 0; // Clear output + // + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pullup on GPIO17 + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // GPIO17 = CANRXA + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input + GpioCtrlRegs.GPADIR.bit.GPIO17 = 0; // GPIO17 = 0/1 - input/output + GpioDataRegs.GPASET.bit.GPIO17 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO17 = 0; // Clear output + // + EDIS; + // +}//end +// + +//SCIA +void GPIO::gpio_scia_setup() +{}// + +// +//RS485 - SCIB +void GPIO::gpio_scib_setup() +{ + EALLOW; + // + // Enable SCI-B on GPIO21, GPIO22, GPIO23 - RS485 + // SCIENBLB - GPIO21 + // SCITXDB - GPIO22 + // SCIRXDB - GPIO23 + // + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; // GPIO22 = SCITXDB + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO22 + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Asynch input + GpioCtrlRegs.GPADIR.bit.GPIO22 = 0; // GPIO22 = 0/1 - input/output + // + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; // GPIO23 = SCIRXDB + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pullup on GPIO23 + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input + GpioCtrlRegs.GPADIR.bit.GPIO23 = 0; // GPIO23 = 0/1 - input/output + // + EDIS; + // +}//end +// +void GPIO::gpio_scib_re_de_setup() +{ + EALLOW; + // + // Enable SCI-B on GPIO21, GPIO22, GPIO23 - RS485 + // SCIENBLB - GPIO21 + // SCITXDB - GPIO22 + // SCIRXDB - GPIO23 + // + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0; // GPIO21 = DE-RS485 + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pullup on GPIO21 + GpioCtrlRegs.GPADIR.bit.GPIO21 = 1; // GPIO21 = 0/1 - input/output + GpioDataRegs.GPASET.bit.GPIO21 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO21 = 0; // Clear output + // + EDIS; + // +}//end +// +// #pragma CODE_SECTION("ramfuncs"); +void GPIO::gpio_scib_re_de_set() +{ + //set GPIO21 + GpioDataRegs.GPASET.bit.GPIO21 = 1; + // +}// +// +// #pragma CODE_SECTION("ramfuncs"); +void GPIO::gpio_scib_re_de_clear() +{ + //clear GPIO21 + GpioDataRegs.GPACLEAR.bit.GPIO21 = 1; + // +}// +// +//RS485 - SCIC +void GPIO::gpio_scic_setup() +{ + EALLOW; + // + // Enable SCI-C on GPIO61, GPIO62, GPIO63 - RS485 + // SCIENBLC - GPIO61 + // SCIRXDC - GPIO62 + // SCITXDC - GPIO63 + // + GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0; // GPIO61 = DE-RS485 + GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pullup on GPIO61 + GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1; // GPIO61 = 0/1 - input/output + GpioDataRegs.GPBSET.bit.GPIO61 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO61 = 0; // Clear output + // + GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // GPIO62 = SCIRXDC + GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pullup on GPIO62 + GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input + GpioCtrlRegs.GPBDIR.bit.GPIO62 = 0; // GPIO62 = 0/1 - input/output + // + GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // GPIO63 = SCITXDC + GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pullup on GPIO63 + GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0; // Asynch input + GpioCtrlRegs.GPBDIR.bit.GPIO63 = 0; // GPIO63 = 0/1 - input/output + // + EDIS; + // +}//end + + +//FRAM - SPIA +void GPIO::gpio_spia_setup() +{ + EALLOW; + // + //GPIO54 - SPISIMOA + //GPIO55 - SPISOMIA + //GPIO56 - SPICLKA + //GPIO57 - SPISTEA + //GPIO58 - SPISWP - Write Protect + // + GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA + GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA) + GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO54 (SPISIMOA) + GpioCtrlRegs.GPBDIR.bit.GPIO54 = 1; // GPIO54 = 0/1 - input/output + // + GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA + GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA) + GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO55 (SPISOMIA) + GpioCtrlRegs.GPBDIR.bit.GPIO55 = 0; // GPIO55 = 0/1 - input/output + // + GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA + GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA) + GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO56 (SPICLKA) + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1; // GPIO56 = 0/1 - input/output + // + GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA + GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA) + GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO57 (SPISTEA) + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1; // GPIO57 = 0/1 - input/output + // + GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0; // Configure GPIO58 as GPIO + GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58 + GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58 + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1; // GPIO58 = 0/1 - input/output + // + EDIS; + // +}// +// +void GPIO::gpio_spia_write_protect_set() +{ + GpioDataRegs.GPBSET.bit.GPIO58 = 1; // Set output + // +}// +// +void GPIO::gpio_spia_write_protect_clear() +{ + GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1; // Set output + // +}// +// + + + +// +void GPIO::gpio_eqep_setup() +{ + EALLOW; + // + // Enable eQEP on GPIO50, CPIO51 + // EQEP1A - GPIO50 + // EQEP1B - GPIO51 + // + GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pullup on GPIO50 + GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // GPIO50 = EQEP1A + GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Asynch input + GpioCtrlRegs.GPBDIR.bit.GPIO50 = 0; // GPIO50 = 0/1 - input/output + GpioDataRegs.GPBSET.bit.GPIO50 = 1; // + GpioDataRegs.GPBCLEAR.bit.GPIO50 = 0; // Clear output + // + GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pullup on GPIO51 + GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // GPIO51 = EQEP1B + GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Asynch input + GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0; // GPIO51 = 0/1 - input/output + GpioDataRegs.GPBSET.bit.GPIO51 = 1; // + GpioDataRegs.GPBCLEAR.bit.GPIO51 = 0; // Clear output + // + EDIS; + // +}// +// + +void GPIO::gpio_xintf_16bit_setup() +{ + EALLOW; + // + // XINF - external interface + // + // GPIO34 - XREADY + GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pullup on GPIO34 + GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0; // GPIO34 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // GPIO34 = XREADY + GpioDataRegs.GPBSET.bit.GPIO34 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO34 = 0; // Clear output + // + // GPIO35 - XR/nW + GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pullup on GPIO35 + GpioCtrlRegs.GPBDIR.bit.GPIO35 = 1; // GPIO35 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // GPIO35 = XR/nW + GpioDataRegs.GPBSET.bit.GPIO35 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO35 = 0; // Clear output + // + // GPIO36 - nXZCS0 + GpioCtrlRegs.GPBPUD.bit.GPIO36 = 0; // Enable pullup on GPIO36 + GpioCtrlRegs.GPBDIR.bit.GPIO36 = 1; // GPIO36 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO36 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // GPIO36 = nXZCS0 + GpioDataRegs.GPBSET.bit.GPIO36 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO36 = 0; // Clear output + // + // GPIO28 - nXZCS6 + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28 + GpioCtrlRegs.GPADIR.bit.GPIO28 = 1; // GPIO28 = 0/1 - input/output + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 0; // Asynch input + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // GPIO28 = nXZCS6 + GpioDataRegs.GPASET.bit.GPIO28 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO28 = 0; // Clear output + // + // GPIO37 - nXZCS7 + GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pullup on GPIO37 + GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1; // GPIO37 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // GPIO37 = nXZCS7 + GpioDataRegs.GPBSET.bit.GPIO37 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO37 = 0; // Clear output + // + // GPIO38 - nXWE0 + GpioCtrlRegs.GPBPUD.bit.GPIO38 = 0; // Enable pullup on GPIO38 + GpioCtrlRegs.GPBDIR.bit.GPIO38 = 1; // GPIO38 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO38 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // GPIO38 = nXWE0 + GpioDataRegs.GPBSET.bit.GPIO38 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO38 = 0; // Clear output + // + // GPIO39 - XA16 + GpioCtrlRegs.GPBPUD.bit.GPIO39 = 0; // Enable pullup on GPIO39 + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0; // GPIO39 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO39 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // GPIO39 = XA16 + GpioDataRegs.GPBSET.bit.GPIO39 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO39 = 0; // Clear output + // + // GPIO40 - XA0 + GpioCtrlRegs.GPBPUD.bit.GPIO40 = 0; // Enable pullup on GPIO40 + GpioCtrlRegs.GPBDIR.bit.GPIO40 = 0; // GPIO40 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO40 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // GPIO40 = XA0 + GpioDataRegs.GPBSET.bit.GPIO40 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO40 = 0; // Clear output + // + // GPIO41 - XA1 + GpioCtrlRegs.GPBPUD.bit.GPIO41 = 0; // Enable pullup on GPIO41 + GpioCtrlRegs.GPBDIR.bit.GPIO41 = 0; // GPIO41 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO41 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // GPIO41 = XA1 + GpioDataRegs.GPBSET.bit.GPIO41 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO41 = 0; // Clear output + // + // GPIO42 - XA2 + GpioCtrlRegs.GPBPUD.bit.GPIO42 = 0; // Enable pullup on GPIO42 + GpioCtrlRegs.GPBDIR.bit.GPIO42 = 0; // GPIO42 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO42 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // GPIO42 = XA2 + GpioDataRegs.GPBSET.bit.GPIO42 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO42 = 0; // Clear output + // + // GPIO43 - XA3 + GpioCtrlRegs.GPBPUD.bit.GPIO43 = 0; // Enable pullup on GPIO43 + GpioCtrlRegs.GPBDIR.bit.GPIO43 = 0; // GPIO43 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO43 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // GPIO43 = XA3 + GpioDataRegs.GPBSET.bit.GPIO43 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO43 = 0; // Clear output + // + // GPIO44 - XA4 + GpioCtrlRegs.GPBPUD.bit.GPIO44 = 0; // Enable pullup on GPIO44 + GpioCtrlRegs.GPBDIR.bit.GPIO44 = 0; // GPIO44 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO44 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // GPIO44 = XA4 + GpioDataRegs.GPBSET.bit.GPIO44 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO44 = 0; // Clear output + // + // GPIO45 - XA5 + GpioCtrlRegs.GPBPUD.bit.GPIO45 = 0; // Enable pullup on GPIO45 + GpioCtrlRegs.GPBDIR.bit.GPIO45 = 0; // GPIO45 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO45 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // GPIO45 = XA5 + GpioDataRegs.GPBSET.bit.GPIO45 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO45 = 0; // Clear output + // + // GPIO46 - XA6 + GpioCtrlRegs.GPBPUD.bit.GPIO46 = 0; // Enable pullup on GPIO46 + GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0; // GPIO46 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO46 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // GPIO46 = XA6 + GpioDataRegs.GPBSET.bit.GPIO46 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO46 = 0; // Clear output + // + // GPIO47 - XA7 + GpioCtrlRegs.GPBPUD.bit.GPIO47 = 0; // Enable pullup on GPIO47 + GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0; // GPIO47 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO47 = 0; // Asynch input + GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // GPIO47 = XA7 + GpioDataRegs.GPBSET.bit.GPIO47 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO47 = 0; // Clear output + // + // GPIO80 - XA8 + GpioCtrlRegs.GPCPUD.bit.GPIO80 = 0; // Enable pullup on GPIO80 + GpioCtrlRegs.GPCDIR.bit.GPIO80 = 0; // GPIO80 = 0/1 - input/output + GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 2; // GPIO80 = XA8 + GpioDataRegs.GPCSET.bit.GPIO80 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO80 = 0; // Clear output + // + // GPIO81 - XA9 + GpioCtrlRegs.GPCPUD.bit.GPIO81 = 0; // Enable pullup on GPIO81 + GpioCtrlRegs.GPCDIR.bit.GPIO81 = 0; // GPIO81 = 0/1 - input/output + GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 2; // GPIO81 = XA9 + GpioDataRegs.GPCSET.bit.GPIO81 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO81 = 0; // Clear output + // + // GPIO82 - XA10 + GpioCtrlRegs.GPCPUD.bit.GPIO82 = 0; // Enable pullup on GPIO82 + GpioCtrlRegs.GPCDIR.bit.GPIO82 = 0; // GPIO82 = 0/1 - input/output + GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 2; // GPIO82 = XA10 + GpioDataRegs.GPCSET.bit.GPIO82 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO82 = 0; // Clear output + // + // GPIO83 - XA11 + GpioCtrlRegs.GPCPUD.bit.GPIO83 = 0; // Enable pullup on GPIO83 + GpioCtrlRegs.GPCDIR.bit.GPIO83 = 0; // GPIO83 = 0/1 - input/output + GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 2; // GPIO83 = XA11 + GpioDataRegs.GPCSET.bit.GPIO83 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO83 = 0; // Clear output + // + // GPIO84 - XA12 + GpioCtrlRegs.GPCPUD.bit.GPIO84 = 0; // Enable pullup on GPIO84 + GpioCtrlRegs.GPCDIR.bit.GPIO84 = 0; // GPIO84 = 0/1 - input/output + GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2; // GPIO84 = XA12 + GpioDataRegs.GPCSET.bit.GPIO84 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO84 = 0; // Clear output + // + // GPIO85 - XA13 + GpioCtrlRegs.GPCPUD.bit.GPIO85 = 0; // Enable pullup on GPIO85 + GpioCtrlRegs.GPCDIR.bit.GPIO85 = 0; // GPIO85 = 0/1 - input/output + GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 2; // GPIO85 = XA13 + GpioDataRegs.GPCSET.bit.GPIO85 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO85 = 0; // Clear output + // + // GPIO86 - XA14 + GpioCtrlRegs.GPCPUD.bit.GPIO86 = 0; // Enable pullup on GPIO86 + GpioCtrlRegs.GPCDIR.bit.GPIO86 = 0; // GPIO86 = 0/1 - input/output + GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 2; // GPIO86 = XA14 + GpioDataRegs.GPCSET.bit.GPIO86 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO86 = 0; // Clear output + // + // GPIO87 - XA15 + GpioCtrlRegs.GPCPUD.bit.GPIO87 = 0; // Enable pullup on GPIO87 + GpioCtrlRegs.GPCDIR.bit.GPIO87 = 0; // GPIO87 = 0/1 - input/output + GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 2; // GPIO87 = XA15 + GpioDataRegs.GPCSET.bit.GPIO87 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO87 = 0; // Clear output + // + // GPIO39 - XA16 + GpioCtrlRegs.GPBPUD.bit.GPIO39 = 0; // Enable pullup on GPIO39 + GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0; // GPIO39 = 0/1 - input/output + GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // GPIO39 = XA16 + GpioDataRegs.GPBSET.bit.GPIO39 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO39 = 0; // Clear output + // + // GPIO31 - XA17 + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pullup on GPIO31 + GpioCtrlRegs.GPADIR.bit.GPIO31 = 0; // GPIO31 = 0/1 - input/output + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // GPIO31 = XA17 + GpioDataRegs.GPASET.bit.GPIO31 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO31 = 0; // Clear output + // + // GPIO30 - XA18 + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pullup on GPIO30 + GpioCtrlRegs.GPADIR.bit.GPIO30 = 0; // GPIO30 = 0/1 - input/output + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // GPIO30 = XA18 + GpioDataRegs.GPASET.bit.GPIO30 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO30 = 0; // Clear output + + // GPIO29 - XA19 + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29 + GpioCtrlRegs.GPADIR.bit.GPIO29 = 0; // GPIO29 = 0/1 - input/output + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // GPIO29 = XA19 + GpioDataRegs.GPASET.bit.GPIO29 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO29 = 0; // Clear output + // + // GPIO64 - XD15 + GpioCtrlRegs.GPCPUD.bit.GPIO64 = 0; // Enable pullup on GPIO64 + GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0; // GPIO64 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 2; // GPIO64 = XD + GpioDataRegs.GPCSET.bit.GPIO64 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO64 = 0; // Clear output + // + // GPIO65 - XD14 + GpioCtrlRegs.GPCPUD.bit.GPIO65 = 0; // Enable pullup on GPIO65 + GpioCtrlRegs.GPCDIR.bit.GPIO65 = 0; // GPIO65 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 2; // GPIO65 = XD14 + GpioDataRegs.GPCSET.bit.GPIO65 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO65 = 0; // Clear output + // + // GPIO66 - XD13 + GpioCtrlRegs.GPCPUD.bit.GPIO66 = 0; // Enable pullup on GPIO66 + GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0; // GPIO66 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 2; // GPIO66 = XD13 + GpioDataRegs.GPCSET.bit.GPIO66 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO66 = 0; // Clear output + // + // GPIO67 - XD12 + GpioCtrlRegs.GPCPUD.bit.GPIO67 = 0; // Enable pullup on GPIO67 + GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0; // GPIO67 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 2; // GPIO67 = XD12 + GpioDataRegs.GPCSET.bit.GPIO67 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO67 = 0; // Clear output + // + // GPIO68 - XD11 + GpioCtrlRegs.GPCPUD.bit.GPIO68 = 0; // Enable pullup on GPIO68 + GpioCtrlRegs.GPCDIR.bit.GPIO68 = 0; // GPIO68 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 2; // GPIO68 = XD11 + GpioDataRegs.GPCSET.bit.GPIO68 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO68 = 0; // Clear output + // + // GPIO69 - XD10 + GpioCtrlRegs.GPCPUD.bit.GPIO69 = 0; // Enable pullup on GPIO69 + GpioCtrlRegs.GPCDIR.bit.GPIO69 = 0; // GPIO69 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 2; // GPIO69 = XD10 + GpioDataRegs.GPCSET.bit.GPIO69 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO69 = 0; // Clear output + // + // GPIO70 - XD9 + GpioCtrlRegs.GPCPUD.bit.GPIO70 = 0; // Enable pullup on GPIO70 + GpioCtrlRegs.GPCDIR.bit.GPIO70 = 0; // GPIO70 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 2; // GPIO70 = XD9 + GpioDataRegs.GPCSET.bit.GPIO70 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO70 = 0; // Clear output + // + // GPIO71 - XD8 + GpioCtrlRegs.GPCPUD.bit.GPIO71 = 0; // Enable pullup on GPIO71 + GpioCtrlRegs.GPCDIR.bit.GPIO71 = 0; // GPIO71 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 2; // GPIO71 = XD8 + GpioDataRegs.GPCSET.bit.GPIO71 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO71 = 0; // Clear output + // + // GPIO72 - XD7 + GpioCtrlRegs.GPCPUD.bit.GPIO72 = 0; // Enable pullup on GPIO72 + GpioCtrlRegs.GPCDIR.bit.GPIO72 = 0; // GPIO72 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 2; // GPIO72 = XD7 + GpioDataRegs.GPCSET.bit.GPIO72 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO72 = 0; // Clear output + // + // GPIO73 - XD6 + GpioCtrlRegs.GPCPUD.bit.GPIO73 = 0; // Enable pullup on GPIO73 + GpioCtrlRegs.GPCDIR.bit.GPIO73 = 0; // GPIO73 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 2; // GPIO73 = XD6 + GpioDataRegs.GPCSET.bit.GPIO73 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO73 = 0; // Clear output + // + // GPIO74 - XD5 + GpioCtrlRegs.GPCPUD.bit.GPIO74 = 0; // Enable pullup on GPIO74 + GpioCtrlRegs.GPCDIR.bit.GPIO74 = 0; // GPIO74 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 2; // GPIO74 = XD5 + GpioDataRegs.GPCSET.bit.GPIO74 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO74 = 0; // Clear output + // + // GPIO75 - XD4 + GpioCtrlRegs.GPCPUD.bit.GPIO75 = 0; // Enable pullup on GPIO75 + GpioCtrlRegs.GPCDIR.bit.GPIO75 = 0; // GPIO75 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 2; // GPIO75 = XD4 + GpioDataRegs.GPCSET.bit.GPIO75 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO75 = 0; // Clear output + // + // GPIO76 - XD3 + GpioCtrlRegs.GPCPUD.bit.GPIO76 = 0; // Enable pullup on GPIO76 + GpioCtrlRegs.GPCDIR.bit.GPIO76 = 0; // GPIO76 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 2; // GPIO76 = XD3 + GpioDataRegs.GPCSET.bit.GPIO76 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO76 = 0; // Clear output + // + // GPIO77 - XD2 + GpioCtrlRegs.GPCPUD.bit.GPIO77 = 0; // Enable pullup on GPIO77 + GpioCtrlRegs.GPCDIR.bit.GPIO77 = 0; // GPIO77 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 2; // GPIO77 = XD2 + GpioDataRegs.GPCSET.bit.GPIO77 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO77 = 0; // Clear output + // + // GPIO78 - XD1 + GpioCtrlRegs.GPCPUD.bit.GPIO78 = 0; // Enable pullup on GPIO78 + GpioCtrlRegs.GPCDIR.bit.GPIO78 = 0; // GPIO78 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 2; // GPIO78 = XD1 + GpioDataRegs.GPCSET.bit.GPIO78 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO78 = 0; // Clear output + // + // GPIO79 - XD0 + GpioCtrlRegs.GPCPUD.bit.GPIO79 = 0; // Enable pullup on GPIO79 + GpioCtrlRegs.GPCDIR.bit.GPIO79 = 0; // GPIO79 = 0/1 - input/output + GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 2; // GPIO79 = XD0 + GpioDataRegs.GPCSET.bit.GPIO79 = 0; // + GpioDataRegs.GPCCLEAR.bit.GPIO79 = 0; // Clear output + // + EDIS; + // +}// +// +void GPIO::gpio_xintf_32bit_setup() +{}// +// + + +void GPIO::gpio_dicrete_outputs_setup() +{ + EALLOW; + // + // GPIO1 + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; // GPIO1 + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Enable pullup on GPIO1 + GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; // GPIO1 = 0/1 - input/output + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Asynch input + GpioDataRegs.GPASET.bit.GPIO1 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO1 = 0; // Clear output + // + // GPIO2 + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0; // GPIO2 + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Enable pullup on GPIO2 + GpioCtrlRegs.GPADIR.bit.GPIO2 = 1; // GPIO2 = 0/1 - input/output + GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 0; // Asynch input + GpioDataRegs.GPASET.bit.GPIO2 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO2 = 0; // Clear output + // + // GPIO3 + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0; // GPIO3 + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Enable pullup on GPIO3 + GpioCtrlRegs.GPADIR.bit.GPIO3 = 1; // GPIO3 = 0/1 - input/output + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Asynch input + GpioDataRegs.GPASET.bit.GPIO3 = 0; // + GpioDataRegs.GPACLEAR.bit.GPIO3 = 0; // Clear output + // + // + // GPIO54 + GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 0; // GPIO54 + GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pullup on GPIO54 + GpioCtrlRegs.GPBDIR.bit.GPIO54 = 1; // GPIO54 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; // Asynch input + GpioDataRegs.GPBSET.bit.GPIO54 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO54 = 0; // Clear output + // + // GPIO56 + GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 0; // GPIO56 + GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pullup on GPIO56 + GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1; // GPIO56 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 0; // Asynch input + GpioDataRegs.GPBSET.bit.GPIO56 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO56 = 0; // Clear output + // + // GPIO57 + GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 0; // GPIO57 + GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pullup on GPIO57 + GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1; // GPIO57 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 0; // Asynch input + GpioDataRegs.GPBSET.bit.GPIO57 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO57 = 0; // Clear output + // + // GPIO58 + GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0; // GPIO58 + GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pullup on GPIO58 + GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1; // GPIO58 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 0; // Asynch input + GpioDataRegs.GPBSET.bit.GPIO58 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO58 = 0; // Clear output + // + // GPIO61 + GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0; // GPIO61 + GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pullup on GPIO61 + GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1; // GPIO61 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 0; // Asynch input + GpioDataRegs.GPBSET.bit.GPIO61 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO61 = 0; // Clear output + // + EDIS; + // +}// +// + +void GPIO::ext_adc_start_convertion_setup() +{ + EALLOW; + // GPIO33 + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0; // GPIO33 + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33 + GpioCtrlRegs.GPBDIR.bit.GPIO33 = 1; // GPIO33 = 0/1 - input/output + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0; // Asynch input + GpioDataRegs.GPBSET.bit.GPIO33 = 0; // + GpioDataRegs.GPBCLEAR.bit.GPIO33 = 0; // Clear output + // + EDIS; + // +}// +// +void GPIO::set_ext_adc_start_convertion() +{ + //set GPIO33 + GpioDataRegs.GPBSET.bit.GPIO33 = 1; + // + // +}// +// +void GPIO::clear_ext_adc_start_convertion() +{ + //clear GPIO33 + GpioDataRegs.GPBCLEAR.bit.GPIO33 = 1; + // +}// +// +void GPIO::gpio_hard_fault_setup() +{ + EALLOW; + // GPIO4 - Fault A + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0; // GPIO4 + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4 + GpioCtrlRegs.GPADIR.bit.GPIO4 = 0; // GPIO4 = 0/1 - input/output + GpioCtrlRegs.GPAQSEL1.bit.GPIO4 = 0; // Asynch input + // + // GPIO6 - Fault B + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO6 + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6 + GpioCtrlRegs.GPADIR.bit.GPIO6 = 0; // GPIO6 = 0/1 - input/output + GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Asynch input + // + // GPIO8 - Fault C + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO8 + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8 + GpioCtrlRegs.GPADIR.bit.GPIO8 = 0; // GPIO8 = 0/1 - input/output + GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0; // Asynch input + // + EDIS; + // +}// +// +// #pragma CODE_SECTION("ramfuncs"); +void GPIO::gpio_hard_fault_read(uint16_t& data) +{ + data = (uint16_t)((GpioDataRegs.GPADAT.bit.GPIO8 == 1 ? 0x4 : 0x0) | + (GpioDataRegs.GPADAT.bit.GPIO6 == 1 ? 0x2 : 0x0) | + (GpioDataRegs.GPADAT.bit.GPIO4 == 1 ? 0x1 : 0x0)); + // +}// +// + +// +// Analog Alarm Current Sensors +void GPIO::gpio_analog_fault_setup() +{ + EALLOW; + // GPIO12 - Analog Alarm 21 + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0; // GPIO12 + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12 + GpioCtrlRegs.GPADIR.bit.GPIO12 = 0; // GPIO4 = 0/1 - input/output + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Asynch input + // + // GPIO13 - Analog Alarm 22 + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0; // GPIO13 + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pullup on GPIO13 + GpioCtrlRegs.GPADIR.bit.GPIO13 = 0; // GPIO13 = 0/1 - input/output + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Asynch input + // + // GPIO20 - Analog Alarm 20 + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0; // GPIO20 + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pullup on GPIO20 + GpioCtrlRegs.GPADIR.bit.GPIO20 = 0; // GPIO20 = 0/1 - input/output + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Asynch input + // + EDIS; + // + // +}// +// +// #pragma CODE_SECTION("ramfuncs"); +void GPIO::gpio_analog_fault_read(uint16_t& data) +{ + data = (uint16_t)((GpioDataRegs.GPADAT.bit.GPIO12 == 1 ? 0x4 : 0x0) | + (GpioDataRegs.GPADAT.bit.GPIO13 == 1 ? 0x2 : 0x0) | + (GpioDataRegs.GPADAT.bit.GPIO20 == 1 ? 0x1 : 0x0)); + // +}// +// +} /* namespace DSP28335 */ diff --git a/DSP28335/GPIO.h b/DSP28335/GPIO.h new file mode 100644 index 0000000..923bdb5 --- /dev/null +++ b/DSP28335/GPIO.h @@ -0,0 +1,75 @@ +/* + * GPIO.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "F28335/DSP28x_Project.h" + +#include "DSP28335/CPUBase.h" + +#ifndef DSP28335_GPIO_H_ +#define DSP28335_GPIO_H_ + +namespace DSP28335 +{ + +typedef void (*pGPIO_FUNCTION)(); + +class GPIO: public DSP28335::CPUBase +{ +public: + GPIO(); + //EPWM + static void gpio_epwm_setup(); + // + //CAN Inteface + static void gpio_cana_setup(); + static void gpio_canb_setup(); + // + //SCIA + static void gpio_scia_setup(); + // + //RS485 - SCIB external - HMI + static void gpio_scib_setup(); + static void gpio_scib_re_de_setup(); + static void gpio_scib_re_de_set(); + static void gpio_scib_re_de_clear(); + // + //RS485 - SCIC internal + static void gpio_scic_setup(); + // + //FRAM - SPIA + static void gpio_spia_setup(); + static void gpio_spia_write_protect_set(); + static void gpio_spia_write_protect_clear(); + // + // EQEP + static void gpio_eqep_setup(); + // + // XINTF + static void gpio_xintf_16bit_setup(); + static void gpio_xintf_32bit_setup(); + // + // GPIO + static void gpio_dicrete_outputs_setup(); + // + // EXTERNAL ADC + static void ext_adc_start_convertion_setup(); + static void set_ext_adc_start_convertion(); + static void clear_ext_adc_start_convertion(); + // + // Hard Fault + static void gpio_hard_fault_setup(); + static void gpio_hard_fault_read(uint16_t& data); + // + // Analog Fault Current Sensors + static void gpio_analog_fault_setup(); + static void gpio_analog_fault_read(uint16_t& data); + // +};//class GPIO() + +} /* namespace DSP28335 */ + +#endif /* DSP28335_GPIO_H_ */ diff --git a/DSP28335/MeasureTimeInterval.cpp b/DSP28335/MeasureTimeInterval.cpp new file mode 100644 index 0000000..fd3c150 --- /dev/null +++ b/DSP28335/MeasureTimeInterval.cpp @@ -0,0 +1,78 @@ +/* + * MeasureTimeInterval.cpp + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "DSP28335/MeasureTimeInterval.h" + +namespace DSP28335 +{ + +//Constructor +MeasureTimeInterval::MeasureTimeInterval(CPUTIMER_VARS& CPUTimer): + m_CPUTimer(CPUTimer), + m_time_interval((Uint32)0), + m_time_interval_previous((Uint32)0), + m_magic_number((Uint32)0) +{}//end Constructor + +// #pragma CODE_SECTION("ramfuncs"); +void MeasureTimeInterval::start(void) +{ + m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer + m_CPUTimer.RegsAddr->TCR.bit.TRB = 1; // Reload CPU Timer + m_CPUTimer.RegsAddr->TCR.bit.TSS = 0; // Start CPU Timer + // +}//end + +// #pragma CODE_SECTION("ramfuncs"); +void MeasureTimeInterval::stop(void) +{ + m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer + // + m_time_interval_previous = m_time_interval; + m_time_interval = m_CPUTimer.RegsAddr->PRD.all - m_CPUTimer.RegsAddr->TIM.all - m_magic_number; + // +}//end + +// #pragma CODE_SECTION("ramfuncs"); +Uint32 MeasureTimeInterval::interval(void) +{ + return m_CPUTimer.RegsAddr->PRD.all - m_CPUTimer.RegsAddr->TIM.all - m_magic_number; + // +}// +// + +// #pragma CODE_SECTION("ramfuncs"); +void MeasureTimeInterval::reset(void) +{ + m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer + m_CPUTimer.RegsAddr->PRD.all = 0xFFFFFFFF; + m_CPUTimer.RegsAddr->TCR.bit.TRB = 1; // Reload CPU Timer + // +}//end + +// #pragma CODE_SECTION("ramfuncs"); +void MeasureTimeInterval::inc_counter() +{ + m_CPUTimer.InterruptCount++; + // +}// +// +// #pragma CODE_SECTION("ramfuncs"); +void MeasureTimeInterval::reset_counter() +{ + m_CPUTimer.InterruptCount = (Uint32)0; + // +}// +// +void MeasureTimeInterval::set_magic(const Uint32 magic) +{ + m_magic_number = (Uint32)magic; + // +}//end +// + +} /* namespace DSP28335 */ diff --git a/DSP28335/MeasureTimeInterval.h b/DSP28335/MeasureTimeInterval.h new file mode 100644 index 0000000..c6f22e1 --- /dev/null +++ b/DSP28335/MeasureTimeInterval.h @@ -0,0 +1,38 @@ +/* + * MeasureTimeInterval.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "F28335/DSP28x_Project.h" + +#ifndef DSP28335_TIMEINTERVAL_H_ +#define DSP28335_TIMEINTERVAL_H_ + +namespace DSP28335 +{ + +class MeasureTimeInterval +{ +private: + CPUTIMER_VARS& m_CPUTimer; + Uint32 m_time_interval; + Uint32 m_time_interval_previous; + Uint32 m_magic_number; +public: + MeasureTimeInterval(CPUTIMER_VARS& CPUTimer); +public: + void start(void); + void stop(void); + Uint32 interval(void); + void reset(void); + void inc_counter(); + void reset_counter(); + void set_magic(const Uint32 magic); + // +};//end class MeasureTimeStartStop + +} /* namespace DSP28335 */ + +#endif /* DSP28335_TIMEINTERVAL_H_ */ diff --git a/DSP28335/SCIA.cpp b/DSP28335/SCIA.cpp new file mode 100644 index 0000000..5040b40 --- /dev/null +++ b/DSP28335/SCIA.cpp @@ -0,0 +1,144 @@ +/* + * SCIA.cpp + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "DSP28335/SCIA.h" + +namespace DSP28335 +{ +//CONSTRUCTOR +SCIA::SCIA(volatile struct SCI_REGS& SciRegs): + DSP28335::SCIBase(SciRegs) +// +{ + // set default + settings.config.baudrate = SCIA_BAUDRATE_DEFAULT; + settings.config.parity = SCIA_PARITY_DEFAULT; + settings.config.stopbits = SCIA_STOPBITS_DEFAULT; + settings.config.lenght = SCIA_LENGHT_DEFAULT; + settings.gpio_setup = SCIA_GPIO_SETUP_DEFAULT; + // +}//end CONSTRUCTOR + + +void SCIA::setup() +{ + // + get_default_configuration(settings.config); + _configure(settings.config); + // + _gpio_setup = settings.gpio_setup; + (*_gpio_setup)(); + // +}// +// +void SCIA::setup(DSP28335::SCISetup& setup) +{ + settings = setup; + _configure(settings.config); + // + _gpio_setup = settings.gpio_setup; + (*_gpio_setup)(); + // +}// +// +void SCIA::get_default_configuration(DSP28335::SCIConfiguration& config) +{ + config.baudrate = SCIA_BAUDRATE_DEFAULT; + config.parity = SCIA_PARITY_DEFAULT; + config.stopbits = SCIA_STOPBITS_DEFAULT; + config.lenght = SCIA_LENGHT_DEFAULT; + // +}// +// +void SCIA::get_configuration(DSP28335::SCIConfiguration& config) +{ + config = settings.config; + // +}// +// +void SCIA::set_configuration(DSP28335::SCIConfiguration& config) +{ + settings.config = config; + _configure(settings.config); + // +}// +// +bool SCIA::compare_configuration(DSP28335::SCIConfiguration& config) +{ + + return (settings.config.baudrate == config.baudrate) + & (settings.config.parity == config.parity) + & (settings.config.stopbits == config.stopbits) + & (settings.config.lenght == config.lenght); + // +}// +// +void SCIA::_configure(DSP28335::SCIConfiguration& config) +{ + // + // SCICTL1.5 - Software reset 0/1-reset/active state + SciRegs.SCICTL1.bit.SWRESET = 0x000; + // + // Reset FIFO's + SciRegs.SCIFFTX.all=0x8000; + // + // SCICCR.7 - Number of stop bits + if(config.stopbits == DSP28335::ONE){ SciRegs.SCICCR.bit.STOPBITS = 0x00;} + if(config.stopbits == DSP28335::TWO){ SciRegs.SCICCR.bit.STOPBITS = 0x01;} + // + // SCICCR.5 - Parity enable + // SCICCR.6 - Parity odd/even + if(config.parity == DSP28335::NO){ SciRegs.SCICCR.bit.PARITYENA = 0x00; SciRegs.SCICCR.bit.PARITY = 0x00;} + if(config.parity == DSP28335::ODD){ SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x00;} + if(config.parity == DSP28335::EVEN){ SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x01;} + // + // SCICCR.4 - Loop Back test mode enable + SciRegs.SCICCR.bit.LOOPBKENA = 0x00; + // + // SCICCR.3 - Idle - Address mode protocol + SciRegs.SCICCR.bit.ADDRIDLE_MODE = 0x00; + // + // SCICCR.2-0 - Character-length + if(config.lenght == DSP28335::LEN1){ SciRegs.SCICCR.bit.SCICHAR = 0x00;} + if(config.lenght == DSP28335::LEN2){ SciRegs.SCICCR.bit.SCICHAR = 0x01;} + if(config.lenght == DSP28335::LEN3){ SciRegs.SCICCR.bit.SCICHAR = 0x02;} + if(config.lenght == DSP28335::LEN4){ SciRegs.SCICCR.bit.SCICHAR = 0x03;} + if(config.lenght == DSP28335::LEN5){ SciRegs.SCICCR.bit.SCICHAR = 0x04;} + if(config.lenght == DSP28335::LEN6){ SciRegs.SCICCR.bit.SCICHAR = 0x05;} + if(config.lenght == DSP28335::LEN7){ SciRegs.SCICCR.bit.SCICHAR = 0x06;} + if(config.lenght == DSP28335::LEN8){ SciRegs.SCICCR.bit.SCICHAR = 0x07;} + // + // SCICTL1.6 - Receive error interrupt enable + SciRegs.SCICTL1.bit.RXERRINTENA =0x000; + // + SciRegs.SCICTL1.bit.RXENA =0x001; // Receiver enable + SciRegs.SCICTL1.bit.TXENA =0x001; // Transmitter enable + SciRegs.SCICTL1.bit.SLEEP =0x000; // Sleep 0/1 - disable/enable + SciRegs.SCICTL1.bit.TXWAKE =0x000; // Transmitter wake-up method select + + SciRegs.SCICTL2.bit.TXINTENA =0x0001; // SCITXBUF-register interrupt enable + SciRegs.SCICTL2.bit.RXBKINTENA =0x001; // Receiver-buffer/break interrupt enable + + // Ideal Baud BRR Actual Baud Error, % + // 2400 1952(07A0h) 2400 0 + // 4800 976(03D0h) 4798 -0,04 + // 9600 487(01E7h) 9606 0.06 + // 19200 243(00F3h) 19211 0.06 + // 38400 121(0079h) 38422 0.006 + + if(config.baudrate == DSP28335::BR2400){ SciRegs.SCIHBAUD = 0x0007; SciRegs.SCILBAUD = 0x00A0;} + if(config.baudrate == DSP28335::BR4800){ SciRegs.SCIHBAUD = 0x0003; SciRegs.SCILBAUD = 0x00D0;} + if(config.baudrate == DSP28335::BR9600){ SciRegs.SCIHBAUD = 0x0001; SciRegs.SCILBAUD = 0x00E7;} + if(config.baudrate == DSP28335::BR19200){ SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x00F3;} + if(config.baudrate == DSP28335::BR38400){ SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x0079;} + + // SCICTL1.5 - Relinquish SCI from Reset + SciRegs.SCICTL1.bit.SWRESET =0x001; + // +}// +// +} /* namespace DSP28335 */ diff --git a/DSP28335/SCIA.h b/DSP28335/SCIA.h new file mode 100644 index 0000000..f3e1e47 --- /dev/null +++ b/DSP28335/SCIA.h @@ -0,0 +1,58 @@ +/* + * SCIA.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ +#include "F28335/DSP28x_Project.h" + +#include "DSP28335/SCIBase.h" + +#ifndef DSP28335_SCIA_H_ +#define DSP28335_SCIA_H_ + + +#ifndef SCIA_BAUDRATE_DEFAULT +#define SCIA_BAUDRATE_DEFAULT (DSP28335::BR9600) +#endif + +#ifndef SCIA_PARITY_DEFAULT +#define SCIA_PARITY_DEFAULT (DSP28335::NO) +//#define SCIA_PARITY_DEFAULT (DSP28335::ODD) +//#define SCIA_PARITY_DEFAULT (DSP28335::EVEN) +#endif + +#ifndef SCIA_STOPBITS_DEFAULT +#define SCIA_STOPBITS_DEFAULT (DSP28335::ONE) +#endif + +#ifndef SCIA_LENGHT_DEFAULT +#define SCIA_LENGHT_DEFAULT (DSP28335::LEN8) +#endif + +#ifndef SCIA_GPIO_SETUP_DEFAULT +#define SCIA_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_scia_setup) +#endif + + +namespace DSP28335 +{ + +class SCIA: public DSP28335::SCIBase +{ +public: + SCIA(volatile struct SCI_REGS& SciRegs); + void setup(); + void setup(DSP28335::SCISetup& setup); + void get_default_configuration(DSP28335::SCIConfiguration& config); + void get_configuration(DSP28335::SCIConfiguration& config); + void set_configuration(DSP28335::SCIConfiguration& config); + bool compare_configuration(DSP28335::SCIConfiguration& config); +protected: + void _configure(DSP28335::SCIConfiguration& config); + // +};//end class SCIA + +} /* namespace DSP28335 */ + +#endif /* DSP28335_SCIA_H_ */ diff --git a/DSP28335/SCIB.cpp b/DSP28335/SCIB.cpp new file mode 100644 index 0000000..96cb8b8 --- /dev/null +++ b/DSP28335/SCIB.cpp @@ -0,0 +1,163 @@ +/* + * SCIB.cpp + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "DSP28335/SCIB.h" + +namespace DSP28335 +{ +//CONSTRUCTOR +SCIB::SCIB(volatile struct SCI_REGS& SciRegs): + DSP28335::SCIBase(SciRegs) +{ + // set default + settings.config.baudrate = SCIB_BAUDRATE_DEFAULT; + settings.config.parity = SCIB_PARITY_DEFAULT; + settings.config.stopbits = SCIB_STOPBITS_DEFAULT; + settings.config.lenght = SCIB_LENGHT_DEFAULT; + settings.gpio_setup = SCIB_GPIO_SETUP_DEFAULT; + // +}//CONSTRUCTOR +// + +void SCIB::setup() +{ + // + get_default_configuration(settings.config); + _configure(settings.config); + // + _gpio_setup = settings.gpio_setup; + (*_gpio_setup)(); + // +}// +// +void SCIB::setup(DSP28335::SCISetup& setup) +{ + settings = setup; + _configure(settings.config); + + _gpio_setup = settings.gpio_setup; + (*_gpio_setup)(); + +}// +// +void SCIB::get_default_configuration(DSP28335::SCIConfiguration& config) +{ + config.baudrate = SCIB_BAUDRATE_DEFAULT; + config.parity = SCIB_PARITY_DEFAULT; + config.stopbits = SCIB_STOPBITS_DEFAULT; + config.lenght = SCIB_LENGHT_DEFAULT; + // +}// +// + +void SCIB::get_configuration(DSP28335::SCIConfiguration& config) +{ + config = settings.config; + // +}// +// +void SCIB::set_configuration(DSP28335::SCIConfiguration& config) +{ + settings.config = config; + _configure(settings.config); + // +}// +// +bool SCIB::compare_configuration(DSP28335::SCIConfiguration& config) +{ + + return (settings.config.baudrate == config.baudrate) + & (settings.config.parity == config.parity) + & (settings.config.stopbits == config.stopbits) + & (settings.config.lenght == config.lenght); + // +}// +// +void SCIB::_configure(DSP28335::SCIConfiguration& config) +{ + // + // SCICTL1.5 - Software reset 0/1-reset/active state + //m_sci_regs.SCICTL1.bit.SWRESET = 0x000; + SciRegs.SCICTL1.bit.SWRESET = 0x000; + // + // Reset FIFO's + SciRegs.SCIFFTX.all=0x8000; + // + // SCICCR.7 - Number of stop bits + switch(config.stopbits) + { + case DSP28335::ONE: { SciRegs.SCICCR.bit.STOPBITS = 0x00; break;} + case DSP28335::TWO: { SciRegs.SCICCR.bit.STOPBITS = 0x01; break;} + default: {break;} + }//switch + // + // SCICCR.5 - Parity enable + // SCICCR.6 - Parity odd/even + switch(config.parity) + { + case DSP28335::NO: {SciRegs.SCICCR.bit.PARITYENA = 0x00; SciRegs.SCICCR.bit.PARITY = 0x00; break;} + case DSP28335::ODD: {SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x00; break;} + case DSP28335::EVEN: {SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x01; break;} + default: {break;} + }//switch + // + // SCICCR.4 - Loop Back test mode enable + SciRegs.SCICCR.bit.LOOPBKENA = 0x00; + // + // SCICCR.3 - Idle - Address mode protocol + SciRegs.SCICCR.bit.ADDRIDLE_MODE = 0x00; + // + // SCICCR.2-0 - Character-length + switch(config.lenght) + { + case DSP28335::LEN1: {SciRegs.SCICCR.bit.SCICHAR = 0x00; break;} + case DSP28335::LEN2: {SciRegs.SCICCR.bit.SCICHAR = 0x01; break;} + case DSP28335::LEN3: {SciRegs.SCICCR.bit.SCICHAR = 0x02; break;} + case DSP28335::LEN4: {SciRegs.SCICCR.bit.SCICHAR = 0x03; break;} + case DSP28335::LEN5: {SciRegs.SCICCR.bit.SCICHAR = 0x04; break;} + case DSP28335::LEN6: {SciRegs.SCICCR.bit.SCICHAR = 0x05; break;} + case DSP28335::LEN7: {SciRegs.SCICCR.bit.SCICHAR = 0x06; break;} + case DSP28335::LEN8: {SciRegs.SCICCR.bit.SCICHAR = 0x07; break;} + default: {break;} + }//switch + // + // SCICTL1.6 - Receive error interrupt enable + SciRegs.SCICTL1.bit.RXERRINTENA =0x000; + // + SciRegs.SCICTL1.bit.RXENA =0x001; // Receiver enable + SciRegs.SCICTL1.bit.TXENA =0x001; // Transmitter enable + SciRegs.SCICTL1.bit.SLEEP =0x000; // Sleep 0/1 - disable/enable + SciRegs.SCICTL1.bit.TXWAKE =0x000; // Transmitter wake-up method select + + SciRegs.SCICTL2.bit.TXINTENA =0x000; // SCITXBUF-register interrupt enable + SciRegs.SCICTL2.bit.RXBKINTENA =0x00; // Receiver-buffer/break interrupt enable + + // Ideal Baud BRR Actual Baud Error, % + // 2400 1952(07A0h) 2400 0 + // 4800 976(03D0h) 4798 -0,04 + // 9600 487(01E7h) 9606 0.06 + // 19200 243(00F3h) 19211 0.06 + // 38400 121(0079h) 38422 0.006 + + switch(config.baudrate) + { + case DSP28335::BR2400: {SciRegs.SCIHBAUD = 0x0007; SciRegs.SCILBAUD = 0x00A0; break;} + case DSP28335::BR4800: {SciRegs.SCIHBAUD = 0x0003; SciRegs.SCILBAUD = 0x00D0; break;} + case DSP28335::BR9600: {SciRegs.SCIHBAUD = 0x0001; SciRegs.SCILBAUD = 0x00E7; break;} + case DSP28335::BR19200: {SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x00F3; break;} + case DSP28335::BR38400: {SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x0079; break;} + default: {break;} + }//switch + + // SCICTL1.5 - Relinquish SCI from Reset + SciRegs.SCICTL1.bit.SWRESET =0x001; + + // +}// +// + +} /* namespace DSP28335 */ diff --git a/DSP28335/SCIB.h b/DSP28335/SCIB.h new file mode 100644 index 0000000..f994bbb --- /dev/null +++ b/DSP28335/SCIB.h @@ -0,0 +1,57 @@ +/* + * SCIB.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "F28335/DSP28x_Project.h" + +#include "DSP28335/SCIBase.h" + +#ifndef DSP28335_SCIB_H_ +#define DSP28335_SCIB_H_ + +#ifndef SCIB_BAUDRATE_DEFAULT +#define SCIB_BAUDRATE_DEFAULT (DSP28335::BR9600) +#endif + +#ifndef SCIB_PARITY_DEFAULT +#define SCIB_PARITY_DEFAULT (DSP28335::NO) +//#define SCIB_PARITY_DEFAULT (DSP28335::ODD) +//#define SCIB_PARITY_DEFAULT (DSP28335::EVEN) +#endif + +#ifndef SCIB_STOPBITS_DEFAULT +#define SCIB_STOPBITS_DEFAULT (DSP28335::ONE) +#endif + +#ifndef SCIB_LENGHT_DEFAULT +#define SCIB_LENGHT_DEFAULT (DSP28335::LEN8) +#endif + +#ifndef SCIB_GPIO_SETUP_DEFAULT +#define SCIB_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_scib_setup) +#endif + + +namespace DSP28335 +{ + +class SCIB: public SCIBase +{ +public: + SCIB(volatile struct SCI_REGS& SciRegs); + void setup(); + void setup(DSP28335::SCISetup& setup); + void get_default_configuration(DSP28335::SCIConfiguration& config); + void get_configuration(DSP28335::SCIConfiguration& config); + void set_configuration(DSP28335::SCIConfiguration& config); + bool compare_configuration(DSP28335::SCIConfiguration& config); +protected: + void _configure(DSP28335::SCIConfiguration& config); +};//SCIB + +} /* namespace DSP28335 */ + +#endif /* DSP28335_SCIB_H_ */ diff --git a/DSP28335/SCIBase.cpp b/DSP28335/SCIBase.cpp new file mode 100644 index 0000000..f49b9d0 --- /dev/null +++ b/DSP28335/SCIBase.cpp @@ -0,0 +1,21 @@ +/* + * SCIBase.cpp + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "DSP28335/SCIBase.h" + +namespace DSP28335 +{ + +SCIBase::SCIBase(volatile struct SCI_REGS& SciRegs): + SciRegs(SciRegs), + settings(), + _gpio_setup(0) +// +{}//CONSTRUCTOR + +// +} /* namespace DSP28335 */ diff --git a/DSP28335/SCIBase.h b/DSP28335/SCIBase.h new file mode 100644 index 0000000..936486d --- /dev/null +++ b/DSP28335/SCIBase.h @@ -0,0 +1,78 @@ +/* + * SCIBase.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "F28335/DSP28x_Project.h" + +#include "DSP28335/GPIO.h" +#include "RUDRIVEFRAMEWORK/DataType.h" +#include "RUDRIVEFRAMEWORK/SystemDefinitions.h" + + +#ifndef DSP28335_SCIBASE_H_ +#define DSP28335_SCIBASE_H_ + + +namespace DSP28335 +{ + + +enum SCIBaudRate { BR2400, BR4800, BR9600, BR19200, BR38400}; +enum SCIParity {NO, ODD, EVEN}; +enum SCIStopBits {ONE, TWO}; +enum SCICharLenght { LEN1, LEN2, LEN3, LEN4, LEN5, LEN6, LEN7, LEN8}; + + + +struct SCIConfiguration +{ + DSP28335::SCIBaudRate baudrate; + DSP28335::SCIParity parity; + DSP28335::SCIStopBits stopbits; + DSP28335::SCICharLenght lenght; + SCIConfiguration(): + baudrate(DSP28335::BR19200), + parity(DSP28335::ODD), + stopbits(DSP28335::ONE), + lenght(DSP28335::LEN1) + {} +};// + + +struct SCISetup +{ + SCIConfiguration config; + pGPIO_FUNCTION gpio_setup; + // SCISetup(): + // config(), + // gpio_setup(0) + // {} +};// + + + +class SCIBase +{ +public: + volatile struct SCI_REGS& SciRegs; +protected: + SCISetup settings; +public: + SCIBase(volatile struct SCI_REGS& SciRegs); + virtual void setup() = 0; + //virtual void setup(DSP28335::SCISetup& setup) = 0; + virtual void get_default_configuration(DSP28335::SCIConfiguration& config) = 0; + virtual void get_configuration(DSP28335::SCIConfiguration& config) = 0; + virtual void set_configuration(DSP28335::SCIConfiguration& config) = 0; + virtual bool compare_configuration(DSP28335::SCIConfiguration& config) = 0; +protected: + virtual void _configure(DSP28335::SCIConfiguration& config) = 0; + void (*_gpio_setup)(); +}; + +} /* namespace DSP28335 */ + +#endif /* DSP28335_SCIBASE_H_ */ diff --git a/DSP28335/SCIC.cpp b/DSP28335/SCIC.cpp new file mode 100644 index 0000000..75afa81 --- /dev/null +++ b/DSP28335/SCIC.cpp @@ -0,0 +1,143 @@ +/* + * SCIC.cpp + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "DSP28335/SCIC.h" + +namespace DSP28335 +{ +//CONSTRUCTOR +SCIC::SCIC(volatile struct SCI_REGS& SciRegs): + DSP28335::SCIBase(SciRegs) +{ + // set default + settings.config.baudrate = SCIC_BAUDRATE_DEFAULT; + settings.config.parity = SCIC_PARITY_DEFAULT; + settings.config.stopbits = SCIC_STOPBITS_DEFAULT; + settings.config.lenght = SCIC_LENGHT_DEFAULT; + settings.gpio_setup = SCIC_GPIO_SETUP_DEFAULT; + // +}//CONSTRUCTOR + + +void SCIC::setup() +{ + // + get_default_configuration(settings.config); + _configure(settings.config); + // + _gpio_setup = settings.gpio_setup; + (*_gpio_setup)(); + // +}// +// +void SCIC::setup(DSP28335::SCISetup& setup) +{ + settings = setup; + _configure(settings.config); + // + _gpio_setup = settings.gpio_setup; + (*_gpio_setup)(); + // +}// +// +void SCIC::get_default_configuration(DSP28335::SCIConfiguration& config) +{ + config.baudrate = SCIC_BAUDRATE_DEFAULT; + config.parity = SCIC_PARITY_DEFAULT; + config.stopbits = SCIC_STOPBITS_DEFAULT; + config.lenght = SCIC_LENGHT_DEFAULT; + // +}// +// +void SCIC::get_configuration(DSP28335::SCIConfiguration& config) +{ + config = settings.config; + // +}// +// +void SCIC::set_configuration(DSP28335::SCIConfiguration& config) +{ + settings.config = config; + _configure(settings.config); + // +}// +// +bool SCIC::compare_configuration(DSP28335::SCIConfiguration& config) +{ + + return (settings.config.baudrate == config.baudrate) + & (settings.config.parity == config.parity) + & (settings.config.stopbits == config.stopbits) + & (settings.config.lenght == config.lenght); + // +}// +// +void SCIC::_configure(DSP28335::SCIConfiguration& config) +{ + // + // SCICTL1.5 - Software reset 0/1-reset/active state + SciRegs.SCICTL1.bit.SWRESET = 0x000; + // + // Reset FIFO's + SciRegs.SCIFFTX.all=0x8000; + // + // SCICCR.7 - Number of stop bits + if(config.stopbits == DSP28335::ONE){ SciRegs.SCICCR.bit.STOPBITS = 0x00;} + if(config.stopbits == DSP28335::TWO){ SciRegs.SCICCR.bit.STOPBITS = 0x01;} + // + // SCICCR.5 - Parity enable + // SCICCR.6 - Parity odd/even + if(config.parity == DSP28335::NO){ SciRegs.SCICCR.bit.PARITYENA = 0x00; SciRegs.SCICCR.bit.PARITY = 0x00;} + if(config.parity == DSP28335::ODD){ SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x00;} + if(config.parity == DSP28335::EVEN){ SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x01;} + // + // SCICCR.4 - Loop Back test mode enable + SciRegs.SCICCR.bit.LOOPBKENA = 0x00; + // + // SCICCR.3 - Idle - Address mode protocol + SciRegs.SCICCR.bit.ADDRIDLE_MODE = 0x00; + // + // SCICCR.2-0 - Character-length + if(config.lenght == DSP28335::LEN1){ SciRegs.SCICCR.bit.SCICHAR = 0x00;} + if(config.lenght == DSP28335::LEN2){ SciRegs.SCICCR.bit.SCICHAR = 0x01;} + if(config.lenght == DSP28335::LEN3){ SciRegs.SCICCR.bit.SCICHAR = 0x02;} + if(config.lenght == DSP28335::LEN4){ SciRegs.SCICCR.bit.SCICHAR = 0x03;} + if(config.lenght == DSP28335::LEN5){ SciRegs.SCICCR.bit.SCICHAR = 0x04;} + if(config.lenght == DSP28335::LEN6){ SciRegs.SCICCR.bit.SCICHAR = 0x05;} + if(config.lenght == DSP28335::LEN7){ SciRegs.SCICCR.bit.SCICHAR = 0x06;} + if(config.lenght == DSP28335::LEN8){ SciRegs.SCICCR.bit.SCICHAR = 0x07;} + // + // SCICTL1.6 - Receive error interrupt enable + SciRegs.SCICTL1.bit.RXERRINTENA =0x000; + // + SciRegs.SCICTL1.bit.RXENA =0x001; // Receiver enable + SciRegs.SCICTL1.bit.TXENA =0x001; // Transmitter enable + SciRegs.SCICTL1.bit.SLEEP =0x000; // Sleep 0/1 - disable/enable + SciRegs.SCICTL1.bit.TXWAKE =0x000; // Transmitter wake-up method select + + SciRegs.SCICTL2.bit.TXINTENA =0x000; // SCITXBUF-register interrupt enable + SciRegs.SCICTL2.bit.RXBKINTENA =0x00; // Receiver-buffer/break interrupt enable + + // Ideal Baud BRR Actual Baud Error, % + // 2400 1952(07A0h) 2400 0 + // 4800 976(03D0h) 4798 -0,04 + // 9600 487(01E7h) 9606 0.06 + // 19200 243(00F3h) 19211 0.06 + // 38400 121(0079h) 38422 0.006 + + if(config.baudrate == DSP28335::BR2400){ SciRegs.SCIHBAUD = 0x0007; SciRegs.SCILBAUD = 0x00A0;} + if(config.baudrate == DSP28335::BR4800){ SciRegs.SCIHBAUD = 0x0003; SciRegs.SCILBAUD = 0x00D0;} + if(config.baudrate == DSP28335::BR9600){ SciRegs.SCIHBAUD = 0x0001; SciRegs.SCILBAUD = 0x00E7;} + if(config.baudrate == DSP28335::BR19200){ SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x00F3;} + if(config.baudrate == DSP28335::BR38400){ SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x0079;} + + // SCICTL1.5 - Relinquish SCI from Reset + SciRegs.SCICTL1.bit.SWRESET =0x001; + // +}// +// +} /* namespace DSP28335 */ diff --git a/DSP28335/SCIC.h b/DSP28335/SCIC.h new file mode 100644 index 0000000..81f6290 --- /dev/null +++ b/DSP28335/SCIC.h @@ -0,0 +1,57 @@ +/* + * SCIC.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include "F28335/DSP28x_Project.h" + +#include "DSP28335/SCIBase.h" + +#ifndef DSP28335_SCIC_H_ +#define DSP28335_SCIC_H_ + +#ifndef SCIC_BAUDRATE_DEFAULT +#define SCIC_BAUDRATE_DEFAULT (DSP28335::BR9600) +#endif + +#ifndef SCIC_PARITY_DEFAULT +#define SCIC_PARITY_DEFAULT (DSP28335::NO) +//#define SCIC_PARITY_DEFAULT (DSP28335::ODD) +//#define SCIC_PARITY_DEFAULT (DSP28335::EVEN) +#endif + +#ifndef SCIC_STOPBITS_DEFAULT +#define SCIC_STOPBITS_DEFAULT (DSP28335::ONE) +#endif + +#ifndef SCIC_LENGHT_DEFAULT +#define SCIC_LENGHT_DEFAULT (DSP28335::LEN8) +#endif + +#ifndef SCIC_GPIO_SETUP_DEFAULT +#define SCIC_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_scic_setup) +#endif + + +namespace DSP28335 +{ + +class SCIC: public SCIBase +{ +public: + SCIC(volatile struct SCI_REGS& SciRegs); + void setup(); + void setup(DSP28335::SCISetup& setup); + void get_default_configuration(DSP28335::SCIConfiguration& config); + void get_configuration(DSP28335::SCIConfiguration& config); + void set_configuration(DSP28335::SCIConfiguration& config); + bool compare_configuration(DSP28335::SCIConfiguration& config); +protected: + void _configure(DSP28335::SCIConfiguration& config); +}; + +} /* namespace DSP28335 */ + +#endif /* DSP28335_SCIC_H_ */ diff --git a/F28335/DSP2833x_Adc.c b/F28335/DSP2833x_Adc.c new file mode 100644 index 0000000..f7eb525 --- /dev/null +++ b/F28335/DSP2833x_Adc.c @@ -0,0 +1,70 @@ +//########################################################################### +// +// FILE: DSP2833x_Adc.c +// +// TITLE: DSP2833x ADC Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +// +// Included Files +// +#include "F28335/DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "F28335/DSP2833x_Examples.h" // DSP2833x Examples Include File + +// +// Defines +// +#define ADC_usDELAY 5000L + +// +// InitAdc - This function initializes ADC to a known state. +// +void +InitAdc(void) +{ + //extern void DSP28x_usDelay(Uint32 Count); + extern void DelayUs(Uint16); + + // + // *IMPORTANT* + // The ADC_cal function, which copies the ADC calibration values from + // TI reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC to + // function according to specification. The clocks to the ADC MUST be + // enabled before calling this function. See the device data manual and/or + // the ADC Reference Manual for more information. + // + EALLOW; + SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; + ADC_cal(); + EDIS; + + // + // To powerup the ADC the ADCENCLK bit should be set first to enable + // clocks, followed by powering up the bandgap, reference circuitry, and + // ADC core. Before the first conversion is performed a 5ms delay must be + // observed after power up to give all analog circuits time to power up + // and settle + // + + // + // Please note that for the delay function below to operate correctly the + // CPU_RATE define statement in the DSP2833x_Examples.h file must + // contain the correct CPU clock period in nanoseconds. + // + AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits + DELAY_US(5000); // Delay before converting ADC channels + // +} + +// +// End of file +// + diff --git a/F28335/DSP2833x_Adc.h b/F28335/DSP2833x_Adc.h new file mode 100644 index 0000000..3c2d5f1 --- /dev/null +++ b/F28335/DSP2833x_Adc.h @@ -0,0 +1,254 @@ +//########################################################################### +// +// FILE: DSP2833x_Adc.h +// +// TITLE: DSP2833x Device ADC Register Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_ADC_H +#define DSP2833x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// ADC Individual Register Bit Definitions: +// +struct ADCTRL1_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode + Uint16 SEQ_OVRD:1; // 5 Sequencer override + Uint16 CONT_RUN:1; // 6 Continuous run + Uint16 CPS:1; // 7 ADC core clock pre-scalar + Uint16 ACQ_PS:4; // 11:8 Acquisition window size + Uint16 SUSMOD:2; // 13:12 Emulation suspend mode + Uint16 RESET:1; // 14 ADC reset + Uint16 rsvd2:1; // 15 reserved +}; + +union ADCTRL1_REG { + Uint16 all; + struct ADCTRL1_BITS bit; +}; + +struct ADCTRL2_BITS { // bits description + Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 + Uint16 rsvd1:1; // 1 reserved + Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode + Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable + Uint16 rsvd2:1; // 4 reserved + Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 + Uint16 RST_SEQ2:1; // 6 Reset SEQ2 + Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 + Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 + Uint16 rsvd3:1; // 9 reserved + Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode + Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable + Uint16 rsvd4:1; // 12 reserved + Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 + Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 + Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable +}; + +union ADCTRL2_REG { + Uint16 all; + struct ADCTRL2_BITS bit; +}; + +struct ADCASEQSR_BITS { // bits description + Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state + Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state + Uint16 rsvd1:1; // 7 reserved + Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status + Uint16 rsvd2:4; // 15:12 reserved +}; + +union ADCASEQSR_REG { + Uint16 all; + struct ADCASEQSR_BITS bit; +}; + +struct ADCMAXCONV_BITS { // bits description + Uint16 MAX_CONV1:4; // 3:0 Max number of conversions + Uint16 MAX_CONV2:3; // 6:4 Max number of conversions + Uint16 rsvd1:9; // 15:7 reserved +}; + +union ADCMAXCONV_REG { + Uint16 all; + struct ADCMAXCONV_BITS bit; +}; + +struct ADCCHSELSEQ1_BITS { // bits description + Uint16 CONV00:4; // 3:0 Conversion selection 00 + Uint16 CONV01:4; // 7:4 Conversion selection 01 + Uint16 CONV02:4; // 11:8 Conversion selection 02 + Uint16 CONV03:4; // 15:12 Conversion selection 03 +}; + +union ADCCHSELSEQ1_REG{ + Uint16 all; + struct ADCCHSELSEQ1_BITS bit; +}; + +struct ADCCHSELSEQ2_BITS { // bits description + Uint16 CONV04:4; // 3:0 Conversion selection 04 + Uint16 CONV05:4; // 7:4 Conversion selection 05 + Uint16 CONV06:4; // 11:8 Conversion selection 06 + Uint16 CONV07:4; // 15:12 Conversion selection 07 +}; + +union ADCCHSELSEQ2_REG{ + Uint16 all; + struct ADCCHSELSEQ2_BITS bit; +}; + +struct ADCCHSELSEQ3_BITS { // bits description + Uint16 CONV08:4; // 3:0 Conversion selection 08 + Uint16 CONV09:4; // 7:4 Conversion selection 09 + Uint16 CONV10:4; // 11:8 Conversion selection 10 + Uint16 CONV11:4; // 15:12 Conversion selection 11 +}; + +union ADCCHSELSEQ3_REG{ + Uint16 all; + struct ADCCHSELSEQ3_BITS bit; +}; + +struct ADCCHSELSEQ4_BITS { // bits description + Uint16 CONV12:4; // 3:0 Conversion selection 12 + Uint16 CONV13:4; // 7:4 Conversion selection 13 + Uint16 CONV14:4; // 11:8 Conversion selection 14 + Uint16 CONV15:4; // 15:12 Conversion selection 15 +}; + +union ADCCHSELSEQ4_REG { + Uint16 all; + struct ADCCHSELSEQ4_BITS bit; +}; + +struct ADCTRL3_BITS { // bits description + Uint16 SMODE_SEL:1; // 0 Sampling mode select + Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider + Uint16 ADCPWDN:1; // 5 ADC powerdown + Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCTRL3_REG { + Uint16 all; + struct ADCTRL3_BITS bit; +}; + +struct ADCST_BITS { // bits description + Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag + Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag + Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status + Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status + Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear + Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear + Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 + Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 + Uint16 rsvd1:8; // 15:8 reserved +}; + +union ADCST_REG { + Uint16 all; + struct ADCST_BITS bit; +}; + +struct ADCREFSEL_BITS { // bits description + Uint16 rsvd1:14; // 13:0 reserved + Uint16 REF_SEL:2; // 15:14 Reference select +}; +union ADCREFSEL_REG { + Uint16 all; + struct ADCREFSEL_BITS bit; +}; + +struct ADCOFFTRIM_BITS{ // bits description + int16 OFFSET_TRIM:9; // 8:0 Offset Trim + Uint16 rsvd1:7; // 15:9 reserved +}; + +union ADCOFFTRIM_REG{ + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADC_REGS { + union ADCTRL1_REG ADCTRL1; //ADC Control 1 + union ADCTRL2_REG ADCTRL2; //ADC Control 2 + union ADCMAXCONV_REG ADCMAXCONV; //Max conversions + union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1 + union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2 + union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3 + union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4 + union ADCASEQSR_REG ADCASEQSR; //Autosequence status register + Uint16 ADCRESULT0; //Conversion Result Buffer 0 + Uint16 ADCRESULT1; //Conversion Result Buffer 1 + Uint16 ADCRESULT2; //Conversion Result Buffer 2 + Uint16 ADCRESULT3; //Conversion Result Buffer 3 + Uint16 ADCRESULT4; //Conversion Result Buffer 4 + Uint16 ADCRESULT5; //Conversion Result Buffer 5 + Uint16 ADCRESULT6; //Conversion Result Buffer 6 + Uint16 ADCRESULT7; //Conversion Result Buffer 7 + Uint16 ADCRESULT8; //Conversion Result Buffer 8 + Uint16 ADCRESULT9; //Conversion Result Buffer 9 + Uint16 ADCRESULT10; //Conversion Result Buffer 10 + Uint16 ADCRESULT11; //Conversion Result Buffer 11 + Uint16 ADCRESULT12; //Conversion Result Buffer 12 + Uint16 ADCRESULT13; //Conversion Result Buffer 13 + Uint16 ADCRESULT14; //Conversion Result Buffer 14 + Uint16 ADCRESULT15; //Conversion Result Buffer 15 + union ADCTRL3_REG ADCTRL3; //ADC Control 3 + union ADCST_REG ADCST; //ADC Status Register + Uint16 rsvd1; + Uint16 rsvd2; + union ADCREFSEL_REG ADCREFSEL; //Reference Select Register + union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register +}; + +struct ADC_RESULT_MIRROR_REGS +{ + Uint16 ADCRESULT0; // Conversion Result Buffer 0 + Uint16 ADCRESULT1; // Conversion Result Buffer 1 + Uint16 ADCRESULT2; // Conversion Result Buffer 2 + Uint16 ADCRESULT3; // Conversion Result Buffer 3 + Uint16 ADCRESULT4; // Conversion Result Buffer 4 + Uint16 ADCRESULT5; // Conversion Result Buffer 5 + Uint16 ADCRESULT6; // Conversion Result Buffer 6 + Uint16 ADCRESULT7; // Conversion Result Buffer 7 + Uint16 ADCRESULT8; // Conversion Result Buffer 8 + Uint16 ADCRESULT9; // Conversion Result Buffer 9 + Uint16 ADCRESULT10; // Conversion Result Buffer 10 + Uint16 ADCRESULT11; // Conversion Result Buffer 11 + Uint16 ADCRESULT12; // Conversion Result Buffer 12 + Uint16 ADCRESULT13; // Conversion Result Buffer 13 + Uint16 ADCRESULT14; // Conversion Result Buffer 14 + Uint16 ADCRESULT15; // Conversion Result Buffer 15 +}; + +// +// ADC External References & Function Declarations: +// +extern volatile struct ADC_REGS AdcRegs; +extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ADC_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_CpuTimers.h b/F28335/DSP2833x_CpuTimers.h new file mode 100644 index 0000000..9cc32ab --- /dev/null +++ b/F28335/DSP2833x_CpuTimers.h @@ -0,0 +1,224 @@ +//########################################################################### +// +// FILE: DSP2833x_CpuTimers.h +// +// TITLE: DSP2833x CPU 32-bit Timers Register Definitions. +// +// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and +// other realtime operating systems. +// +// Do not use these two timers in your application if you ever plan +// on integrating DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two +// timers if using DSP-BIOS or another realtime OS. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_CPU_TIMERS_H +#define DSP2833x_CPU_TIMERS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// CPU Timer Register Bit Definitions +// + +// +// TCR: Control register bit definitions +// +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 TSS:1; // 4 Timer Start/Stop + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 + Uint16 rsvd3:2; // 12:13 reserved + Uint16 TIE:1; // 14 Output enable + Uint16 TIF:1; // 15 Interrupt flag +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +// +// TPR: Pre-scale low bit definitions +// +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 Divide-down low + Uint16 PSC:8; // 15:8 Prescale counter low +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +// +// TPRH: Pre-scale high bit definitions +// +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 Divide-down high + Uint16 PSCH:8; // 15:8 Prescale counter high +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +// +// TIM, TIMH: Timer register definitions +// +struct TIM_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union TIM_GROUP { + Uint32 all; + struct TIM_REG half; +}; + +// +// PRD, PRDH: Period register definitions +// +struct PRD_REG { + Uint16 LSW; + Uint16 MSW; +}; + +union PRD_GROUP { + Uint32 all; + struct PRD_REG half; +}; + +// +// CPU Timer Register File +// +struct CPUTIMER_REGS { + union TIM_GROUP TIM; // Timer counter register + union PRD_GROUP PRD; // Period register + union TCR_REG TCR; // Timer control register + Uint16 rsvd1; // reserved + union TPR_REG TPR; // Timer pre-scale low + union TPRH_REG TPRH; // Timer pre-scale high +}; + +// +// CPU Timer Support Variables +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +// +// Function prototypes and external definitions +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern struct CPUTIMER_VARS CpuTimer0; + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. +// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS +// +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; + +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines for useful Timer Operations: +// + +// +// Start Timer +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS +// Do not use these two timers if you ever plan on integrating +// DSP-BIOS or another realtime OS. +// +// For this reason, comment out the code to manipulate these two timers +// if using DSP-BIOS or another realtime OS. +// + +// +// Start Timer +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_CPU_TIMERS_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_DMA.h b/F28335/DSP2833x_DMA.h new file mode 100644 index 0000000..49cb243 --- /dev/null +++ b/F28335/DSP2833x_DMA.h @@ -0,0 +1,366 @@ +//########################################################################### +// +// FILE: DSP2833x_DMA.h +// +// TITLE: DSP2833x DMA Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_DMA_H +#define DSP2833x_DMA_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Channel MODE register bit definitions +// +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W): + // 0 no interrupt + // 1 SEQ1INT & ADCSYNC + // 2 SEQ2INT + // 3 XINT1 + // 4 XINT2 + // 5 XINT3 + // 6 XINT4 + // 7 XINT5 + // 8 XINT6 + // 9 XINT7 + // 10 XINT13 + // 11 TINT0 + // 12 TINT1 + // 13 TINT2 + // 14 MXEVTA & MXSYNCA + // 15 MREVTA & MRSYNCA + // 16 MXEVTB & MXSYNCB + // 17 MREVTB & MRSYNCB + // 18 ePWM1SOCA + // 19 ePWM1SOCB + // 20 ePWM2SOCA + // 21 ePWM2SOCB + // 22 ePWM3SOCA + // 23 ePWM3SOCB + // 24 ePWM4SOCA + // 25 ePWM4SOCB + // 26 ePWM5SOCA + // 27 ePWM5SOCB + // 28 ePWM6SOCA + // 29 ePWM6SOCB + // 30:31 no interrupt + Uint16 rsvd1:2; // 6:5 (R=0:0) + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W): + // 0 overflow interrupt disabled + // 1 overflow interrupt enabled + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W): + // 0 peripheral interrupt disabled + // 1 peripheral interrupt enabled + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W): + // 0 generate interrupt at beginning of new + // transfer + // 1 generate interrupt at end of transfer + Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W): + // 0 only interrupt event triggers single + // burst transfer + // 1 first interrupt triggers burst, + // continue until transfer count is zero + Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W): + // 0 stop when transfer count is zero + // 1 re-initialize when transfer count is + // zero + Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W): + // 0 ignore selected interrupt sync signal + // 1 enable selected interrupt sync signal + Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W): + // 0 sync signal controls source wrap + // counter + // 1 sync signal controls destination wrap + // counter + Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W): + // 0 16-bit data transfer size + // 1 32-bit data transfer size + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W): + // 0 channel interrupt disabled + // 1 channel interrupt enabled +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +// +// Channel CONTROL register bit definitions +// +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit (R=0/W=1) + Uint16 HALT:1; // 1 Halt Bit (R=0/W=1) + Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1) + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1) + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1) + Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1) + Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1) + Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1) + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R): + // 0 no interrupt pending + // 1 interrupt pending + Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R): + // 0 no sync pending + // 1 sync pending + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R): + // 0 no sync error + // 1 sync error detected + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R): + // 0 no transfer in progress or pending + // 1 transfer in progress or pending + Uint16 BURSTSTS:1; // 12 Burst Status Bit (R): + // 0 no burst in progress or pending + // 1 burst in progress or pending + Uint16 RUNSTS:1; // 13 Run Status Bit (R): + // 0 channel not running or halted + // 1 channel running + Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R) + // 0 no overflow event + // 1 overflow event + Uint16 rsvd1:1; // 15 (R=0) +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +// +// DMACTRL register bit definitions +// +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1) + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1) + Uint16 rsvd1:14; // 15:2 (R=0:0) +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +// +// DEBUGCTRL register bit definitions +// +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 (R=0:0) + Uint16 FREE:1; // 15 Debug Mode Bit (R/W): + // 0 halt after current read-write operation + // 1 continue running +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +// +// PRIORITYCTRL1 register bit definitions +// +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W): + // 0 same priority as all other channels + // 1 highest priority channel + Uint16 rsvd1:15; // 15:1 (R=0:0) +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +// +// PRIORITYSTAT register bit definitions: +// +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R): + // 0,0,0 no channel active + // 0,0,1 Ch1 channel active + // 0,1,0 Ch2 channel active + // 0,1,1 Ch3 channel active + // 1,0,0 Ch4 channel active + // 1,0,1 Ch5 channel active + // 1,1,0 Ch6 channel active + Uint16 rsvd1:1; // 3 (R=0) + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R): + // 0,0,0 no channel active & interrupted by Ch1 + // 0,0,1 cannot occur + // 0,1,0 Ch2 was active and interrupted by Ch1 + // 0,1,1 Ch3 was active and interrupted by Ch1 + // 1,0,0 Ch4 was active and interrupted by Ch1 + // 1,0,1 Ch5 was active and interrupted by Ch1 + // 1,1,0 Ch6 was active and interrupted by Ch1 + Uint16 rsvd2:9; // 15:7 (R=0:0) +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +// +// Burst Size +// +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +// +// Burst Count +// +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size + Uint16 rsvd1:11; // 15:5 reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +// +// DMA Channel Registers: +// +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + + // + // Source Burst Step Register + // + int16 SRC_BURST_STEP; + + // + // Destination Burst Step Register + // + int16 DST_BURST_STEP; + + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + + // + // Source Transfer Step Register + // + int16 SRC_TRANSFER_STEP; + + // + // Destination Transfer Step Register + // + int16 DST_TRANSFER_STEP; + + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + + // + // Destination Wrap Size Register + // + Uint16 DST_WRAP_SIZE; + + // + // Destination Wrap Count Register + // + Uint16 DST_WRAP_COUNT; + + // + // Destination Wrap Step Register + // + int16 DST_WRAP_STEP; + + // + // Source Begin Address Shadow Register + // + Uint32 SRC_BEG_ADDR_SHADOW; + + // + // Source Address Shadow Register + // + Uint32 SRC_ADDR_SHADOW; + + // + // Source Begin Address Active Register + // + Uint32 SRC_BEG_ADDR_ACTIVE; + + // + // Source Address Active Register + // + Uint32 SRC_ADDR_ACTIVE; + + // + // Destination Begin Address Shadow Register + // + Uint32 DST_BEG_ADDR_SHADOW; + + // + // Destination Address Shadow Register + // + Uint32 DST_ADDR_SHADOW; + + // + // Destination Begin Address Active Register + // + Uint32 DST_BEG_ADDR_ACTIVE; + + // + // Destination Address Active Register + // + Uint32 DST_ADDR_ACTIVE; +}; + +// +// DMA Registers +// +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // reserved + Uint16 rsvd1; // + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +// +// External References & Function Declarations +// +extern volatile struct DMA_REGS DmaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DMA_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_DefaultIsr.h b/F28335/DSP2833x_DefaultIsr.h new file mode 100644 index 0000000..0d969f0 --- /dev/null +++ b/F28335/DSP2833x_DefaultIsr.h @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: DSP2833x_DefaultIsr.h +// +// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_DEFAULT_ISR_H +#define DSP2833x_DEFAULT_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the DSP2833x_PieVect.h +// file. +// + +// +// Non-Peripheral Interrupts +// +interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 +interrupt void INT14_ISR(void); // CPU-Timer2 +interrupt void DATALOG_ISR(void); // Datalogging interrupt +interrupt void RTOSINT_ISR(void); // RTOS interrupt +interrupt void EMUINT_ISR(void); // Emulation interrupt +interrupt void NMI_ISR(void); // Non-maskable interrupt +interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP +interrupt void USER1_ISR(void); // User Defined trap 1 +interrupt void USER2_ISR(void); // User Defined trap 2 +interrupt void USER3_ISR(void); // User Defined trap 3 +interrupt void USER4_ISR(void); // User Defined trap 4 +interrupt void USER5_ISR(void); // User Defined trap 5 +interrupt void USER6_ISR(void); // User Defined trap 6 +interrupt void USER7_ISR(void); // User Defined trap 7 +interrupt void USER8_ISR(void); // User Defined trap 8 +interrupt void USER9_ISR(void); // User Defined trap 9 +interrupt void USER10_ISR(void); // User Defined trap 10 +interrupt void USER11_ISR(void); // User Defined trap 11 +interrupt void USER12_ISR(void); // User Defined trap 12 + +// +// Group 1 PIE Interrupt Service Routines +// +interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR +interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR +interrupt void XINT1_ISR(void); // External interrupt 1 +interrupt void XINT2_ISR(void); // External interrupt 2 +interrupt void ADCINT_ISR(void); // ADC +interrupt void TINT0_ISR(void); // Timer 0 +interrupt void WAKEINT_ISR(void); // WD + +// +// Group 2 PIE Interrupt Service Routines +// +interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 +interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 +interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 +interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 +interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 +interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 + +// +// Group 3 PIE Interrupt Service Routines +// +interrupt void EPWM1_INT_ISR(void); // EPWM-1 +interrupt void EPWM2_INT_ISR(void); // EPWM-2 +interrupt void EPWM3_INT_ISR(void); // EPWM-3 +interrupt void EPWM4_INT_ISR(void); // EPWM-4 +interrupt void EPWM5_INT_ISR(void); // EPWM-5 +interrupt void EPWM6_INT_ISR(void); // EPWM-6 + +// +// Group 4 PIE Interrupt Service Routines +// +interrupt void ECAP1_INT_ISR(void); // ECAP-1 +interrupt void ECAP2_INT_ISR(void); // ECAP-2 +interrupt void ECAP3_INT_ISR(void); // ECAP-3 +interrupt void ECAP4_INT_ISR(void); // ECAP-4 +interrupt void ECAP5_INT_ISR(void); // ECAP-5 +interrupt void ECAP6_INT_ISR(void); // ECAP-6 + +// +// Group 5 PIE Interrupt Service Routines +// +interrupt void EQEP1_INT_ISR(void); // EQEP-1 +interrupt void EQEP2_INT_ISR(void); // EQEP-2 + +// +// Group 6 PIE Interrupt Service Routines +// +interrupt void SPIRXINTA_ISR(void); // SPI-A +interrupt void SPITXINTA_ISR(void); // SPI-A +interrupt void MRINTA_ISR(void); // McBSP-A +interrupt void MXINTA_ISR(void); // McBSP-A +interrupt void MRINTB_ISR(void); // McBSP-B +interrupt void MXINTB_ISR(void); // McBSP-B + +// +// Group 7 PIE Interrupt Service Routines +// +interrupt void DINTCH1_ISR(void); // DMA-Channel 1 +interrupt void DINTCH2_ISR(void); // DMA-Channel 2 +interrupt void DINTCH3_ISR(void); // DMA-Channel 3 +interrupt void DINTCH4_ISR(void); // DMA-Channel 4 +interrupt void DINTCH5_ISR(void); // DMA-Channel 5 +interrupt void DINTCH6_ISR(void); // DMA-Channel 6 + +// +// Group 8 PIE Interrupt Service Routines +// +interrupt void I2CINT1A_ISR(void); // I2C-A +interrupt void I2CINT2A_ISR(void); // I2C-A +interrupt void SCIRXINTC_ISR(void); // SCI-C +interrupt void SCITXINTC_ISR(void); // SCI-C + +// +// Group 9 PIE Interrupt Service Routines +// +interrupt void SCIRXINTA_ISR(void); // SCI-A +interrupt void SCITXINTA_ISR(void); // SCI-A +interrupt void SCIRXINTB_ISR(void); // SCI-B +interrupt void SCITXINTB_ISR(void); // SCI-B +interrupt void ECAN0INTA_ISR(void); // eCAN-A +interrupt void ECAN1INTA_ISR(void); // eCAN-A +interrupt void ECAN0INTB_ISR(void); // eCAN-B +interrupt void ECAN1INTB_ISR(void); // eCAN-B + +// +// Group 10 PIE Interrupt Service Routines +// + +// +// Group 11 PIE Interrupt Service Routines +// + +// +// Group 12 PIE Interrupt Service Routines +// +interrupt void XINT3_ISR(void); // External interrupt 3 +interrupt void XINT4_ISR(void); // External interrupt 4 +interrupt void XINT5_ISR(void); // External interrupt 5 +interrupt void XINT6_ISR(void); // External interrupt 6 +interrupt void XINT7_ISR(void); // External interrupt 7 +interrupt void LVF_ISR(void); // Latched overflow flag +interrupt void LUF_ISR(void); // Latched underflow flag + +// +// Catch-all for Reserved Locations For testing purposes +// +interrupt void PIE_RESERVED(void); // Reserved for test +interrupt void rsvd_ISR(void); // for test +interrupt void INT_NOTUSED_ISR(void); // for unused interrupts + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEFAULT_ISR_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_DevEmu.h b/F28335/DSP2833x_DevEmu.h new file mode 100644 index 0000000..7ff52c0 --- /dev/null +++ b/F28335/DSP2833x_DevEmu.h @@ -0,0 +1,100 @@ +//########################################################################### +// +// FILE: DSP2833x_DevEmu.h +// +// TITLE: DSP2833x Device Emulation Register Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_DEV_EMU_H +#define DSP2833x_DEV_EMU_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Device Emulation Register Bit Definitions: +// + +// +// Device Configuration Register Bit Definitions +// +struct DEVICECNF_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 VMAPS:1; // 3 VMAP Status + Uint16 rsvd2:1; // 4 reserved + Uint16 XRSn:1; // 5 XRSn Signal Status + Uint16 rsvd3:10; // 15:6 + Uint16 rsvd4:3; // 18:16 + Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection + Uint16 rsvd5:7; // 26:20 reserved + Uint16 TRSTN:1; // 27 Status of TRSTn signal + Uint16 rsvd6:4; // 31:28 reserved +}; + +union DEVICECNF_REG { + Uint32 all; + struct DEVICECNF_BITS bit; +}; + +// +// CLASSID +// +struct CLASSID_BITS { // bits description + Uint16 CLASSNO:8; // 7:0 Class Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union CLASSID_REG { + Uint16 all; + struct CLASSID_BITS bit; +}; + +struct DEV_EMU_REGS { + union DEVICECNF_REG DEVICECNF; // device configuration + union CLASSID_REG CLASSID; // Class ID + Uint16 REVID; // Device ID + Uint16 PROTSTART; // Write-Read protection start + Uint16 PROTRANGE; // Write-Read protection range + Uint16 rsvd2[202]; +}; + +// +// PARTID +// +struct PARTID_BITS { // bits description + Uint16 PARTNO:8; // 7:0 Part Number + Uint16 PARTTYPE:8; // 15:8 Part Type +}; + +union PARTID_REG { + Uint16 all; + struct PARTID_BITS bit; +}; + +struct PARTID_REGS { + union PARTID_REG PARTID; // Part ID +}; + +// +// Device Emulation Register References & Function Declarations +// +extern volatile struct DEV_EMU_REGS DevEmuRegs; +extern volatile struct PARTID_REGS PartIdRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEV_EMU_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_Device.h b/F28335/DSP2833x_Device.h new file mode 100644 index 0000000..56c5a7e --- /dev/null +++ b/F28335/DSP2833x_Device.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: DSP2833x_Device.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_DEVICE_H +#define DSP2833x_DEVICE_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define TARGET 1 + +// +// User To Select Target Device +// +#define DSP28_28335 TARGET // Selects '28335/'28235 +#define DSP28_28334 0 // Selects '28334/'28234 +#define DSP28_28333 0 // Selects '28333/' +#define DSP28_28332 0 // Selects '28332/'28232 + +// +// Common CPU Definitions +// +extern cregister volatile unsigned int IFR; +extern cregister volatile unsigned int IER; + +#define EINT asm(" clrc INTM") +#define DINT asm(" setc INTM") +#define ERTM asm(" clrc DBGM") +#define DRTM asm(" setc DBGM") +#define EALLOW asm(" EALLOW") +#define EDIS asm(" EDIS") +#define ESTOP0 asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#define BIT0 0x0001 +#define BIT1 0x0002 +#define BIT2 0x0004 +#define BIT3 0x0008 +#define BIT4 0x0010 +#define BIT5 0x0020 +#define BIT6 0x0040 +#define BIT7 0x0080 +#define BIT8 0x0100 +#define BIT9 0x0200 +#define BIT10 0x0400 +#define BIT11 0x0800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 + +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// Included Peripheral Header Files +// +#include "F28335/DSP2833x_Adc.h" // ADC Registers +#include "F28335/DSP2833x_DevEmu.h" // Device Emulation Registers +#include "F28335/DSP2833x_CpuTimers.h" // 32-bit CPU Timers +#include "F28335/DSP2833x_ECan.h" // Enhanced eCAN Registers +#include "F28335/DSP2833x_ECap.h" // Enhanced Capture +#include "F28335/DSP2833x_DMA.h" // DMA Registers +#include "F28335/DSP2833x_EPwm.h" // Enhanced PWM +#include "F28335/DSP2833x_EQep.h" // Enhanced QEP +#include "F28335/DSP2833x_Gpio.h" // General Purpose I/O Registers +#include "F28335/DSP2833x_I2c.h" // I2C Registers +#include "F28335/DSP2833x_Mcbsp.h" // McBSP +#include "F28335/DSP2833x_PieCtrl.h" // PIE Control Registers +#include "F28335/DSP2833x_PieVect.h" // PIE Vector Table +#include "F28335/DSP2833x_Spi.h" // SPI Registers +#include "F28335/DSP2833x_Sci.h" // SCI Registers +#include "F28335/DSP2833x_SysCtrl.h" // System Control/Power Modes +#include "F28335/DSP2833x_XIntrupt.h" // External Interrupts +#include "F28335/DSP2833x_Xintf.h" // XINTF External Interface + +#if DSP28_28335 || DSP28_28333 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 1 +#define DSP28_ECAP6 1 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28335 || DSP28_28333 + +#if DSP28_28334 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 1 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 1 +#define DSP28_I2CA 1 +#endif // end DSP28_28334 + +#if DSP28_28332 +#define DSP28_EPWM1 1 +#define DSP28_EPWM2 1 +#define DSP28_EPWM3 1 +#define DSP28_EPWM4 1 +#define DSP28_EPWM5 1 +#define DSP28_EPWM6 1 +#define DSP28_ECAP1 1 +#define DSP28_ECAP2 1 +#define DSP28_ECAP3 1 +#define DSP28_ECAP4 1 +#define DSP28_ECAP5 0 +#define DSP28_ECAP6 0 +#define DSP28_EQEP1 1 +#define DSP28_EQEP2 1 +#define DSP28_ECANA 1 +#define DSP28_ECANB 1 +#define DSP28_MCBSPA 1 +#define DSP28_MCBSPB 0 +#define DSP28_SPIA 1 +#define DSP28_SCIA 1 +#define DSP28_SCIB 1 +#define DSP28_SCIC 0 +#define DSP28_I2CA 1 +#endif // end DSP28_28332 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_DEVICE_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_Dma_defines.h b/F28335/DSP2833x_Dma_defines.h new file mode 100644 index 0000000..1d4fbcc --- /dev/null +++ b/F28335/DSP2833x_Dma_defines.h @@ -0,0 +1,108 @@ +//########################################################################### +// +// FILE: DSP2833x_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_DMA_DEFINES_H +#define DSP2833x_DMA_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// MODE +// +// PERINTSEL bits +// +#define DMA_SEQ1INT 1 +#define DMA_SEQ2INT 2 +#define DMA_XINT1 3 +#define DMA_XINT2 4 +#define DMA_XINT3 5 +#define DMA_XINT4 6 +#define DMA_XINT5 7 +#define DMA_XINT6 8 +#define DMA_XINT7 9 +#define DMA_XINT13 10 +#define DMA_TINT0 11 +#define DMA_TINT1 12 +#define DMA_TINT2 13 +#define DMA_MXEVTA 14 +#define DMA_MREVTA 15 +#define DMA_MXREVTB 16 +#define DMA_MREVTB 17 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/F28335/DSP2833x_ECan.h b/F28335/DSP2833x_ECan.h new file mode 100644 index 0000000..6960a00 --- /dev/null +++ b/F28335/DSP2833x_ECan.h @@ -0,0 +1,1256 @@ +//########################################################################### +// +// FILE: DSP2833x_ECan.h +// +// TITLE: DSP2833x Device eCAN Register Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_ECAN_H +#define DSP2833x_ECAN_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// eCAN Control & Status Registers +// + +// +// eCAN Mailbox enable register (CANME) bit definitions +// +struct CANME_BITS { // bit description + Uint16 ME0:1; // 0 Enable Mailbox 0 + Uint16 ME1:1; // 1 Enable Mailbox 1 + Uint16 ME2:1; // 2 Enable Mailbox 2 + Uint16 ME3:1; // 3 Enable Mailbox 3 + Uint16 ME4:1; // 4 Enable Mailbox 4 + Uint16 ME5:1; // 5 Enable Mailbox 5 + Uint16 ME6:1; // 6 Enable Mailbox 6 + Uint16 ME7:1; // 7 Enable Mailbox 7 + Uint16 ME8:1; // 8 Enable Mailbox 8 + Uint16 ME9:1; // 9 Enable Mailbox 9 + Uint16 ME10:1; // 10 Enable Mailbox 10 + Uint16 ME11:1; // 11 Enable Mailbox 11 + Uint16 ME12:1; // 12 Enable Mailbox 12 + Uint16 ME13:1; // 13 Enable Mailbox 13 + Uint16 ME14:1; // 14 Enable Mailbox 14 + Uint16 ME15:1; // 15 Enable Mailbox 15 + Uint16 ME16:1; // 16 Enable Mailbox 16 + Uint16 ME17:1; // 17 Enable Mailbox 17 + Uint16 ME18:1; // 18 Enable Mailbox 18 + Uint16 ME19:1; // 19 Enable Mailbox 19 + Uint16 ME20:1; // 20 Enable Mailbox 20 + Uint16 ME21:1; // 21 Enable Mailbox 21 + Uint16 ME22:1; // 22 Enable Mailbox 22 + Uint16 ME23:1; // 23 Enable Mailbox 23 + Uint16 ME24:1; // 24 Enable Mailbox 24 + Uint16 ME25:1; // 25 Enable Mailbox 25 + Uint16 ME26:1; // 26 Enable Mailbox 26 + Uint16 ME27:1; // 27 Enable Mailbox 27 + Uint16 ME28:1; // 28 Enable Mailbox 28 + Uint16 ME29:1; // 29 Enable Mailbox 29 + Uint16 ME30:1; // 30 Enable Mailbox 30 + Uint16 ME31:1; // 31 Enable Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANME_REG { + Uint32 all; + struct CANME_BITS bit; +}; + +// +// eCAN Mailbox direction register (CANMD) bit definitions +// +struct CANMD_BITS { // bit description + Uint16 MD0:1; // 0 0 -> Tx 1 -> Rx + Uint16 MD1:1; // 1 0 -> Tx 1 -> Rx + Uint16 MD2:1; // 2 0 -> Tx 1 -> Rx + Uint16 MD3:1; // 3 0 -> Tx 1 -> Rx + Uint16 MD4:1; // 4 0 -> Tx 1 -> Rx + Uint16 MD5:1; // 5 0 -> Tx 1 -> Rx + Uint16 MD6:1; // 6 0 -> Tx 1 -> Rx + Uint16 MD7:1; // 7 0 -> Tx 1 -> Rx + Uint16 MD8:1; // 8 0 -> Tx 1 -> Rx + Uint16 MD9:1; // 9 0 -> Tx 1 -> Rx + Uint16 MD10:1; // 10 0 -> Tx 1 -> Rx + Uint16 MD11:1; // 11 0 -> Tx 1 -> Rx + Uint16 MD12:1; // 12 0 -> Tx 1 -> Rx + Uint16 MD13:1; // 13 0 -> Tx 1 -> Rx + Uint16 MD14:1; // 14 0 -> Tx 1 -> Rx + Uint16 MD15:1; // 15 0 -> Tx 1 -> Rx + Uint16 MD16:1; // 16 0 -> Tx 1 -> Rx + Uint16 MD17:1; // 17 0 -> Tx 1 -> Rx + Uint16 MD18:1; // 18 0 -> Tx 1 -> Rx + Uint16 MD19:1; // 19 0 -> Tx 1 -> Rx + Uint16 MD20:1; // 20 0 -> Tx 1 -> Rx + Uint16 MD21:1; // 21 0 -> Tx 1 -> Rx + Uint16 MD22:1; // 22 0 -> Tx 1 -> Rx + Uint16 MD23:1; // 23 0 -> Tx 1 -> Rx + Uint16 MD24:1; // 24 0 -> Tx 1 -> Rx + Uint16 MD25:1; // 25 0 -> Tx 1 -> Rx + Uint16 MD26:1; // 26 0 -> Tx 1 -> Rx + Uint16 MD27:1; // 27 0 -> Tx 1 -> Rx + Uint16 MD28:1; // 28 0 -> Tx 1 -> Rx + Uint16 MD29:1; // 29 0 -> Tx 1 -> Rx + Uint16 MD30:1; // 30 0 -> Tx 1 -> Rx + Uint16 MD31:1; // 31 0 -> Tx 1 -> Rx +}; + +// +// Allow access to the bit fields or entire register +// +union CANMD_REG { + Uint32 all; + struct CANMD_BITS bit; +}; + +// +// eCAN Transmit Request Set register (CANTRS) bit definitions +// +struct CANTRS_BITS { // bit description + Uint16 TRS0:1; // 0 TRS for Mailbox 0 + Uint16 TRS1:1; // 1 TRS for Mailbox 1 + Uint16 TRS2:1; // 2 TRS for Mailbox 2 + Uint16 TRS3:1; // 3 TRS for Mailbox 3 + Uint16 TRS4:1; // 4 TRS for Mailbox 4 + Uint16 TRS5:1; // 5 TRS for Mailbox 5 + Uint16 TRS6:1; // 6 TRS for Mailbox 6 + Uint16 TRS7:1; // 7 TRS for Mailbox 7 + Uint16 TRS8:1; // 8 TRS for Mailbox 8 + Uint16 TRS9:1; // 9 TRS for Mailbox 9 + Uint16 TRS10:1; // 10 TRS for Mailbox 10 + Uint16 TRS11:1; // 11 TRS for Mailbox 11 + Uint16 TRS12:1; // 12 TRS for Mailbox 12 + Uint16 TRS13:1; // 13 TRS for Mailbox 13 + Uint16 TRS14:1; // 14 TRS for Mailbox 14 + Uint16 TRS15:1; // 15 TRS for Mailbox 15 + Uint16 TRS16:1; // 16 TRS for Mailbox 16 + Uint16 TRS17:1; // 17 TRS for Mailbox 17 + Uint16 TRS18:1; // 18 TRS for Mailbox 18 + Uint16 TRS19:1; // 19 TRS for Mailbox 19 + Uint16 TRS20:1; // 20 TRS for Mailbox 20 + Uint16 TRS21:1; // 21 TRS for Mailbox 21 + Uint16 TRS22:1; // 22 TRS for Mailbox 22 + Uint16 TRS23:1; // 23 TRS for Mailbox 23 + Uint16 TRS24:1; // 24 TRS for Mailbox 24 + Uint16 TRS25:1; // 25 TRS for Mailbox 25 + Uint16 TRS26:1; // 26 TRS for Mailbox 26 + Uint16 TRS27:1; // 27 TRS for Mailbox 27 + Uint16 TRS28:1; // 28 TRS for Mailbox 28 + Uint16 TRS29:1; // 29 TRS for Mailbox 29 + Uint16 TRS30:1; // 30 TRS for Mailbox 30 + Uint16 TRS31:1; // 31 TRS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRS_REG { + Uint32 all; + struct CANTRS_BITS bit; +}; + +// +// eCAN Transmit Request Reset register (CANTRR) bit definitions +// +struct CANTRR_BITS { // bit description + Uint16 TRR0:1; // 0 TRR for Mailbox 0 + Uint16 TRR1:1; // 1 TRR for Mailbox 1 + Uint16 TRR2:1; // 2 TRR for Mailbox 2 + Uint16 TRR3:1; // 3 TRR for Mailbox 3 + Uint16 TRR4:1; // 4 TRR for Mailbox 4 + Uint16 TRR5:1; // 5 TRR for Mailbox 5 + Uint16 TRR6:1; // 6 TRR for Mailbox 6 + Uint16 TRR7:1; // 7 TRR for Mailbox 7 + Uint16 TRR8:1; // 8 TRR for Mailbox 8 + Uint16 TRR9:1; // 9 TRR for Mailbox 9 + Uint16 TRR10:1; // 10 TRR for Mailbox 10 + Uint16 TRR11:1; // 11 TRR for Mailbox 11 + Uint16 TRR12:1; // 12 TRR for Mailbox 12 + Uint16 TRR13:1; // 13 TRR for Mailbox 13 + Uint16 TRR14:1; // 14 TRR for Mailbox 14 + Uint16 TRR15:1; // 15 TRR for Mailbox 15 + Uint16 TRR16:1; // 16 TRR for Mailbox 16 + Uint16 TRR17:1; // 17 TRR for Mailbox 17 + Uint16 TRR18:1; // 18 TRR for Mailbox 18 + Uint16 TRR19:1; // 19 TRR for Mailbox 19 + Uint16 TRR20:1; // 20 TRR for Mailbox 20 + Uint16 TRR21:1; // 21 TRR for Mailbox 21 + Uint16 TRR22:1; // 22 TRR for Mailbox 22 + Uint16 TRR23:1; // 23 TRR for Mailbox 23 + Uint16 TRR24:1; // 24 TRR for Mailbox 24 + Uint16 TRR25:1; // 25 TRR for Mailbox 25 + Uint16 TRR26:1; // 26 TRR for Mailbox 26 + Uint16 TRR27:1; // 27 TRR for Mailbox 27 + Uint16 TRR28:1; // 28 TRR for Mailbox 28 + Uint16 TRR29:1; // 29 TRR for Mailbox 29 + Uint16 TRR30:1; // 30 TRR for Mailbox 30 + Uint16 TRR31:1; // 31 TRR for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTRR_REG { + Uint32 all; + struct CANTRR_BITS bit; +}; + +// +// eCAN Transmit Acknowledge register (CANTA) bit definitions +// +struct CANTA_BITS { // bit description + Uint16 TA0:1; // 0 TA for Mailbox 0 + Uint16 TA1:1; // 1 TA for Mailbox 1 + Uint16 TA2:1; // 2 TA for Mailbox 2 + Uint16 TA3:1; // 3 TA for Mailbox 3 + Uint16 TA4:1; // 4 TA for Mailbox 4 + Uint16 TA5:1; // 5 TA for Mailbox 5 + Uint16 TA6:1; // 6 TA for Mailbox 6 + Uint16 TA7:1; // 7 TA for Mailbox 7 + Uint16 TA8:1; // 8 TA for Mailbox 8 + Uint16 TA9:1; // 9 TA for Mailbox 9 + Uint16 TA10:1; // 10 TA for Mailbox 10 + Uint16 TA11:1; // 11 TA for Mailbox 11 + Uint16 TA12:1; // 12 TA for Mailbox 12 + Uint16 TA13:1; // 13 TA for Mailbox 13 + Uint16 TA14:1; // 14 TA for Mailbox 14 + Uint16 TA15:1; // 15 TA for Mailbox 15 + Uint16 TA16:1; // 16 TA for Mailbox 16 + Uint16 TA17:1; // 17 TA for Mailbox 17 + Uint16 TA18:1; // 18 TA for Mailbox 18 + Uint16 TA19:1; // 19 TA for Mailbox 19 + Uint16 TA20:1; // 20 TA for Mailbox 20 + Uint16 TA21:1; // 21 TA for Mailbox 21 + Uint16 TA22:1; // 22 TA for Mailbox 22 + Uint16 TA23:1; // 23 TA for Mailbox 23 + Uint16 TA24:1; // 24 TA for Mailbox 24 + Uint16 TA25:1; // 25 TA for Mailbox 25 + Uint16 TA26:1; // 26 TA for Mailbox 26 + Uint16 TA27:1; // 27 TA for Mailbox 27 + Uint16 TA28:1; // 28 TA for Mailbox 28 + Uint16 TA29:1; // 29 TA for Mailbox 29 + Uint16 TA30:1; // 30 TA for Mailbox 30 + Uint16 TA31:1; // 31 TA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTA_REG { + Uint32 all; + struct CANTA_BITS bit; +}; + +// +// eCAN Transmit Abort Acknowledge register (CANAA) bit definitions +// +struct CANAA_BITS { // bit description + Uint16 AA0:1; // 0 AA for Mailbox 0 + Uint16 AA1:1; // 1 AA for Mailbox 1 + Uint16 AA2:1; // 2 AA for Mailbox 2 + Uint16 AA3:1; // 3 AA for Mailbox 3 + Uint16 AA4:1; // 4 AA for Mailbox 4 + Uint16 AA5:1; // 5 AA for Mailbox 5 + Uint16 AA6:1; // 6 AA for Mailbox 6 + Uint16 AA7:1; // 7 AA for Mailbox 7 + Uint16 AA8:1; // 8 AA for Mailbox 8 + Uint16 AA9:1; // 9 AA for Mailbox 9 + Uint16 AA10:1; // 10 AA for Mailbox 10 + Uint16 AA11:1; // 11 AA for Mailbox 11 + Uint16 AA12:1; // 12 AA for Mailbox 12 + Uint16 AA13:1; // 13 AA for Mailbox 13 + Uint16 AA14:1; // 14 AA for Mailbox 14 + Uint16 AA15:1; // 15 AA for Mailbox 15 + Uint16 AA16:1; // 16 AA for Mailbox 16 + Uint16 AA17:1; // 17 AA for Mailbox 17 + Uint16 AA18:1; // 18 AA for Mailbox 18 + Uint16 AA19:1; // 19 AA for Mailbox 19 + Uint16 AA20:1; // 20 AA for Mailbox 20 + Uint16 AA21:1; // 21 AA for Mailbox 21 + Uint16 AA22:1; // 22 AA for Mailbox 22 + Uint16 AA23:1; // 23 AA for Mailbox 23 + Uint16 AA24:1; // 24 AA for Mailbox 24 + Uint16 AA25:1; // 25 AA for Mailbox 25 + Uint16 AA26:1; // 26 AA for Mailbox 26 + Uint16 AA27:1; // 27 AA for Mailbox 27 + Uint16 AA28:1; // 28 AA for Mailbox 28 + Uint16 AA29:1; // 29 AA for Mailbox 29 + Uint16 AA30:1; // 30 AA for Mailbox 30 + Uint16 AA31:1; // 31 AA for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANAA_REG { + Uint32 all; + struct CANAA_BITS bit; +}; + +// +// eCAN Received Message Pending register (CANRMP) bit definitions +// +struct CANRMP_BITS { // bit description + Uint16 RMP0:1; // 0 RMP for Mailbox 0 + Uint16 RMP1:1; // 1 RMP for Mailbox 1 + Uint16 RMP2:1; // 2 RMP for Mailbox 2 + Uint16 RMP3:1; // 3 RMP for Mailbox 3 + Uint16 RMP4:1; // 4 RMP for Mailbox 4 + Uint16 RMP5:1; // 5 RMP for Mailbox 5 + Uint16 RMP6:1; // 6 RMP for Mailbox 6 + Uint16 RMP7:1; // 7 RMP for Mailbox 7 + Uint16 RMP8:1; // 8 RMP for Mailbox 8 + Uint16 RMP9:1; // 9 RMP for Mailbox 9 + Uint16 RMP10:1; // 10 RMP for Mailbox 10 + Uint16 RMP11:1; // 11 RMP for Mailbox 11 + Uint16 RMP12:1; // 12 RMP for Mailbox 12 + Uint16 RMP13:1; // 13 RMP for Mailbox 13 + Uint16 RMP14:1; // 14 RMP for Mailbox 14 + Uint16 RMP15:1; // 15 RMP for Mailbox 15 + Uint16 RMP16:1; // 16 RMP for Mailbox 16 + Uint16 RMP17:1; // 17 RMP for Mailbox 17 + Uint16 RMP18:1; // 18 RMP for Mailbox 18 + Uint16 RMP19:1; // 19 RMP for Mailbox 19 + Uint16 RMP20:1; // 20 RMP for Mailbox 20 + Uint16 RMP21:1; // 21 RMP for Mailbox 21 + Uint16 RMP22:1; // 22 RMP for Mailbox 22 + Uint16 RMP23:1; // 23 RMP for Mailbox 23 + Uint16 RMP24:1; // 24 RMP for Mailbox 24 + Uint16 RMP25:1; // 25 RMP for Mailbox 25 + Uint16 RMP26:1; // 26 RMP for Mailbox 26 + Uint16 RMP27:1; // 27 RMP for Mailbox 27 + Uint16 RMP28:1; // 28 RMP for Mailbox 28 + Uint16 RMP29:1; // 29 RMP for Mailbox 29 + Uint16 RMP30:1; // 30 RMP for Mailbox 30 + Uint16 RMP31:1; // 31 RMP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRMP_REG { + Uint32 all; + struct CANRMP_BITS bit; +}; + +// +// eCAN Received Message Lost register (CANRML) bit definitions +// +struct CANRML_BITS { // bit description + Uint16 RML0:1; // 0 RML for Mailbox 0 + Uint16 RML1:1; // 1 RML for Mailbox 1 + Uint16 RML2:1; // 2 RML for Mailbox 2 + Uint16 RML3:1; // 3 RML for Mailbox 3 + Uint16 RML4:1; // 4 RML for Mailbox 4 + Uint16 RML5:1; // 5 RML for Mailbox 5 + Uint16 RML6:1; // 6 RML for Mailbox 6 + Uint16 RML7:1; // 7 RML for Mailbox 7 + Uint16 RML8:1; // 8 RML for Mailbox 8 + Uint16 RML9:1; // 9 RML for Mailbox 9 + Uint16 RML10:1; // 10 RML for Mailbox 10 + Uint16 RML11:1; // 11 RML for Mailbox 11 + Uint16 RML12:1; // 12 RML for Mailbox 12 + Uint16 RML13:1; // 13 RML for Mailbox 13 + Uint16 RML14:1; // 14 RML for Mailbox 14 + Uint16 RML15:1; // 15 RML for Mailbox 15 + Uint16 RML16:1; // 16 RML for Mailbox 16 + Uint16 RML17:1; // 17 RML for Mailbox 17 + Uint16 RML18:1; // 18 RML for Mailbox 18 + Uint16 RML19:1; // 19 RML for Mailbox 19 + Uint16 RML20:1; // 20 RML for Mailbox 20 + Uint16 RML21:1; // 21 RML for Mailbox 21 + Uint16 RML22:1; // 22 RML for Mailbox 22 + Uint16 RML23:1; // 23 RML for Mailbox 23 + Uint16 RML24:1; // 24 RML for Mailbox 24 + Uint16 RML25:1; // 25 RML for Mailbox 25 + Uint16 RML26:1; // 26 RML for Mailbox 26 + Uint16 RML27:1; // 27 RML for Mailbox 27 + Uint16 RML28:1; // 28 RML for Mailbox 28 + Uint16 RML29:1; // 29 RML for Mailbox 29 + Uint16 RML30:1; // 30 RML for Mailbox 30 + Uint16 RML31:1; // 31 RML for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRML_REG { + Uint32 all; + struct CANRML_BITS bit; +}; + +// +// eCAN Remote Frame Pending register (CANRFP) bit definitions +// +struct CANRFP_BITS { // bit description + Uint16 RFP0:1; // 0 RFP for Mailbox 0 + Uint16 RFP1:1; // 1 RFP for Mailbox 1 + Uint16 RFP2:1; // 2 RFP for Mailbox 2 + Uint16 RFP3:1; // 3 RFP for Mailbox 3 + Uint16 RFP4:1; // 4 RFP for Mailbox 4 + Uint16 RFP5:1; // 5 RFP for Mailbox 5 + Uint16 RFP6:1; // 6 RFP for Mailbox 6 + Uint16 RFP7:1; // 7 RFP for Mailbox 7 + Uint16 RFP8:1; // 8 RFP for Mailbox 8 + Uint16 RFP9:1; // 9 RFP for Mailbox 9 + Uint16 RFP10:1; // 10 RFP for Mailbox 10 + Uint16 RFP11:1; // 11 RFP for Mailbox 11 + Uint16 RFP12:1; // 12 RFP for Mailbox 12 + Uint16 RFP13:1; // 13 RFP for Mailbox 13 + Uint16 RFP14:1; // 14 RFP for Mailbox 14 + Uint16 RFP15:1; // 15 RFP for Mailbox 15 + Uint16 RFP16:1; // 16 RFP for Mailbox 16 + Uint16 RFP17:1; // 17 RFP for Mailbox 17 + Uint16 RFP18:1; // 18 RFP for Mailbox 18 + Uint16 RFP19:1; // 19 RFP for Mailbox 19 + Uint16 RFP20:1; // 20 RFP for Mailbox 20 + Uint16 RFP21:1; // 21 RFP for Mailbox 21 + Uint16 RFP22:1; // 22 RFP for Mailbox 22 + Uint16 RFP23:1; // 23 RFP for Mailbox 23 + Uint16 RFP24:1; // 24 RFP for Mailbox 24 + Uint16 RFP25:1; // 25 RFP for Mailbox 25 + Uint16 RFP26:1; // 26 RFP for Mailbox 26 + Uint16 RFP27:1; // 27 RFP for Mailbox 27 + Uint16 RFP28:1; // 28 RFP for Mailbox 28 + Uint16 RFP29:1; // 29 RFP for Mailbox 29 + Uint16 RFP30:1; // 30 RFP for Mailbox 30 + Uint16 RFP31:1; // 31 RFP for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANRFP_REG { + Uint32 all; + struct CANRFP_BITS bit; +}; + +// +// eCAN Global Acceptance Mask register (CANGAM) bit definitions +// +struct CANGAM_BITS { // bits description + Uint16 GAM150:16; // 15:0 Global acceptance mask bits 0-15 + Uint16 GAM2816:13; // 28:16 Global acceptance mask bits 16-28 + Uint16 rsvd:2; // 30:29 reserved + Uint16 AMI:1; // 31 AMI bit +}; + +// +// Allow access to the bit fields or entire register +// +union CANGAM_REG { + Uint32 all; + struct CANGAM_BITS bit; +}; + +// +// eCAN Master Control register (CANMC) bit definitions +// +struct CANMC_BITS { // bits description + Uint16 MBNR:5; // 4:0 MBX # for CDR bit + Uint16 SRES:1; // 5 Soft reset + Uint16 STM:1; // 6 Self-test mode + Uint16 ABO:1; // 7 Auto bus-on + Uint16 CDR:1; // 8 Change data request + Uint16 WUBA:1; // 9 Wake-up on bus activity + Uint16 DBO:1; // 10 Data-byte order + Uint16 PDR:1; // 11 Power-down mode request + Uint16 CCR:1; // 12 Change configuration request + Uint16 SCB:1; // 13 SCC compatibility bit + Uint16 TCC:1; // 14 TSC MSB clear bit + Uint16 MBCC:1; // 15 TSC clear bit thru mailbox 16 + Uint16 SUSP:1; // 16 SUSPEND free/soft bit + Uint16 rsvd:15; // 31:17 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMC_REG { + Uint32 all; + struct CANMC_BITS bit; +}; + +// +// eCAN Bit -timing configuration register (CANBTC) bit definitions +// +struct CANBTC_BITS { // bits description + Uint16 TSEG2REG:3; // 2:0 TSEG2 register value + Uint16 TSEG1REG:4; // 6:3 TSEG1 register value + Uint16 SAM:1; // 7 Sample-point setting + Uint16 SJWREG:2; // 9:8 Synchroniztion Jump Width register value + Uint16 rsvd1:6; // 15:10 reserved + Uint16 BRPREG:8; // 23:16 Baudrate prescaler register value + Uint16 rsvd2:8; // 31:24 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANBTC_REG { + Uint32 all; + struct CANBTC_BITS bit; +}; + +// +// eCAN Error & Status register (CANES) bit definitions +// +struct CANES_BITS { // bits description + Uint16 TM:1; // 0 Transmit Mode + Uint16 RM:1; // 1 Receive Mode + Uint16 rsvd1:1; // 2 reserved + Uint16 PDA:1; // 3 Power-down acknowledge + Uint16 CCE:1; // 4 Change Configuration Enable + Uint16 SMA:1; // 5 Suspend Mode Acknowledge + Uint16 rsvd2:10; // 15:6 reserved + Uint16 EW:1; // 16 Warning status + Uint16 EP:1; // 17 Error Passive status + Uint16 BO:1; // 18 Bus-off status + Uint16 ACKE:1; // 19 Acknowledge error + Uint16 SE:1; // 20 Stuff error + Uint16 CRCE:1; // 21 CRC error + Uint16 SA1:1; // 22 Stuck at Dominant error + Uint16 BE:1; // 23 Bit error + Uint16 FE:1; // 24 Framing error + Uint16 rsvd3:7; // 31:25 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANES_REG { + Uint32 all; + struct CANES_BITS bit; +}; + +// +// eCAN Transmit Error Counter register (CANTEC) bit definitions +// +struct CANTEC_BITS { // bits description + Uint16 TEC:8; // 7:0 TEC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTEC_REG { + Uint32 all; + struct CANTEC_BITS bit; +}; + +// +// eCAN Receive Error Counter register (CANREC) bit definitions +// +struct CANREC_BITS { // bits description + Uint16 REC:8; // 7:0 REC + Uint16 rsvd1:8; // 15:8 reserved + Uint16 rsvd2:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANREC_REG { + Uint32 all; + struct CANREC_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions +// +struct CANGIF0_BITS { // bits description + Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF0:1; // 8 Warning level interrupt flag + Uint16 EPIF0:1; // 9 Error-passive interrupt flag + Uint16 BOIF0:1; // 10 Bus-off interrupt flag + Uint16 RMLIF0:1; // 11 Received message lost interrupt flag + Uint16 WUIF0:1; // 12 Wakeup interrupt flag + Uint16 WDIF0:1; // 13 Write denied interrupt flag + Uint16 AAIF0:1; // 14 Abort Ack interrupt flag + Uint16 GMIF0:1; // 15 Global MBX interrupt flag + Uint16 TCOF0:1; // 16 TSC Overflow flag + Uint16 MTOF0:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF0_REG { + Uint32 all; + struct CANGIF0_BITS bit; +}; + +// +// eCAN Global Interrupt Mask register (CANGIM) bit definitions +// +struct CANGIM_BITS { // bits description + Uint16 I0EN:1; // 0 Interrupt 0 enable + Uint16 I1EN:1; // 1 Interrupt 1 enable + Uint16 GIL:1; // 2 Global Interrupt Level + Uint16 rsvd1:5; // 7:3 reserved + Uint16 WLIM:1; // 8 Warning level interrupt mask + Uint16 EPIM:1; // 9 Error-passive interrupt mask + Uint16 BOIM:1; // 10 Bus-off interrupt mask + Uint16 RMLIM:1; // 11 Received message lost interrupt mask + Uint16 WUIM:1; // 12 Wakeup interrupt mask + Uint16 WDIM:1; // 13 Write denied interrupt mask + Uint16 AAIM:1; // 14 Abort Ack interrupt mask + Uint16 rsvd2:1; // 15 reserved + Uint16 TCOM:1; // 16 TSC overflow interrupt mask + Uint16 MTOM:1; // 17 MBX Timeout interrupt mask + Uint16 rsvd3:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIM_REG { + Uint32 all; + struct CANGIM_BITS bit; +}; + +// +// eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions +// +struct CANGIF1_BITS { // bits description + Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector + Uint16 rsvd1:3; // 7:5 reserved + Uint16 WLIF1:1; // 8 Warning level interrupt flag + Uint16 EPIF1:1; // 9 Error-passive interrupt flag + Uint16 BOIF1:1; // 10 Bus-off interrupt flag + Uint16 RMLIF1:1; // 11 Received message lost interrupt flag + Uint16 WUIF1:1; // 12 Wakeup interrupt flag + Uint16 WDIF1:1; // 13 Write denied interrupt flag + Uint16 AAIF1:1; // 14 Abort Ack interrupt flag + Uint16 GMIF1:1; // 15 Global MBX interrupt flag + Uint16 TCOF1:1; // 16 TSC Overflow flag + Uint16 MTOF1:1; // 17 Mailbox Timeout flag + Uint16 rsvd2:14; // 31:18 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANGIF1_REG { + Uint32 all; + struct CANGIF1_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions +// +struct CANMIM_BITS { // bit description + Uint16 MIM0:1; // 0 MIM for Mailbox 0 + Uint16 MIM1:1; // 1 MIM for Mailbox 1 + Uint16 MIM2:1; // 2 MIM for Mailbox 2 + Uint16 MIM3:1; // 3 MIM for Mailbox 3 + Uint16 MIM4:1; // 4 MIM for Mailbox 4 + Uint16 MIM5:1; // 5 MIM for Mailbox 5 + Uint16 MIM6:1; // 6 MIM for Mailbox 6 + Uint16 MIM7:1; // 7 MIM for Mailbox 7 + Uint16 MIM8:1; // 8 MIM for Mailbox 8 + Uint16 MIM9:1; // 9 MIM for Mailbox 9 + Uint16 MIM10:1; // 10 MIM for Mailbox 10 + Uint16 MIM11:1; // 11 MIM for Mailbox 11 + Uint16 MIM12:1; // 12 MIM for Mailbox 12 + Uint16 MIM13:1; // 13 MIM for Mailbox 13 + Uint16 MIM14:1; // 14 MIM for Mailbox 14 + Uint16 MIM15:1; // 15 MIM for Mailbox 15 + Uint16 MIM16:1; // 16 MIM for Mailbox 16 + Uint16 MIM17:1; // 17 MIM for Mailbox 17 + Uint16 MIM18:1; // 18 MIM for Mailbox 18 + Uint16 MIM19:1; // 19 MIM for Mailbox 19 + Uint16 MIM20:1; // 20 MIM for Mailbox 20 + Uint16 MIM21:1; // 21 MIM for Mailbox 21 + Uint16 MIM22:1; // 22 MIM for Mailbox 22 + Uint16 MIM23:1; // 23 MIM for Mailbox 23 + Uint16 MIM24:1; // 24 MIM for Mailbox 24 + Uint16 MIM25:1; // 25 MIM for Mailbox 25 + Uint16 MIM26:1; // 26 MIM for Mailbox 26 + Uint16 MIM27:1; // 27 MIM for Mailbox 27 + Uint16 MIM28:1; // 28 MIM for Mailbox 28 + Uint16 MIM29:1; // 29 MIM for Mailbox 29 + Uint16 MIM30:1; // 30 MIM for Mailbox 30 + Uint16 MIM31:1; // 31 MIM for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIM_REG { + Uint32 all; + struct CANMIM_BITS bit; +}; + +// +// eCAN Mailbox Interrupt Level register (CANMIL) bit definitions +// +struct CANMIL_BITS { // bit description + Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6 + Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMIL_REG { + Uint32 all; + struct CANMIL_BITS bit; +}; + +// +// eCAN Overwrite Protection Control register (CANOPC) bit definitions +// +struct CANOPC_BITS { // bit description + Uint16 OPC0:1; // 0 OPC for Mailbox 0 + Uint16 OPC1:1; // 1 OPC for Mailbox 1 + Uint16 OPC2:1; // 2 OPC for Mailbox 2 + Uint16 OPC3:1; // 3 OPC for Mailbox 3 + Uint16 OPC4:1; // 4 OPC for Mailbox 4 + Uint16 OPC5:1; // 5 OPC for Mailbox 5 + Uint16 OPC6:1; // 6 OPC for Mailbox 6 + Uint16 OPC7:1; // 7 OPC for Mailbox 7 + Uint16 OPC8:1; // 8 OPC for Mailbox 8 + Uint16 OPC9:1; // 9 OPC for Mailbox 9 + Uint16 OPC10:1; // 10 OPC for Mailbox 10 + Uint16 OPC11:1; // 11 OPC for Mailbox 11 + Uint16 OPC12:1; // 12 OPC for Mailbox 12 + Uint16 OPC13:1; // 13 OPC for Mailbox 13 + Uint16 OPC14:1; // 14 OPC for Mailbox 14 + Uint16 OPC15:1; // 15 OPC for Mailbox 15 + Uint16 OPC16:1; // 16 OPC for Mailbox 16 + Uint16 OPC17:1; // 17 OPC for Mailbox 17 + Uint16 OPC18:1; // 18 OPC for Mailbox 18 + Uint16 OPC19:1; // 19 OPC for Mailbox 19 + Uint16 OPC20:1; // 20 OPC for Mailbox 20 + Uint16 OPC21:1; // 21 OPC for Mailbox 21 + Uint16 OPC22:1; // 22 OPC for Mailbox 22 + Uint16 OPC23:1; // 23 OPC for Mailbox 23 + Uint16 OPC24:1; // 24 OPC for Mailbox 24 + Uint16 OPC25:1; // 25 OPC for Mailbox 25 + Uint16 OPC26:1; // 26 OPC for Mailbox 26 + Uint16 OPC27:1; // 27 OPC for Mailbox 27 + Uint16 OPC28:1; // 28 OPC for Mailbox 28 + Uint16 OPC29:1; // 29 OPC for Mailbox 29 + Uint16 OPC30:1; // 30 OPC for Mailbox 30 + Uint16 OPC31:1; // 31 OPC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANOPC_REG { + Uint32 all; + struct CANOPC_BITS bit; +}; + +// +// eCAN TX I/O Control Register (CANTIOC) bit definitions +// +struct CANTIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 TXFUNC:1; // 3 TXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANTIOC_REG { + Uint32 all; + struct CANTIOC_BITS bit; +}; + +// +// eCAN RX I/O Control Register (CANRIOC) bit definitions +// +struct CANRIOC_BITS { // bits description + Uint16 rsvd1:3; // 2:0 reserved + Uint16 RXFUNC:1; // 3 RXFUNC + Uint16 rsvd2:12; // 15:4 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANRIOC_REG { + Uint32 all; + struct CANRIOC_BITS bit; +}; + +// +// eCAN Time-out Control register (CANTOC) bit definitions +// +struct CANTOC_BITS { // bit description + Uint16 TOC0:1; // 0 TOC for Mailbox 0 + Uint16 TOC1:1; // 1 TOC for Mailbox 1 + Uint16 TOC2:1; // 2 TOC for Mailbox 2 + Uint16 TOC3:1; // 3 TOC for Mailbox 3 + Uint16 TOC4:1; // 4 TOC for Mailbox 4 + Uint16 TOC5:1; // 5 TOC for Mailbox 5 + Uint16 TOC6:1; // 6 TOC for Mailbox 6 + Uint16 TOC7:1; // 7 TOC for Mailbox 7 + Uint16 TOC8:1; // 8 TOC for Mailbox 8 + Uint16 TOC9:1; // 9 TOC for Mailbox 9 + Uint16 TOC10:1; // 10 TOC for Mailbox 10 + Uint16 TOC11:1; // 11 TOC for Mailbox 11 + Uint16 TOC12:1; // 12 TOC for Mailbox 12 + Uint16 TOC13:1; // 13 TOC for Mailbox 13 + Uint16 TOC14:1; // 14 TOC for Mailbox 14 + Uint16 TOC15:1; // 15 TOC for Mailbox 15 + Uint16 TOC16:1; // 16 TOC for Mailbox 16 + Uint16 TOC17:1; // 17 TOC for Mailbox 17 + Uint16 TOC18:1; // 18 TOC for Mailbox 18 + Uint16 TOC19:1; // 19 TOC for Mailbox 19 + Uint16 TOC20:1; // 20 TOC for Mailbox 20 + Uint16 TOC21:1; // 21 TOC for Mailbox 21 + Uint16 TOC22:1; // 22 TOC for Mailbox 22 + Uint16 TOC23:1; // 23 TOC for Mailbox 23 + Uint16 TOC24:1; // 24 TOC for Mailbox 24 + Uint16 TOC25:1; // 25 TOC for Mailbox 25 + Uint16 TOC26:1; // 26 TOC for Mailbox 26 + Uint16 TOC27:1; // 27 TOC for Mailbox 27 + Uint16 TOC28:1; // 28 TOC for Mailbox 28 + Uint16 TOC29:1; // 29 TOC for Mailbox 29 + Uint16 TOC30:1; // 30 TOC for Mailbox 30 + Uint16 TOC31:1; // 31 TOC for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOC_REG { + Uint32 all; + struct CANTOC_BITS bit; +}; + +// +// eCAN Time-out Status register (CANTOS) bit definitions +// +struct CANTOS_BITS { // bit description + Uint16 TOS0:1; // 0 TOS for Mailbox 0 + Uint16 TOS1:1; // 1 TOS for Mailbox 1 + Uint16 TOS2:1; // 2 TOS for Mailbox 2 + Uint16 TOS3:1; // 3 TOS for Mailbox 3 + Uint16 TOS4:1; // 4 TOS for Mailbox 4 + Uint16 TOS5:1; // 5 TOS for Mailbox 5 + Uint16 TOS6:1; // 6 TOS for Mailbox 6 + Uint16 TOS7:1; // 7 TOS for Mailbox 7 + Uint16 TOS8:1; // 8 TOS for Mailbox 8 + Uint16 TOS9:1; // 9 TOS for Mailbox 9 + Uint16 TOS10:1; // 10 TOS for Mailbox 10 + Uint16 TOS11:1; // 11 TOS for Mailbox 11 + Uint16 TOS12:1; // 12 TOS for Mailbox 12 + Uint16 TOS13:1; // 13 TOS for Mailbox 13 + Uint16 TOS14:1; // 14 TOS for Mailbox 14 + Uint16 TOS15:1; // 15 TOS for Mailbox 15 + Uint16 TOS16:1; // 16 TOS for Mailbox 16 + Uint16 TOS17:1; // 17 TOS for Mailbox 17 + Uint16 TOS18:1; // 18 TOS for Mailbox 18 + Uint16 TOS19:1; // 19 TOS for Mailbox 19 + Uint16 TOS20:1; // 20 TOS for Mailbox 20 + Uint16 TOS21:1; // 21 TOS for Mailbox 21 + Uint16 TOS22:1; // 22 TOS for Mailbox 22 + Uint16 TOS23:1; // 23 TOS for Mailbox 23 + Uint16 TOS24:1; // 24 TOS for Mailbox 24 + Uint16 TOS25:1; // 25 TOS for Mailbox 25 + Uint16 TOS26:1; // 26 TOS for Mailbox 26 + Uint16 TOS27:1; // 27 TOS for Mailbox 27 + Uint16 TOS28:1; // 28 TOS for Mailbox 28 + Uint16 TOS29:1; // 29 TOS for Mailbox 29 + Uint16 TOS30:1; // 30 TOS for Mailbox 30 + Uint16 TOS31:1; // 31 TOS for Mailbox 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANTOS_REG { + Uint32 all; + struct CANTOS_BITS bit; +}; + +// +// eCAN Control & Status register file +// +struct ECAN_REGS { + union CANME_REG CANME; // Mailbox Enable + union CANMD_REG CANMD; // Mailbox Direction + union CANTRS_REG CANTRS; // Transmit Request Set + union CANTRR_REG CANTRR; // Transmit Request Reset + union CANTA_REG CANTA; // Transmit Acknowledge + union CANAA_REG CANAA; // Abort Acknowledge + union CANRMP_REG CANRMP; // Received Message Pending + union CANRML_REG CANRML; // Received Message Lost + union CANRFP_REG CANRFP; // Remote Frame Pending + union CANGAM_REG CANGAM; // Global Acceptance Mask + union CANMC_REG CANMC; // Master Control + union CANBTC_REG CANBTC; // Bit Timing + union CANES_REG CANES; // Error Status + union CANTEC_REG CANTEC; // Transmit Error Counter + union CANREC_REG CANREC; // Receive Error Counter + union CANGIF0_REG CANGIF0; // Global Interrupt Flag 0 + union CANGIM_REG CANGIM; // Global Interrupt Mask 0 + union CANGIF1_REG CANGIF1; // Global Interrupt Flag 1 + union CANMIM_REG CANMIM; // Mailbox Interrupt Mask + union CANMIL_REG CANMIL; // Mailbox Interrupt Level + union CANOPC_REG CANOPC; // Overwrite Protection Control + union CANTIOC_REG CANTIOC; // TX I/O Control + union CANRIOC_REG CANRIOC; // RX I/O Control + Uint32 CANTSC; // Time-stamp counter + union CANTOC_REG CANTOC; // Time-out Control + union CANTOS_REG CANTOS; // Time-out Status +}; + +// +// eCAN Mailbox Registers +// + +// +// eCAN Message ID (MSGID) bit definitions +// +struct CANMSGID_BITS { // bits description + Uint16 EXTMSGID_L:16; // 0:15 + Uint16 EXTMSGID_H:2; // 16:17 + Uint16 STDMSGID:11; // 18:28 + Uint16 AAM:1; // 29 + Uint16 AME:1; // 30 + Uint16 IDE:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGID_REG { + Uint32 all; + struct CANMSGID_BITS bit; +}; + +// +// eCAN Message Control Register (MSGCTRL) bit definitions +// +struct CANMSGCTRL_BITS { // bits description + Uint16 DLC:4; // 0:3 + Uint16 RTR:1; // 4 + Uint16 rsvd1:3; // 7:5 reserved + Uint16 TPL:5; // 12:8 + Uint16 rsvd2:3; // 15:13 reserved + Uint16 rsvd3:16; // 31:16 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union CANMSGCTRL_REG { + Uint32 all; + struct CANMSGCTRL_BITS bit; +}; + +// +// eCAN Message Data Register low (MDR_L) word definitions +// +struct CANMDL_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_L) byte definitions +// +struct CANMDL_BYTES { // bits description + Uint16 BYTE3:8; // 31:24 + Uint16 BYTE2:8; // 23:16 + Uint16 BYTE1:8; // 15:8 + Uint16 BYTE0:8; // 7:0 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDL_REG { + Uint32 all; + struct CANMDL_WORDS word; + struct CANMDL_BYTES byte; +}; + +// +// eCAN Message Data Register high (MDR_H) word definitions +// +struct CANMDH_WORDS { // bits description + Uint16 LOW_WORD:16; // 0:15 + Uint16 HI_WORD:16; // 31:16 +}; + +// +// eCAN Message Data Register low (MDR_H) byte definitions +// +struct CANMDH_BYTES { // bits description + Uint16 BYTE7:8; // 63:56 + Uint16 BYTE6:8; // 55:48 + Uint16 BYTE5:8; // 47:40 + Uint16 BYTE4:8; // 39:32 +}; + +// +// Allow access to the bit fields or entire register +// +union CANMDH_REG { + Uint32 all; + struct CANMDH_WORDS word; + struct CANMDH_BYTES byte; +}; + +struct MBOX { + union CANMSGID_REG MSGID; + union CANMSGCTRL_REG MSGCTRL; + union CANMDL_REG MDL; + union CANMDH_REG MDH; +}; + +// +// eCAN Mailboxes +// +struct ECAN_MBOXES { + struct MBOX MBOX0; + struct MBOX MBOX1; + struct MBOX MBOX2; + struct MBOX MBOX3; + struct MBOX MBOX4; + struct MBOX MBOX5; + struct MBOX MBOX6; + struct MBOX MBOX7; + struct MBOX MBOX8; + struct MBOX MBOX9; + struct MBOX MBOX10; + struct MBOX MBOX11; + struct MBOX MBOX12; + struct MBOX MBOX13; + struct MBOX MBOX14; + struct MBOX MBOX15; + struct MBOX MBOX16; + struct MBOX MBOX17; + struct MBOX MBOX18; + struct MBOX MBOX19; + struct MBOX MBOX20; + struct MBOX MBOX21; + struct MBOX MBOX22; + struct MBOX MBOX23; + struct MBOX MBOX24; + struct MBOX MBOX25; + struct MBOX MBOX26; + struct MBOX MBOX27; + struct MBOX MBOX28; + struct MBOX MBOX29; + struct MBOX MBOX30; + struct MBOX MBOX31; +}; + +// +// eCAN Local Acceptance Mask (LAM) bit definitions +// +struct CANLAM_BITS { // bits description + Uint16 LAM_L:16; // 0:15 + Uint16 LAM_H:13; // 16:28 + Uint16 rsvd1:2; // 29:30 reserved + Uint16 LAMI:1; // 31 +}; + +// +// Allow access to the bit fields or entire register +// +union CANLAM_REG { + Uint32 all; + struct CANLAM_BITS bit; +}; + +// +// eCAN Local Acceptance Masks +// + +// +// eCAN LAM File +// +struct LAM_REGS { + union CANLAM_REG LAM0; + union CANLAM_REG LAM1; + union CANLAM_REG LAM2; + union CANLAM_REG LAM3; + union CANLAM_REG LAM4; + union CANLAM_REG LAM5; + union CANLAM_REG LAM6; + union CANLAM_REG LAM7; + union CANLAM_REG LAM8; + union CANLAM_REG LAM9; + union CANLAM_REG LAM10; + union CANLAM_REG LAM11; + union CANLAM_REG LAM12; + union CANLAM_REG LAM13; + union CANLAM_REG LAM14; + union CANLAM_REG LAM15; + union CANLAM_REG LAM16; + union CANLAM_REG LAM17; + union CANLAM_REG LAM18; + union CANLAM_REG LAM19; + union CANLAM_REG LAM20; + union CANLAM_REG LAM21; + union CANLAM_REG LAM22; + union CANLAM_REG LAM23; + union CANLAM_REG LAM24; + union CANLAM_REG LAM25; + union CANLAM_REG LAM26; + union CANLAM_REG LAM27; + union CANLAM_REG LAM28; + union CANLAM_REG LAM29; + union CANLAM_REG LAM30; + union CANLAM_REG LAM31; +}; + +// +// Mailbox MOTS File +// +struct MOTS_REGS { + Uint32 MOTS0; + Uint32 MOTS1; + Uint32 MOTS2; + Uint32 MOTS3; + Uint32 MOTS4; + Uint32 MOTS5; + Uint32 MOTS6; + Uint32 MOTS7; + Uint32 MOTS8; + Uint32 MOTS9; + Uint32 MOTS10; + Uint32 MOTS11; + Uint32 MOTS12; + Uint32 MOTS13; + Uint32 MOTS14; + Uint32 MOTS15; + Uint32 MOTS16; + Uint32 MOTS17; + Uint32 MOTS18; + Uint32 MOTS19; + Uint32 MOTS20; + Uint32 MOTS21; + Uint32 MOTS22; + Uint32 MOTS23; + Uint32 MOTS24; + Uint32 MOTS25; + Uint32 MOTS26; + Uint32 MOTS27; + Uint32 MOTS28; + Uint32 MOTS29; + Uint32 MOTS30; + Uint32 MOTS31; +}; + +// +// Mailbox MOTO File +// +struct MOTO_REGS { + Uint32 MOTO0; + Uint32 MOTO1; + Uint32 MOTO2; + Uint32 MOTO3; + Uint32 MOTO4; + Uint32 MOTO5; + Uint32 MOTO6; + Uint32 MOTO7; + Uint32 MOTO8; + Uint32 MOTO9; + Uint32 MOTO10; + Uint32 MOTO11; + Uint32 MOTO12; + Uint32 MOTO13; + Uint32 MOTO14; + Uint32 MOTO15; + Uint32 MOTO16; + Uint32 MOTO17; + Uint32 MOTO18; + Uint32 MOTO19; + Uint32 MOTO20; + Uint32 MOTO21; + Uint32 MOTO22; + Uint32 MOTO23; + Uint32 MOTO24; + Uint32 MOTO25; + Uint32 MOTO26; + Uint32 MOTO27; + Uint32 MOTO28; + Uint32 MOTO29; + Uint32 MOTO30; + Uint32 MOTO31; +}; + +// +// eCAN External References & Function Declarations +// +extern volatile struct ECAN_REGS ECanaRegs; +extern volatile struct ECAN_MBOXES ECanaMboxes; +extern volatile struct LAM_REGS ECanaLAMRegs; +extern volatile struct MOTO_REGS ECanaMOTORegs; +extern volatile struct MOTS_REGS ECanaMOTSRegs; + +extern volatile struct ECAN_REGS ECanbRegs; +extern volatile struct ECAN_MBOXES ECanbMboxes; +extern volatile struct LAM_REGS ECanbLAMRegs; +extern volatile struct MOTO_REGS ECanbMOTORegs; +extern volatile struct MOTS_REGS ECanbMOTSRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAN.H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_ECap.h b/F28335/DSP2833x_ECap.h new file mode 100644 index 0000000..4094945 --- /dev/null +++ b/F28335/DSP2833x_ECap.h @@ -0,0 +1,148 @@ +//########################################################################### +// +// FILE: DSP2833x_ECap.h +// +// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_ECAP_H +#define DSP2833x_ECAP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture control register 1 bit definitions +// +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap + // Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +// +// In V1.1 the STOPVALUE bit field was changed to +// STOP_WRAP. This correlated to a silicon change from +// F2833x Rev 0 to Rev A. +// + +// +// Capture control register 2 bit definitions +// +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +// +// ECAP interrupt enable register bit definitions +// +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +// +// ECAP interrupt flag register bit definitions +// +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time stamp counter + Uint32 CTRPHS; // Counter phase + Uint32 CAP1; // Capture 1 + Uint32 CAP2; // Capture 2 + Uint32 CAP3; // Capture 3 + Uint32 CAP4; // Capture 4 + Uint16 rsvd1[8]; // reserved + union ECCTL1_REG ECCTL1; // Capture Control Reg 1 + union ECCTL2_REG ECCTL2; // Capture Control Reg 2 + union ECEINT_REG ECEINT; // ECAP interrupt enable + union ECFLG_REG ECFLG; // ECAP interrupt flags + union ECFLG_REG ECCLR; // ECAP interrupt clear + union ECEINT_REG ECFRC; // ECAP interrupt force + Uint16 rsvd2[6]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_ECAP_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_EPwm.h b/F28335/DSP2833x_EPwm.h new file mode 100644 index 0000000..5b0d62d --- /dev/null +++ b/F28335/DSP2833x_EPwm.h @@ -0,0 +1,434 @@ +//########################################################################### +// +// FILE: DSP2833x_EPwm.h +// +// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_EPWM_H +#define DSP2833x_EPWM_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Time base control register bit definitions +// +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase load enable + Uint16 PRDLD:1; // 3 Active period load + Uint16 SYNCOSEL:2; // 5:4 Sync output select + Uint16 SWFSYNC:1; // 6 Software force sync pulse + Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale + Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale + Uint16 PHSDIR:1; // 13 Phase Direction + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +// +// Time base status register bit definitions +// +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter direction status + Uint16 SYNCI:1; // 1 External input sync status + Uint16 CTRMAX:1; // 2 Counter max latched status + Uint16 rsvd1:13; // 15:3 reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +// +// Compare control register bit definitions +// +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 0:1 Active compare A + Uint16 LOADBMODE:2; // 3:2 Active compare B + Uint16 SHDWAMODE:1; // 4 Compare A block operating mode + Uint16 rsvd1:1; // 5 reserved + Uint16 SHDWBMODE:1; // 6 Compare B block operating mode + Uint16 rsvd2:1; // 7 reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status + Uint16 rsvd3:6; // 15:10 reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +// +// Action qualifier register bit definitions +// +struct AQCTL_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A up + Uint16 CAD:2; // 7:6 Action Counter = Compare A down + Uint16 CBU:2; // 9:8 Action Counter = Compare B up + Uint16 CBD:2; // 11:10 Action Counter = Compare B down + Uint16 rsvd:4; // 15:12 reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +// +// Action qualifier SW force register bit definitions +// +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked + Uint16 OTSFA:1; // 2 One-time SW Force A output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked + Uint16 OTSFB:1; // 5 One-time SW Force A output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow options + Uint16 rsvd1:8; // 15:8 reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +// +// Action qualifier continuous SW force register bit definitions +// +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +// +// As of version 1.1 +// Changed the MODE bit-field to OUT_MODE +// Added the bit-field IN_MODE +// This corresponds to changes in silicon as of F2833x devices +// Rev A silicon. +// + +// +// Dead-band generator control register bit definitions +// +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 rsvd1:10; // 15:4 reserved +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +// +// Trip zone select register bit definitions +// +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 rsvd1:2; // 7:6 reserved + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 rsvd2:2; // 15:14 reserved +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 rsvd:12; // 15:4 reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +// +// Trip zone control register bit definitions +// +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +// +// Trip zone flag register bit definitions +// +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +// +// Trip zone flag clear register bit definitions +// +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global status + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +// +// Trip zone flag force register bit definitions +// +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int + Uint16 OST:1; // 2 Trip Zones One Shot Int + Uint16 rsvd2:13; // 15:3 reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +// +// Event trigger select register bit definitions +// +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCASEL:3; // 10:8 Start of conversion A Select + Uint16 SOCAEN:1; // 11 Start of conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select + Uint16 SOCBEN:1; // 15 Start of conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +// +// Event trigger pre-scale register bit definitions +// +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 rsvd1:4; // 7:4 reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +// +// Event trigger Flag register bit definitions +// +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +// +// Event trigger Clear register bit definitions +// +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +// +// Event trigger Force register bit definitions +// +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +// +// PWM chopper control register bit definitions +// +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits + Uint16 CTLMODE:1; // 2 Control mode Select Bit + Uint16 HRLOAD:1; // 3 Shadow mode Select Bit + Uint16 rsvd1:12; // 15:4 reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct TBPHS_HRPWM_REG { //bits description + Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits) + Uint16 TBPHS; //31:16 Phase offset register +}; + +union TBPHS_HRPWM_GROUP { + Uint32 all; + struct TBPHS_HRPWM_REG half; +}; + +struct CMPA_HRPWM_REG { // bits description + Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) + Uint16 CMPA; // 31:16 Compare A reg +}; + +union CMPA_HRPWM_GROUP { + Uint32 all; + struct CMPA_HRPWM_REG half; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // + union TBSTS_REG TBSTS; // + union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR + Uint16 TBCTR; // Counter + Uint16 TBPRD; // Period register set + Uint16 rsvd1; // + union CMPCTL_REG CMPCTL; // Compare control + union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR + Uint16 CMPB; // Compare B reg + union AQCTL_REG AQCTLA; // Action qual output A + union AQCTL_REG AQCTLB; // Action qual output B + union AQSFRC_REG AQSFRC; // Action qual SW force + union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force + union DBCTL_REG DBCTL; // Dead-band control + Uint16 DBRED; // Dead-band rising edge delay + Uint16 DBFED; // Dead-band falling edge delay + union TZSEL_REG TZSEL; // Trip zone select + Uint16 rsvd2; + union TZCTL_REG TZCTL; // Trip zone control + union TZEINT_REG TZEINT; // Trip zone interrupt enable + union TZFLG_REG TZFLG; // Trip zone interrupt flags + union TZCLR_REG TZCLR; // Trip zone clear + union TZFRC_REG TZFRC; // Trip zone force interrupt + union ETSEL_REG ETSEL; // Event trigger selection + union ETPS_REG ETPS; // Event trigger pre-scaler + union ETFLG_REG ETFLG; // Event trigger flags + union ETCLR_REG ETCLR; // Event trigger clear + union ETFRC_REG ETFRC; // Event trigger force + union PCCTL_REG PCCTL; // PWM chopper control + Uint16 rsvd3; // + union HRCNFG_REG HRCNFG; // HRPWM Config Reg +}; + + +// +// External References & Function Declarations +// +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EPWM_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_EPwm_defines.h b/F28335/DSP2833x_EPwm_defines.h new file mode 100644 index 0000000..2e8d602 --- /dev/null +++ b/F28335/DSP2833x_EPwm_defines.h @@ -0,0 +1,212 @@ +//########################################################################### +// +// FILE: DSP2833x_EPwm_defines.h +// +// TITLE: #defines used in ePWM examples examples +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_EPWM_DEFINES_H +#define DSP2833x_EPWM_DEFINES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// TBCTL (Time-Base Control) +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// ETSEL (Event Trigger Select) +// +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// +// HRCNFG +// +#define HR_Disable 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_EPWM_DEFINES_H + +// +// End of file +// + diff --git a/F28335/DSP2833x_EQep.h b/F28335/DSP2833x_EQep.h new file mode 100644 index 0000000..08d24bd --- /dev/null +++ b/F28335/DSP2833x_EQep.h @@ -0,0 +1,239 @@ +//########################################################################### +// +// FILE: DSP2833x_EQep.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_EQEP_H +#define DSP2833x_EQEP_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Capture decoder control register bit definitions +// +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter + Uint16 XCR:1; // 11 External clock rate + Uint16 SPSEL:1; // 12 Sync output pin select + Uint16 SOEN:1; // 13 Enable position compare sync + Uint16 QSRC:2; // 15:14 Position counter source +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +// +// QEP control register bit definitions +// +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature position counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Position counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +// +// Quadrature capture control register bit definitions +// +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position pre-scale + Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale + Uint16 rsvd1:8; // 14:7 reserved + Uint16 CEN:1; // 15 Enable QEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +// +// Position compare control register bit definitions +// +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +// +// QEP interrupt control register bit definitions +// +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 QPE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +// +// QEP interrupt status register bit definitions +// +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +// +// QEP interrupt force register bit definitions +// +struct QFRC_BITS { // bits description + Uint16 reserved:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error + Uint16 PHE:1; // 2 Quadrature phase error + Uint16 QDC:1; // 3 Quadrature dir change + Uint16 WTO:1; // 4 Watchdog timeout + Uint16 PCU:1; // 5 Position counter underflow + Uint16 PCO:1; // 6 Position counter overflow + Uint16 PCR:1; // 7 Position compare ready + Uint16 PCM:1; // 8 Position compare match + Uint16 SEL:1; // 9 Strobe event latch + Uint16 IEL:1; // 10 Event latch + Uint16 UTO:1; // 11 Unit timeout + Uint16 rsvd2:4; // 15:12 reserved +}; + + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +// +// V1.1 Added UPEVNT (bit 7) This reflects changes +// made as of F2833x Rev A devices +// + +// +// QEP status register bit definitions +// +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error + Uint16 FIMF:1; // 1 First index marker + Uint16 CDEF:1; // 2 Capture direction error + Uint16 COEF:1; // 3 Capture overflow error + Uint16 QDLF:1; // 4 QEP direction latch + Uint16 QDF:1; // 5 Quadrature direction + Uint16 FIDF:1; // 6 Direction on first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position counter + Uint32 QPOSINIT; // Position counter init + Uint32 QPOSMAX; // Maximum position count + Uint32 QPOSCMP; // Position compare + Uint32 QPOSILAT; // Index position latch + Uint32 QPOSSLAT; // Strobe position latch + Uint32 QPOSLAT; // Position latch + Uint32 QUTMR; // Unit timer + Uint32 QUPRD; // Unit period + Uint16 QWDTMR; // QEP watchdog timer + Uint16 QWDPRD; // QEP watchdog period + union QDECCTL_REG QDECCTL; // Quadrature decoder control + union QEPCTL_REG QEPCTL; // QEP control + union QCAPCTL_REG QCAPCTL; // Quadrature capture control + union QPOSCTL_REG QPOSCTL; // Position compare control + union QEINT_REG QEINT; // QEP interrupt control + union QFLG_REG QFLG; // QEP interrupt flag + union QFLG_REG QCLR; // QEP interrupt clear + union QFRC_REG QFRC; // QEP interrupt force + union QEPSTS_REG QEPSTS; // QEP status + Uint16 QCTMR; // QEP capture timer + Uint16 QCPRD; // QEP capture period + Uint16 QCTMRLAT; // QEP capture latch + Uint16 QCPRDLAT; // QEP capture period latch + Uint16 rsvd1[30]; // reserved +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EQEP_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_Examples.h b/F28335/DSP2833x_Examples.h new file mode 100644 index 0000000..bee9ff2 --- /dev/null +++ b/F28335/DSP2833x_Examples.h @@ -0,0 +1,139 @@ +//########################################################################### +// +// FILE: DSP2833x_Examples.h +// +// TITLE: DSP2833x Device Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_EXAMPLES_H +#define DSP2833x_EXAMPLES_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. +// +//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT +//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT +#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT +//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT + +#define DSP28_PLLCR 10 +//#define DSP28_PLLCR 9 +//#define DSP28_PLLCR 8 +//#define DSP28_PLLCR 7 +//#define DSP28_PLLCR 6 +//#define DSP28_PLLCR 5 +//#define DSP28_PLLCR 4 +//#define DSP28_PLLCR 3 +//#define DSP28_PLLCR 2 +//#define DSP28_PLLCR 1 +//#define DSP28_PLLCR 0 // PLL is bypassed in this mode + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example 1:150 MHz devices: +// CLKIN is a 30MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 150Mhz CPU clock (SYSCLKOUT = 150MHz). +// +// In this case, the CPU_RATE will be 6.667L +// Uncomment the line: #define CPU_RATE 6.667L +// +// Example 2: 100 MHz devices: +// CLKIN is a 20MHz crystal. +// +// In step 1 the user specified PLLCR = 0xA for a +// 100Mhz CPU clock (SYSCLKOUT = 100MHz). +// +// In this case, the CPU_RATE will be 10.000L +// Uncomment the line: #define CPU_RATE 10.000L +// +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +// +// Target device (in DSP2833x_Device.h) determines CPU frequency +// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz +// (for 28332 and 28333). User does not have to change anything here. +// +#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only + #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) + #define CPU_FRQ_150MHZ 0 +#else + #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 + #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT +#endif + +// +// Include Example Header Files +// + +// +// Prototypes for global functions within the .c files. +// +#include "F28335/DSP2833x_GlobalPrototypes.h" +#include "F28335/DSP2833x_EPwm_defines.h" // Macros used for PWM examples. +#include "F28335/DSP2833x_Dma_defines.h" // Macros used for DMA examples. +#include "F28335/DSP2833x_I2c_defines.h" // Macros used for I2C examples. + +#define PARTNO_28335 0xEF +#define PARTNO_28334 0xEE +#define PARTNO_28333 0xEA +#define PARTNO_28332 0xED +#define PARTNO_28235 0xE8 +#define PARTNO_28234 0xE7 +#define PARTNO_28232 0xE6 + +// +// Include files not used with DSP/BIOS +// +#ifndef DSP28_BIOS +#include "F28335/DSP2833x_DefaultIsr.h" +#endif + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \ + (long double)CPU_RATE) - 9.0L) / 5.0L) + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_EXAMPLES_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_GlobalPrototypes.h b/F28335/DSP2833x_GlobalPrototypes.h new file mode 100644 index 0000000..325a066 --- /dev/null +++ b/F28335/DSP2833x_GlobalPrototypes.h @@ -0,0 +1,260 @@ +//########################################################################### +// +// FILE: DSP2833x_GlobalPrototypes.h +// +// TITLE: Global prototypes for DSP2833x Examples +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_GLOBALPROTOTYPES_H +#define DSP2833x_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// shared global function prototypes +// +extern void InitAdc(void); +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +extern void InitPeripherals(void); +#if DSP28_ECANA +extern void InitECan(void); +extern void InitECana(void); +extern void InitECanGpio(void); +extern void InitECanaGpio(void); +#endif // endif DSP28_ECANA +#if DSP28_ECANB +extern void InitECanb(void); +extern void InitECanbGpio(void); +#endif // endif DSP28_ECANB +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(void); +extern void InitECap2Gpio(void); +#if DSP28_ECAP3 +extern void InitECap3Gpio(void); +#endif // endif DSP28_ECAP3 +#if DSP28_ECAP4 +extern void InitECap4Gpio(void); +#endif // endif DSP28_ECAP4 +#if DSP28_ECAP5 +extern void InitECap5Gpio(void); +#endif // endif DSP28_ECAP5 +#if DSP28_ECAP6 +extern void InitECap6Gpio(void); +#endif // endif DSP28_ECAP6 +extern void InitEPwm(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +#if DSP28_EPWM4 +extern void InitEPwm4Gpio(void); +#endif // endif DSP28_EPWM4 +#if DSP28_EPWM5 +extern void InitEPwm5Gpio(void); +#endif // endif DSP28_EPWM5 +#if DSP28_EPWM6 +extern void InitEPwm6Gpio(void); +#endif // endif DSP28_EPWM6 +#if DSP28_EQEP1 +extern void InitEQep(void); +extern void InitEQepGpio(void); +extern void InitEQep1Gpio(void); +#endif // if DSP28_EQEP1 +#if DSP28_EQEP2 +extern void InitEQep2Gpio(void); +#endif // endif DSP28_EQEP2 +extern void InitGpio(void); +extern void InitI2CGpio(void); + +extern void InitMcbsp(void); +extern void InitMcbspa(void); +extern void delay_loop(void); +extern void InitMcbspaGpio(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +#if DSP28_MCBSPB +extern void InitMcbspb(void); +extern void InitMcbspbGpio(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +#endif // endif DSP28_MCBSPB + +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); + +extern void InitSci(void); +extern void InitSciGpio(void); +extern void InitSciaGpio(void); +#if DSP28_SCIB +extern void InitScibGpio(void); +#endif // endif DSP28_SCIB +#if DSP28_SCIC +extern void InitScicGpio(void); +#endif +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitTzGpio(void); +extern void InitXIntrupt(void); +extern void XintfInit(void); +extern void InitXintf16Gpio(); +extern void InitXintf32Gpio(); +extern void InitPll(Uint16 pllcr, Uint16 clkindiv); +extern void InitPeripheralClocks(void); +extern void EnableInterrupts(void); +extern void DSP28x_usDelay(Uint32 Count); +extern void ADC_cal (void); +#define KickDog ServiceDog // For compatiblity with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); +extern Uint16 CsmUnlock(void); + +// +// DSP28_DBGIER.asm +// +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); + +void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in either Flash or XINTF to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsLoadSize; + +extern Uint16 XintffuncsLoadStart; +extern Uint16 XintffuncsLoadEnd; +extern Uint16 XintffuncsRunStart; +extern Uint16 XintffuncsLoadSize; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of DSP2833x_GLOBALPROTOTYPES_H + +// +// End of file +// + diff --git a/F28335/DSP2833x_Gpio.h b/F28335/DSP2833x_Gpio.h new file mode 100644 index 0000000..c1f3e8c --- /dev/null +++ b/F28335/DSP2833x_Gpio.h @@ -0,0 +1,462 @@ +//########################################################################### +// +// FILE: DSP2833x_Gpio.h +// +// TITLE: DSP2833x General Purpose I/O Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_GPIO_H +#define DSP2833x_GPIO_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// GPIO A control register bit definitions +// +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 Qual period +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +// +// GPIO B control register bit definitions +// +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qual period + Uint16 QUALPRD1:8; // 15:8 Qual period + Uint16 QUALPRD2:8; // 23:16 Qual period + Uint16 QUALPRD3:8; // 31:24 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +// +// GPIO A Qual/MUX select register bit definitions +// +struct GPA1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 GPIO0 + Uint16 GPIO1:2; // 3:2 GPIO1 + Uint16 GPIO2:2; // 5:4 GPIO2 + Uint16 GPIO3:2; // 7:6 GPIO3 + Uint16 GPIO4:2; // 9:8 GPIO4 + Uint16 GPIO5:2; // 11:10 GPIO5 + Uint16 GPIO6:2; // 13:12 GPIO6 + Uint16 GPIO7:2; // 15:14 GPIO7 + Uint16 GPIO8:2; // 17:16 GPIO8 + Uint16 GPIO9:2; // 19:18 GPIO9 + Uint16 GPIO10:2; // 21:20 GPIO10 + Uint16 GPIO11:2; // 23:22 GPIO11 + Uint16 GPIO12:2; // 25:24 GPIO12 + Uint16 GPIO13:2; // 27:26 GPIO13 + Uint16 GPIO14:2; // 29:28 GPIO14 + Uint16 GPIO15:2; // 31:30 GPIO15 +}; + +struct GPA2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 GPIO16 + Uint16 GPIO17:2; // 3:2 GPIO17 + Uint16 GPIO18:2; // 5:4 GPIO18 + Uint16 GPIO19:2; // 7:6 GPIO19 + Uint16 GPIO20:2; // 9:8 GPIO20 + Uint16 GPIO21:2; // 11:10 GPIO21 + Uint16 GPIO22:2; // 13:12 GPIO22 + Uint16 GPIO23:2; // 15:14 GPIO23 + Uint16 GPIO24:2; // 17:16 GPIO24 + Uint16 GPIO25:2; // 19:18 GPIO25 + Uint16 GPIO26:2; // 21:20 GPIO26 + Uint16 GPIO27:2; // 23:22 GPIO27 + Uint16 GPIO28:2; // 25:24 GPIO28 + Uint16 GPIO29:2; // 27:26 GPIO29 + Uint16 GPIO30:2; // 29:28 GPIO30 + Uint16 GPIO31:2; // 31:30 GPIO31 +}; + +struct GPB1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 GPIO32 + Uint16 GPIO33:2; // 3:2 GPIO33 + Uint16 GPIO34:2; // 5:4 GPIO34 + Uint16 GPIO35:2; // 7:6 GPIO35 + Uint16 GPIO36:2; // 9:8 GPIO36 + Uint16 GPIO37:2; // 11:10 GPIO37 + Uint16 GPIO38:2; // 13:12 GPIO38 + Uint16 GPIO39:2; // 15:14 GPIO39 + Uint16 GPIO40:2; // 17:16 GPIO40 + Uint16 GPIO41:2; // 19:16 GPIO41 + Uint16 GPIO42:2; // 21:20 GPIO42 + Uint16 GPIO43:2; // 23:22 GPIO43 + Uint16 GPIO44:2; // 25:24 GPIO44 + Uint16 GPIO45:2; // 27:26 GPIO45 + Uint16 GPIO46:2; // 29:28 GPIO46 + Uint16 GPIO47:2; // 31:30 GPIO47 +}; + +struct GPB2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 GPIO48 + Uint16 GPIO49:2; // 3:2 GPIO49 + Uint16 GPIO50:2; // 5:4 GPIO50 + Uint16 GPIO51:2; // 7:6 GPIO51 + Uint16 GPIO52:2; // 9:8 GPIO52 + Uint16 GPIO53:2; // 11:10 GPIO53 + Uint16 GPIO54:2; // 13:12 GPIO54 + Uint16 GPIO55:2; // 15:14 GPIO55 + Uint16 GPIO56:2; // 17:16 GPIO56 + Uint16 GPIO57:2; // 19:18 GPIO57 + Uint16 GPIO58:2; // 21:20 GPIO58 + Uint16 GPIO59:2; // 23:22 GPIO59 + Uint16 GPIO60:2; // 25:24 GPIO60 + Uint16 GPIO61:2; // 27:26 GPIO61 + Uint16 GPIO62:2; // 29:28 GPIO62 + Uint16 GPIO63:2; // 31:30 GPIO63 +}; + +struct GPC1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 GPIO64 + Uint16 GPIO65:2; // 3:2 GPIO65 + Uint16 GPIO66:2; // 5:4 GPIO66 + Uint16 GPIO67:2; // 7:6 GPIO67 + Uint16 GPIO68:2; // 9:8 GPIO68 + Uint16 GPIO69:2; // 11:10 GPIO69 + Uint16 GPIO70:2; // 13:12 GPIO70 + Uint16 GPIO71:2; // 15:14 GPIO71 + Uint16 GPIO72:2; // 17:16 GPIO72 + Uint16 GPIO73:2; // 19:18 GPIO73 + Uint16 GPIO74:2; // 21:20 GPIO74 + Uint16 GPIO75:2; // 23:22 GPIO75 + Uint16 GPIO76:2; // 25:24 GPIO76 + Uint16 GPIO77:2; // 27:26 GPIO77 + Uint16 GPIO78:2; // 29:28 GPIO78 + Uint16 GPIO79:2; // 31:30 GPIO79 +}; + +struct GPC2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 GPIO80 + Uint16 GPIO81:2; // 3:2 GPIO81 + Uint16 GPIO82:2; // 5:4 GPIO82 + Uint16 GPIO83:2; // 7:6 GPIO83 + Uint16 GPIO84:2; // 9:8 GPIO84 + Uint16 GPIO85:2; // 11:10 GPIO85 + Uint16 GPIO86:2; // 13:12 GPIO86 + Uint16 GPIO87:2; // 15:14 GPIO87 + Uint16 rsvd:16; // 31:16 reserved +}; + +union GPA1_REG { + Uint32 all; + struct GPA1_BITS bit; +}; + +union GPA2_REG { + Uint32 all; + struct GPA2_BITS bit; +}; + +union GPB1_REG { + Uint32 all; + struct GPB1_BITS bit; +}; + +union GPB2_REG { + Uint32 all; + struct GPB2_BITS bit; +}; + +union GPC1_REG { + Uint32 all; + struct GPC1_BITS bit; +}; + +union GPC2_REG { + Uint32 all; + struct GPC2_BITS bit; +}; + +// +// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions +// +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 + Uint16 GPIO1:1; // 1 GPIO1 + Uint16 GPIO2:1; // 2 GPIO2 + Uint16 GPIO3:1; // 3 GPIO3 + Uint16 GPIO4:1; // 4 GPIO4 + Uint16 GPIO5:1; // 5 GPIO5 + Uint16 GPIO6:1; // 6 GPIO6 + Uint16 GPIO7:1; // 7 GPIO7 + Uint16 GPIO8:1; // 8 GPIO8 + Uint16 GPIO9:1; // 9 GPIO9 + Uint16 GPIO10:1; // 10 GPIO10 + Uint16 GPIO11:1; // 11 GPIO11 + Uint16 GPIO12:1; // 12 GPIO12 + Uint16 GPIO13:1; // 13 GPIO13 + Uint16 GPIO14:1; // 14 GPIO14 + Uint16 GPIO15:1; // 15 GPIO15 + Uint16 GPIO16:1; // 16 GPIO16 + Uint16 GPIO17:1; // 17 GPIO17 + Uint16 GPIO18:1; // 18 GPIO18 + Uint16 GPIO19:1; // 19 GPIO19 + Uint16 GPIO20:1; // 20 GPIO20 + Uint16 GPIO21:1; // 21 GPIO21 + Uint16 GPIO22:1; // 22 GPIO22 + Uint16 GPIO23:1; // 23 GPIO23 + Uint16 GPIO24:1; // 24 GPIO24 + Uint16 GPIO25:1; // 25 GPIO25 + Uint16 GPIO26:1; // 26 GPIO26 + Uint16 GPIO27:1; // 27 GPIO27 + Uint16 GPIO28:1; // 28 GPIO28 + Uint16 GPIO29:1; // 29 GPIO29 + Uint16 GPIO30:1; // 30 GPIO30 + Uint16 GPIO31:1; // 31 GPIO31 +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 + Uint16 GPIO33:1; // 1 GPIO33 + Uint16 GPIO34:1; // 2 GPIO34 + Uint16 GPIO35:1; // 3 GPIO35 + Uint16 GPIO36:1; // 4 GPIO36 + Uint16 GPIO37:1; // 5 GPIO37 + Uint16 GPIO38:1; // 6 GPIO38 + Uint16 GPIO39:1; // 7 GPIO39 + Uint16 GPIO40:1; // 8 GPIO40 + Uint16 GPIO41:1; // 9 GPIO41 + Uint16 GPIO42:1; // 10 GPIO42 + Uint16 GPIO43:1; // 11 GPIO43 + Uint16 GPIO44:1; // 12 GPIO44 + Uint16 GPIO45:1; // 13 GPIO45 + Uint16 GPIO46:1; // 14 GPIO46 + Uint16 GPIO47:1; // 15 GPIO47 + Uint16 GPIO48:1; // 16 GPIO48 + Uint16 GPIO49:1; // 17 GPIO49 + Uint16 GPIO50:1; // 18 GPIO50 + Uint16 GPIO51:1; // 19 GPIO51 + Uint16 GPIO52:1; // 20 GPIO52 + Uint16 GPIO53:1; // 21 GPIO53 + Uint16 GPIO54:1; // 22 GPIO54 + Uint16 GPIO55:1; // 23 GPIO55 + Uint16 GPIO56:1; // 24 GPIO56 + Uint16 GPIO57:1; // 25 GPIO57 + Uint16 GPIO58:1; // 26 GPIO58 + Uint16 GPIO59:1; // 27 GPIO59 + Uint16 GPIO60:1; // 28 GPIO60 + Uint16 GPIO61:1; // 29 GPIO61 + Uint16 GPIO62:1; // 30 GPIO62 + Uint16 GPIO63:1; // 31 GPIO63 +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 GPIO64 + Uint16 GPIO65:1; // 1 GPIO65 + Uint16 GPIO66:1; // 2 GPIO66 + Uint16 GPIO67:1; // 3 GPIO67 + Uint16 GPIO68:1; // 4 GPIO68 + Uint16 GPIO69:1; // 5 GPIO69 + Uint16 GPIO70:1; // 6 GPIO70 + Uint16 GPIO71:1; // 7 GPIO71 + Uint16 GPIO72:1; // 8 GPIO72 + Uint16 GPIO73:1; // 9 GPIO73 + Uint16 GPIO74:1; // 10 GPIO74 + Uint16 GPIO75:1; // 11 GPIO75 + Uint16 GPIO76:1; // 12 GPIO76 + Uint16 GPIO77:1; // 13 GPIO77 + Uint16 GPIO78:1; // 14 GPIO78 + Uint16 GPIO79:1; // 15 GPIO79 + Uint16 GPIO80:1; // 16 GPIO80 + Uint16 GPIO81:1; // 17 GPIO81 + Uint16 GPIO82:1; // 18 GPIO82 + Uint16 GPIO83:1; // 19 GPIO83 + Uint16 GPIO84:1; // 20 GPIO84 + Uint16 GPIO85:1; // 21 GPIO85 + Uint16 GPIO86:1; // 22 GPIO86 + Uint16 GPIO87:1; // 23 GPIO87 + Uint16 rsvd1:8; // 31:24 reserved +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +// +// GPIO Xint1/XINT2/XNMI select register bit definitions +// +struct GPIOXINT_BITS { // bits description + Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source + Uint16 rsvd1:11; // 15:5 reserved +}; + +union GPIOXINT_REG { + Uint16 all; + struct GPIOXINT_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) + + // + // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAQSEL1; + + // + // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAQSEL2; + + // + // GPIO A Mux 1 Register (GPIO0 to 15) + // + union GPA1_REG GPAMUX1; + + // + // GPIO A Mux 2 Register (GPIO16 to 31) + // + union GPA2_REG GPAMUX2; + + union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + + // + // GPIO A Pull Up Disable Register (GPIO0 to 31) + // + union GPADAT_REG GPAPUD; + + Uint32 rsvd1; + union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) + + // + // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + // + union GPB1_REG GPBQSEL1; + + // + // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + // + union GPB2_REG GPBQSEL2; + + union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + + // + // GPIO B Pull Up Disable Register (GPIO32 to 63) + // + union GPBDAT_REG GPBPUD; + + Uint16 rsvd2[8]; + union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + + // + // GPIO C Pull Up Disable Register (GPIO64 to 95) + // + union GPCDAT_REG GPCPUD; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) + + // + // GPIO Data Set Register (GPIO0 to 31) + // + union GPADAT_REG GPASET; + + // + // GPIO Data Clear Register (GPIO0 to 31) + // + union GPADAT_REG GPACLEAR; + + // + // GPIO Data Toggle Register (GPIO0 to 31) + // + union GPADAT_REG GPATOGGLE; + + union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) + + // + // GPIO Data Set Register (GPIO32 to 63) + // + union GPBDAT_REG GPBSET; + + // + // GPIO Data Clear Register (GPIO32 to 63) + // + union GPBDAT_REG GPBCLEAR; + + // + // GPIO Data Toggle Register (GPIO32 to 63) + // + union GPBDAT_REG GPBTOGGLE; + + union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95) + union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95) + + // + // GPIO Data Clear Register (GPIO64 to 95) + // + union GPCDAT_REG GPCCLEAR; + + // + // GPIO Data Toggle Register (GPIO64 to 95) + // + union GPCDAT_REG GPCTOGGLE; + Uint16 rsvd1[8]; +}; + +struct GPIO_INT_REGS { + union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection + union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection + union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection + union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection + union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection + union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection + union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection + union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection + union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select +}; + +// +// GPI/O External References & Function Declarations +// +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +extern volatile struct GPIO_INT_REGS GpioIntRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_GPIO_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_I2c.h b/F28335/DSP2833x_I2c.h new file mode 100644 index 0000000..ebf6b3e --- /dev/null +++ b/F28335/DSP2833x_I2c.h @@ -0,0 +1,202 @@ +//########################################################################### +// +// FILE: DSP2833x_I2c.h +// +// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module +// Register Bit Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_I2C_H +#define DSP2833x_I2C_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// I2C interrupt vector register bit definitions +// +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code + Uint16 rsvd1:13; // 15:3 reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +// +// I2C interrupt mask register bit definitions +// +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 AAS:1; // 6 Address as slave + Uint16 rsvd:9; // 15:7 reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +// +// I2C status register bit definitions +// +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration lost interrupt + Uint16 NACK:1; // 1 No ack interrupt + Uint16 ARDY:1; // 2 Register access ready interrupt + Uint16 RRDY:1; // 3 Recieve data ready interrupt + Uint16 XRDY:1; // 4 Transmit data ready interrupt + Uint16 SCD:1; // 5 Stop condition detection + Uint16 rsvd1:2; // 7:6 reserved + Uint16 AD0:1; // 8 Address Zero + Uint16 AAS:1; // 9 Address as slave + Uint16 XSMT:1; // 10 XMIT shift empty + Uint16 RSFULL:1; // 11 Recieve shift full + Uint16 BB:1; // 12 Bus busy + Uint16 NACKSNT:1; // 13 A no ack sent + Uint16 SDIR:1; // 14 Slave direction + Uint16 rsvd2:1; // 15 reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +// +// I2C mode control register bit definitions +// +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count + Uint16 FDF:1; // 3 Free data format + Uint16 STB:1; // 4 Start byte + Uint16 IRS:1; // 5 I2C Reset not + Uint16 DLB:1; // 6 Digital loopback + Uint16 RM:1; // 7 Repeat mode + Uint16 XA:1; // 8 Expand address + Uint16 TRX:1; // 9 Transmitter/reciever + Uint16 MST:1; // 10 Master/slave + Uint16 STP:1; // 11 Stop condition + Uint16 rsvd1:1; // 12 reserved + Uint16 STT:1; // 13 Start condition + Uint16 FREE:1; // 14 Emulation mode + Uint16 NACKMOD:1; // 15 No Ack mode +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +// +// I2C extended mode control register bit definitions +// +struct I2CEMDR_BITS { // bits description + Uint16 BCM:1; // 0 Backward compatibility mode + Uint16 rsvd:15; // 15 reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +// +// I2C pre-scaler register bit definitions +// +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 pre-scaler + Uint16 rsvd1:8; // 15:8 reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +// +// TX FIFO control register bit definitions +// +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 FIFO interrupt level + Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 TXFFINTCLR:1; // 6 FIFO clear + Uint16 TXFFINT:1; // 7 FIFO interrupt flag + Uint16 TXFFST:5; // 12:8 FIFO level status + Uint16 TXFFRST:1; // 13 FIFO reset + Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs + Uint16 rsvd1:1; // 15 reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +// +// RX FIFO control register bit definitions +// +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 FIFO interrupt level + Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable + Uint16 RXFFINTCLR:1; // 6 FIFO clear + Uint16 RXFFINT:1; // 7 FIFO interrupt flag + Uint16 RXFFST:5; // 12:8 FIFO level + Uint16 RXFFRST:1; // 13 FIFO reset + Uint16 rsvd1:2; // 15:14 reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + Uint16 I2COAR; // Own address register + union I2CIER_REG I2CIER; // Interrupt enable + union I2CSTR_REG I2CSTR; // Interrupt status + Uint16 I2CCLKL; // Clock divider low + Uint16 I2CCLKH; // Clock divider high + Uint16 I2CCNT; // Data count + Uint16 I2CDRR; // Data recieve + Uint16 I2CSAR; // Slave address + Uint16 I2CDXR; // Data transmit + union I2CMDR_REG I2CMDR; // Mode + union I2CISRC_REG I2CISRC; // Interrupt source + union I2CEMDR_REG I2CEMDR; // Extended Mode + union I2CPSC_REG I2CPSC; // Pre-scaler + Uint16 rsvd2[19]; // reserved + union I2CFFTX_REG I2CFFTX; // Transmit FIFO + union I2CFFRX_REG I2CFFRX; // Recieve FIFO +}; + +// +// External References & Function Declarations +// +extern volatile struct I2C_REGS I2caRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_I2C_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_I2c_defines.h b/F28335/DSP2833x_I2c_defines.h new file mode 100644 index 0000000..9ea1efc --- /dev/null +++ b/F28335/DSP2833x_I2c_defines.h @@ -0,0 +1,148 @@ +//########################################################################### +// +// FILE: DSP2833x_I2cExample.h +// +// TITLE: 2833x I2C Example Code Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_I2C_DEFINES_H +#define DSP2833x_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + +// +// Structures +// + +// +// I2C Message Structure +// +struct I2CMSG +{ + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a restart + // as a master receiver with a stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) + + // + // EEPROM address of data associated with msg (high byte) + // + Uint16 MemoryHighAddr; + + // + // EEPROM address of data associated with msg (low byte) + // + Uint16 MemoryLowAddr; + + // + // Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to + // the FIFO's + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; +}; + + +#endif // end of DSP2833x_I2C_DEFINES_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_Mcbsp.h b/F28335/DSP2833x_Mcbsp.h new file mode 100644 index 0000000..7ddf813 --- /dev/null +++ b/F28335/DSP2833x_Mcbsp.h @@ -0,0 +1,776 @@ +//########################################################################### +// +// FILE: DSP2833x_Mcbsp.h +// +// TITLE: DSP2833x Device McBSP Register Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_MCBSP_H +#define DSP2833x_MCBSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// McBSP Individual Register Bit Definitions +// + +// +// McBSP DRR2 register bit definitions +// +struct DRR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +// +// McBSP DRR1 register bit definitions +// +struct DRR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +// +// McBSP DXR2 register bit definitions +// +struct DXR2_BITS { // bit description + Uint16 HWLB:8; // 16:23 High word low byte + Uint16 HWHB:8; // 24:31 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +// +// McBSP DXR1 register bit definitions +// +struct DXR1_BITS { // bit description + Uint16 LWLB:8; // 16:23 Low word low byte + Uint16 LWHB:8; // 24:31 low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +// +// SPCR2 control register bit definitions +// +struct SPCR2_BITS { // bit description + Uint16 XRST:1; // 0 transmit reset + Uint16 XRDY:1; // 1 transmit ready + Uint16 XEMPTY:1; // 2 Transmit empty + Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag + Uint16 XINTM:2; // 5:4 Transmit interrupt types + Uint16 GRST:1; // 6 CLKG reset + Uint16 FRST:1; // 7 Frame sync reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd:6; // 15:10 reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +// +// SPCR1 control register bit definitions +// +struct SPCR1_BITS { // bit description + Uint16 RRST:1; // 0 Receive reset + Uint16 RRDY:1; // 1 Receive ready + Uint16 RFULL:1; // 2 Receive full + Uint16 RSYNCERR:1; // 7 Receive syn error + Uint16 RINTM:2; // 5:4 Receive interrupt types + Uint16 rsvd1:1; // 6 reserved + Uint16 DXENA:1; // 7 DX hi-z enable + Uint16 rsvd2:3; // 10:8 reserved + Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit + Uint16 RJUST:2; // 13:14 Right justified + Uint16 DLB:1; // 15 Digital loop back +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +// +// RCR2 control register bit definitions +// +struct RCR2_BITS { // bit description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length + Uint16 RFRLEN2:7; // 14:8 Receive Frame sync + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +// +// RCR1 control register bit definitions +// +struct RCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length + Uint16 RFRLEN1:7; // 14:8 Receive frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +// +// XCR2 control register bit definitions +// +struct XCR2_BITS { // bit description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length + Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +// +// XCR1 control register bit definitions +// +struct XCR1_BITS { // bit description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length + Uint16 XFRLEN1:7; // 14:8 Transmit frame length + Uint16 rsvd2:1; // 15 reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +// +// SRGR2 Sample rate generator control register bit definitions +// +struct SRGR2_BITS { // bit description + Uint16 FPER:12; // 11:0 Frame period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd:1; // 14 reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +// +// SRGR1 control register bit definitions +// +struct SRGR1_BITS { // bit description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +// +// MCR2 Multichannel control register bit definitions +// +struct MCR2_BITS { // bit description + Uint16 XMCM:2; // 1:0 Transmit multichannel mode + Uint16 XCBLK:3; // 2:4 Transmit current block + Uint16 XPABLK:2; // 5:6 Transmit partition A Block + Uint16 XPBBLK:2; // 7:8 Transmit partition B Block + Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode + Uint16 rsvd:6; // 15:10 reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +// +// MCR1 Multichannel control register bit definitions +// +struct MCR1_BITS { // bit description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd:1; // 1 reserved + Uint16 RCBLK:3; // 4:2 Receive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 7:8 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd1:6; // 15:10 reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +// +// RCERA control register bit definitions +// +struct RCERA_BITS { // bit description + Uint16 RCEA0:1; // 0 Receive Channel enable bit + Uint16 RCEA1:1; // 1 Receive Channel enable bit + Uint16 RCEA2:1; // 2 Receive Channel enable bit + Uint16 RCEA3:1; // 3 Receive Channel enable bit + Uint16 RCEA4:1; // 4 Receive Channel enable bit + Uint16 RCEA5:1; // 5 Receive Channel enable bit + Uint16 RCEA6:1; // 6 Receive Channel enable bit + Uint16 RCEA7:1; // 7 Receive Channel enable bit + Uint16 RCEA8:1; // 8 Receive Channel enable bit + Uint16 RCEA9:1; // 9 Receive Channel enable bit + Uint16 RCEA10:1; // 10 Receive Channel enable bit + Uint16 RCEA11:1; // 11 Receive Channel enable bit + Uint16 RCEA12:1; // 12 Receive Channel enable bit + Uint16 RCEA13:1; // 13 Receive Channel enable bit + Uint16 RCEA14:1; // 14 Receive Channel enable bit + Uint16 RCEA15:1; // 15 Receive Channel enable bit +}; + +union RCERA_REG { + Uint16 all; + struct RCERA_BITS bit; +}; + +// +// RCERB control register bit definitions +// +struct RCERB_BITS { // bit description + Uint16 RCEB0:1; // 0 Receive Channel enable bit + Uint16 RCEB1:1; // 1 Receive Channel enable bit + Uint16 RCEB2:1; // 2 Receive Channel enable bit + Uint16 RCEB3:1; // 3 Receive Channel enable bit + Uint16 RCEB4:1; // 4 Receive Channel enable bit + Uint16 RCEB5:1; // 5 Receive Channel enable bit + Uint16 RCEB6:1; // 6 Receive Channel enable bit + Uint16 RCEB7:1; // 7 Receive Channel enable bit + Uint16 RCEB8:1; // 8 Receive Channel enable bit + Uint16 RCEB9:1; // 9 Receive Channel enable bit + Uint16 RCEB10:1; // 10 Receive Channel enable bit + Uint16 RCEB11:1; // 11 Receive Channel enable bit + Uint16 RCEB12:1; // 12 Receive Channel enable bit + Uint16 RCEB13:1; // 13 Receive Channel enable bit + Uint16 RCEB14:1; // 14 Receive Channel enable bit + Uint16 RCEB15:1; // 15 Receive Channel enable bit +}; + +union RCERB_REG { + Uint16 all; + struct RCERB_BITS bit; +}; + +// +// XCERA control register bit definitions +// +struct XCERA_BITS { // bit description + Uint16 XCERA0:1; // 0 Receive Channel enable bit + Uint16 XCERA1:1; // 1 Receive Channel enable bit + Uint16 XCERA2:1; // 2 Receive Channel enable bit + Uint16 XCERA3:1; // 3 Receive Channel enable bit + Uint16 XCERA4:1; // 4 Receive Channel enable bit + Uint16 XCERA5:1; // 5 Receive Channel enable bit + Uint16 XCERA6:1; // 6 Receive Channel enable bit + Uint16 XCERA7:1; // 7 Receive Channel enable bit + Uint16 XCERA8:1; // 8 Receive Channel enable bit + Uint16 XCERA9:1; // 9 Receive Channel enable bit + Uint16 XCERA10:1; // 10 Receive Channel enable bit + Uint16 XCERA11:1; // 11 Receive Channel enable bit + Uint16 XCERA12:1; // 12 Receive Channel enable bit + Uint16 XCERA13:1; // 13 Receive Channel enable bit + Uint16 XCERA14:1; // 14 Receive Channel enable bit + Uint16 XCERA15:1; // 15 Receive Channel enable bit +}; + +union XCERA_REG { + Uint16 all; + struct XCERA_BITS bit; +}; + +// +// XCERB control register bit definitions +// +struct XCERB_BITS { // bit description + Uint16 XCERB0:1; // 0 Receive Channel enable bit + Uint16 XCERB1:1; // 1 Receive Channel enable bit + Uint16 XCERB2:1; // 2 Receive Channel enable bit + Uint16 XCERB3:1; // 3 Receive Channel enable bit + Uint16 XCERB4:1; // 4 Receive Channel enable bit + Uint16 XCERB5:1; // 5 Receive Channel enable bit + Uint16 XCERB6:1; // 6 Receive Channel enable bit + Uint16 XCERB7:1; // 7 Receive Channel enable bit + Uint16 XCERB8:1; // 8 Receive Channel enable bit + Uint16 XCERB9:1; // 9 Receive Channel enable bit + Uint16 XCERB10:1; // 10 Receive Channel enable bit + Uint16 XCERB11:1; // 11 Receive Channel enable bit + Uint16 XCERB12:1; // 12 Receive Channel enable bit + Uint16 XCERB13:1; // 13 Receive Channel enable bit + Uint16 XCERB14:1; // 14 Receive Channel enable bit + Uint16 XCERB15:1; // 15 Receive Channel enable bit +}; + +union XCERB_REG { + Uint16 all; + struct XCERB_BITS bit; +}; + +// +// PCR control register bit definitions +// +struct PCR_BITS { // bit description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP + Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP + Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP + Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit. + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmitter Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in + // this 28x-McBSP + Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP + Uint16 rsvd:1 ; // 15 reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +// +// RCERC control register bit definitions +// +struct RCERC_BITS { // bit description + Uint16 RCEC0:1; // 0 Receive Channel enable bit + Uint16 RCEC1:1; // 1 Receive Channel enable bit + Uint16 RCEC2:1; // 2 Receive Channel enable bit + Uint16 RCEC3:1; // 3 Receive Channel enable bit + Uint16 RCEC4:1; // 4 Receive Channel enable bit + Uint16 RCEC5:1; // 5 Receive Channel enable bit + Uint16 RCEC6:1; // 6 Receive Channel enable bit + Uint16 RCEC7:1; // 7 Receive Channel enable bit + Uint16 RCEC8:1; // 8 Receive Channel enable bit + Uint16 RCEC9:1; // 9 Receive Channel enable bit + Uint16 RCEC10:1; // 10 Receive Channel enable bit + Uint16 RCEC11:1; // 11 Receive Channel enable bit + Uint16 RCEC12:1; // 12 Receive Channel enable bit + Uint16 RCEC13:1; // 13 Receive Channel enable bit + Uint16 RCEC14:1; // 14 Receive Channel enable bit + Uint16 RCEC15:1; // 15 Receive Channel enable bit +}; + +union RCERC_REG { + Uint16 all; + struct RCERC_BITS bit; +}; + +// +// RCERD control register bit definitions +// +struct RCERD_BITS { // bit description + Uint16 RCED0:1; // 0 Receive Channel enable bit + Uint16 RCED1:1; // 1 Receive Channel enable bit + Uint16 RCED2:1; // 2 Receive Channel enable bit + Uint16 RCED3:1; // 3 Receive Channel enable bit + Uint16 RCED4:1; // 4 Receive Channel enable bit + Uint16 RCED5:1; // 5 Receive Channel enable bit + Uint16 RCED6:1; // 6 Receive Channel enable bit + Uint16 RCED7:1; // 7 Receive Channel enable bit + Uint16 RCED8:1; // 8 Receive Channel enable bit + Uint16 RCED9:1; // 9 Receive Channel enable bit + Uint16 RCED10:1; // 10 Receive Channel enable bit + Uint16 RCED11:1; // 11 Receive Channel enable bit + Uint16 RCED12:1; // 12 Receive Channel enable bit + Uint16 RCED13:1; // 13 Receive Channel enable bit + Uint16 RCED14:1; // 14 Receive Channel enable bit + Uint16 RCED15:1; // 15 Receive Channel enable bit +}; + +union RCERD_REG { + Uint16 all; + struct RCERD_BITS bit; +}; + +// +// XCERC control register bit definitions +// +struct XCERC_BITS { // bit description + Uint16 XCERC0:1; // 0 Receive Channel enable bit + Uint16 XCERC1:1; // 1 Receive Channel enable bit + Uint16 XCERC2:1; // 2 Receive Channel enable bit + Uint16 XCERC3:1; // 3 Receive Channel enable bit + Uint16 XCERC4:1; // 4 Receive Channel enable bit + Uint16 XCERC5:1; // 5 Receive Channel enable bit + Uint16 XCERC6:1; // 6 Receive Channel enable bit + Uint16 XCERC7:1; // 7 Receive Channel enable bit + Uint16 XCERC8:1; // 8 Receive Channel enable bit + Uint16 XCERC9:1; // 9 Receive Channel enable bit + Uint16 XCERC10:1; // 10 Receive Channel enable bit + Uint16 XCERC11:1; // 11 Receive Channel enable bit + Uint16 XCERC12:1; // 12 Receive Channel enable bit + Uint16 XCERC13:1; // 13 Receive Channel enable bit + Uint16 XCERC14:1; // 14 Receive Channel enable bit + Uint16 XCERC15:1; // 15 Receive Channel enable bit +}; + +union XCERC_REG { + Uint16 all; + struct XCERC_BITS bit; +}; + +// +// XCERD control register bit definitions +// +struct XCERD_BITS { // bit description + Uint16 XCERD0:1; // 0 Receive Channel enable bit + Uint16 XCERD1:1; // 1 Receive Channel enable bit + Uint16 XCERD2:1; // 2 Receive Channel enable bit + Uint16 XCERD3:1; // 3 Receive Channel enable bit + Uint16 XCERD4:1; // 4 Receive Channel enable bit + Uint16 XCERD5:1; // 5 Receive Channel enable bit + Uint16 XCERD6:1; // 6 Receive Channel enable bit + Uint16 XCERD7:1; // 7 Receive Channel enable bit + Uint16 XCERD8:1; // 8 Receive Channel enable bit + Uint16 XCERD9:1; // 9 Receive Channel enable bit + Uint16 XCERD10:1; // 10 Receive Channel enable bit + Uint16 XCERD11:1; // 11 Receive Channel enable bit + Uint16 XCERD12:1; // 12 Receive Channel enable bit + Uint16 XCERD13:1; // 13 Receive Channel enable bit + Uint16 XCERD14:1; // 14 Receive Channel enable bit + Uint16 XCERD15:1; // 15 Receive Channel enable bit +}; + +union XCERD_REG { + Uint16 all; + struct XCERD_BITS bit; +}; + +// +// RCERE control register bit definitions +// +struct RCERE_BITS { // bit description + Uint16 RCEE0:1; // 0 Receive Channel enable bit + Uint16 RCEE1:1; // 1 Receive Channel enable bit + Uint16 RCEE2:1; // 2 Receive Channel enable bit + Uint16 RCEE3:1; // 3 Receive Channel enable bit + Uint16 RCEE4:1; // 4 Receive Channel enable bit + Uint16 RCEE5:1; // 5 Receive Channel enable bit + Uint16 RCEE6:1; // 6 Receive Channel enable bit + Uint16 RCEE7:1; // 7 Receive Channel enable bit + Uint16 RCEE8:1; // 8 Receive Channel enable bit + Uint16 RCEE9:1; // 9 Receive Channel enable bit + Uint16 RCEE10:1; // 10 Receive Channel enable bit + Uint16 RCEE11:1; // 11 Receive Channel enable bit + Uint16 RCEE12:1; // 12 Receive Channel enable bit + Uint16 RCEE13:1; // 13 Receive Channel enable bit + Uint16 RCEE14:1; // 14 Receive Channel enable bit + Uint16 RCEE15:1; // 15 Receive Channel enable bit +}; + +union RCERE_REG { + Uint16 all; + struct RCERE_BITS bit; +}; + +// +// RCERF control register bit definitions +// +struct RCERF_BITS { // bit description + Uint16 RCEF0:1; // 0 Receive Channel enable bit + Uint16 RCEF1:1; // 1 Receive Channel enable bit + Uint16 RCEF2:1; // 2 Receive Channel enable bit + Uint16 RCEF3:1; // 3 Receive Channel enable bit + Uint16 RCEF4:1; // 4 Receive Channel enable bit + Uint16 RCEF5:1; // 5 Receive Channel enable bit + Uint16 RCEF6:1; // 6 Receive Channel enable bit + Uint16 RCEF7:1; // 7 Receive Channel enable bit + Uint16 RCEF8:1; // 8 Receive Channel enable bit + Uint16 RCEF9:1; // 9 Receive Channel enable bit + Uint16 RCEF10:1; // 10 Receive Channel enable bit + Uint16 RCEF11:1; // 11 Receive Channel enable bit + Uint16 RCEF12:1; // 12 Receive Channel enable bit + Uint16 RCEF13:1; // 13 Receive Channel enable bit + Uint16 RCEF14:1; // 14 Receive Channel enable bit + Uint16 RCEF15:1; // 15 Receive Channel enable bit +}; + +union RCERF_REG { + Uint16 all; + struct RCERF_BITS bit; +}; + +// XCERE control register bit definitions: +struct XCERE_BITS { // bit description + Uint16 XCERE0:1; // 0 Receive Channel enable bit + Uint16 XCERE1:1; // 1 Receive Channel enable bit + Uint16 XCERE2:1; // 2 Receive Channel enable bit + Uint16 XCERE3:1; // 3 Receive Channel enable bit + Uint16 XCERE4:1; // 4 Receive Channel enable bit + Uint16 XCERE5:1; // 5 Receive Channel enable bit + Uint16 XCERE6:1; // 6 Receive Channel enable bit + Uint16 XCERE7:1; // 7 Receive Channel enable bit + Uint16 XCERE8:1; // 8 Receive Channel enable bit + Uint16 XCERE9:1; // 9 Receive Channel enable bit + Uint16 XCERE10:1; // 10 Receive Channel enable bit + Uint16 XCERE11:1; // 11 Receive Channel enable bit + Uint16 XCERE12:1; // 12 Receive Channel enable bit + Uint16 XCERE13:1; // 13 Receive Channel enable bit + Uint16 XCERE14:1; // 14 Receive Channel enable bit + Uint16 XCERE15:1; // 15 Receive Channel enable bit +}; + +union XCERE_REG { + Uint16 all; + struct XCERE_BITS bit; +}; + +// +// XCERF control register bit definitions +// +struct XCERF_BITS { // bit description + Uint16 XCERF0:1; // 0 Receive Channel enable bit + Uint16 XCERF1:1; // 1 Receive Channel enable bit + Uint16 XCERF2:1; // 2 Receive Channel enable bit + Uint16 XCERF3:1; // 3 Receive Channel enable bit + Uint16 XCERF4:1; // 4 Receive Channel enable bit + Uint16 XCERF5:1; // 5 Receive Channel enable bit + Uint16 XCERF6:1; // 6 Receive Channel enable bit + Uint16 XCERF7:1; // 7 Receive Channel enable bit + Uint16 XCERF8:1; // 8 Receive Channel enable bit + Uint16 XCERF9:1; // 9 Receive Channel enable bit + Uint16 XCERF10:1; // 10 Receive Channel enable bit + Uint16 XCERF11:1; // 11 Receive Channel enable bit + Uint16 XCERF12:1; // 12 Receive Channel enable bit + Uint16 XCERF13:1; // 13 Receive Channel enable bit + Uint16 XCERF14:1; // 14 Receive Channel enable bit + Uint16 XCERF15:1; // 15 Receive Channel enable bit +}; + +union XCERF_REG { + Uint16 all; + struct XCERF_BITS bit; +}; + +// +// RCERG control register bit definitions +// +struct RCERG_BITS { // bit description + Uint16 RCEG0:1; // 0 Receive Channel enable bit + Uint16 RCEG1:1; // 1 Receive Channel enable bit + Uint16 RCEG2:1; // 2 Receive Channel enable bit + Uint16 RCEG3:1; // 3 Receive Channel enable bit + Uint16 RCEG4:1; // 4 Receive Channel enable bit + Uint16 RCEG5:1; // 5 Receive Channel enable bit + Uint16 RCEG6:1; // 6 Receive Channel enable bit + Uint16 RCEG7:1; // 7 Receive Channel enable bit + Uint16 RCEG8:1; // 8 Receive Channel enable bit + Uint16 RCEG9:1; // 9 Receive Channel enable bit + Uint16 RCEG10:1; // 10 Receive Channel enable bit + Uint16 RCEG11:1; // 11 Receive Channel enable bit + Uint16 RCEG12:1; // 12 Receive Channel enable bit + Uint16 RCEG13:1; // 13 Receive Channel enable bit + Uint16 RCEG14:1; // 14 Receive Channel enable bit + Uint16 RCEG15:1; // 15 Receive Channel enable bit +}; + +union RCERG_REG { + Uint16 all; + struct RCERG_BITS bit; +}; + +// RCERH control register bit definitions: +struct RCERH_BITS { // bit description + Uint16 RCEH0:1; // 0 Receive Channel enable bit + Uint16 RCEH1:1; // 1 Receive Channel enable bit + Uint16 RCEH2:1; // 2 Receive Channel enable bit + Uint16 RCEH3:1; // 3 Receive Channel enable bit + Uint16 RCEH4:1; // 4 Receive Channel enable bit + Uint16 RCEH5:1; // 5 Receive Channel enable bit + Uint16 RCEH6:1; // 6 Receive Channel enable bit + Uint16 RCEH7:1; // 7 Receive Channel enable bit + Uint16 RCEH8:1; // 8 Receive Channel enable bit + Uint16 RCEH9:1; // 9 Receive Channel enable bit + Uint16 RCEH10:1; // 10 Receive Channel enable bit + Uint16 RCEH11:1; // 11 Receive Channel enable bit + Uint16 RCEH12:1; // 12 Receive Channel enable bit + Uint16 RCEH13:1; // 13 Receive Channel enable bit + Uint16 RCEH14:1; // 14 Receive Channel enable bit + Uint16 RCEH15:1; // 15 Receive Channel enable bit +}; + +union RCERH_REG { + Uint16 all; + struct RCERH_BITS bit; +}; + +// +// XCERG control register bit definitions +// +struct XCERG_BITS { // bit description + Uint16 XCERG0:1; // 0 Receive Channel enable bit + Uint16 XCERG1:1; // 1 Receive Channel enable bit + Uint16 XCERG2:1; // 2 Receive Channel enable bit + Uint16 XCERG3:1; // 3 Receive Channel enable bit + Uint16 XCERG4:1; // 4 Receive Channel enable bit + Uint16 XCERG5:1; // 5 Receive Channel enable bit + Uint16 XCERG6:1; // 6 Receive Channel enable bit + Uint16 XCERG7:1; // 7 Receive Channel enable bit + Uint16 XCERG8:1; // 8 Receive Channel enable bit + Uint16 XCERG9:1; // 9 Receive Channel enable bit + Uint16 XCERG10:1; // 10 Receive Channel enable bit + Uint16 XCERG11:1; // 11 Receive Channel enable bit + Uint16 XCERG12:1; // 12 Receive Channel enable bit + Uint16 XCERG13:1; // 13 Receive Channel enable bit + Uint16 XCERG14:1; // 14 Receive Channel enable bit + Uint16 XCERG15:1; // 15 Receive Channel enable bit +}; + +union XCERG_REG { + Uint16 all; + struct XCERG_BITS bit; +}; + +// +// XCERH control register bit definitions +// +struct XCERH_BITS { // bit description + Uint16 XCEH0:1; // 0 Receive Channel enable bit + Uint16 XCEH1:1; // 1 Receive Channel enable bit + Uint16 XCEH2:1; // 2 Receive Channel enable bit + Uint16 XCEH3:1; // 3 Receive Channel enable bit + Uint16 XCEH4:1; // 4 Receive Channel enable bit + Uint16 XCEH5:1; // 5 Receive Channel enable bit + Uint16 XCEH6:1; // 6 Receive Channel enable bit + Uint16 XCEH7:1; // 7 Receive Channel enable bit + Uint16 XCEH8:1; // 8 Receive Channel enable bit + Uint16 XCEH9:1; // 9 Receive Channel enable bit + Uint16 XCEH10:1; // 10 Receive Channel enable bit + Uint16 XCEH11:1; // 11 Receive Channel enable bit + Uint16 XCEH12:1; // 12 Receive Channel enable bit + Uint16 XCEH13:1; // 13 Receive Channel enable bit + Uint16 XCEH14:1; // 14 Receive Channel enable bit + Uint16 XCEH15:1; // 15 Receive Channel enable bit +}; + +union XCERH_REG { + Uint16 all; + struct XCERH_BITS bit; +}; + +// +// McBSP Interrupt enable register for RINT/XINT +// +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 XINT interrupt enable + Uint16 rsvd1:1; // 1 reserved + Uint16 RINT:1; // 2 RINT interrupt enable + Uint16 rsvd2:13; // 15:3 reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +// +// McBSP Register File +// +struct MCBSP_REGS { + union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16 + union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0 + union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16 + union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // MCBSP control register bits 31-16 + union SPCR1_REG SPCR1; // MCBSP control register bits 15-0 + union RCR2_REG RCR2; // MCBSP receive control register bits 31-16 + union RCR1_REG RCR1; // MCBSP receive control register bits 15-0 + union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16 + union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0 + union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16 + union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0 + union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16 + union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0 + union RCERA_REG RCERA; // MCBSP Receive channel enable partition A + union RCERB_REG RCERB; // MCBSP Receive channel enable partition B + union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A + union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B + union PCR_REG PCR; // MCBSP Pin control register bits 15-0 + union RCERC_REG RCERC; // MCBSP Receive channel enable partition C + union RCERD_REG RCERD; // MCBSP Receive channel enable partition D + union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C + union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D + union RCERE_REG RCERE; // MCBSP Receive channel enable partition E + union RCERF_REG RCERF; // MCBSP Receive channel enable partition F + union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E + union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F + union RCERG_REG RCERG; // MCBSP Receive channel enable partition G + union RCERH_REG RCERH; // MCBSP Receive channel enable partition H + union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G + union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H + Uint16 rsvd1[4]; // reserved + union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for + // RINT/XINT + Uint16 rsvd2; // reserved +}; + +// +// McBSP External References & Function Declarations +// +extern volatile struct MCBSP_REGS McbspaRegs; +extern volatile struct MCBSP_REGS McbspbRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_MCBSP_H definition + +// +// No more +// + diff --git a/F28335/DSP2833x_PieCtrl.h b/F28335/DSP2833x_PieCtrl.h new file mode 100644 index 0000000..c6a5625 --- /dev/null +++ b/F28335/DSP2833x_PieCtrl.h @@ -0,0 +1,164 @@ +//########################################################################### +// +// FILE: DSP2833x_PieCtrl.h +// +// TITLE: DSP2833x Device PIE Control Register Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_PIE_CTRL_H +#define DSP2833x_PIE_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Control Register Bit Definitions +// + +// +// PIECTRL: Register bit definitions +// +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 Enable PIE block + Uint16 PIEVECT:15; // 15:1 Fetched vector address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +// +// PIEIER: Register bit definitions +// +struct PIEIER_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIER_REG { + Uint16 all; + struct PIEIER_BITS bit; +}; + +// +// PIEIFR: Register bit definitions +// +struct PIEIFR_BITS { // bits description + Uint16 INTx1:1; // 0 INTx.1 + Uint16 INTx2:1; // 1 INTx.2 + Uint16 INTx3:1; // 2 INTx.3 + Uint16 INTx4:1; // 3 INTx.4 + Uint16 INTx5:1; // 4 INTx.5 + Uint16 INTx6:1; // 5 INTx.6 + Uint16 INTx7:1; // 6 INTx.7 + Uint16 INTx8:1; // 7 INTx.8 + Uint16 rsvd:8; // 15:8 reserved +}; + +union PIEIFR_REG { + Uint16 all; + struct PIEIFR_BITS bit; +}; + +// +// PIEACK: Register bit definitions +// +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 + Uint16 rsvd:4; // 15:12 reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +// +// PIE Control Register File +// +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // PIE control register + union PIEACK_REG PIEACK; // PIE acknowledge + union PIEIER_REG PIEIER1; // PIE int1 IER register + union PIEIFR_REG PIEIFR1; // PIE int1 IFR register + union PIEIER_REG PIEIER2; // PIE INT2 IER register + union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register + union PIEIER_REG PIEIER3; // PIE INT3 IER register + union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register + union PIEIER_REG PIEIER4; // PIE INT4 IER register + union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register + union PIEIER_REG PIEIER5; // PIE INT5 IER register + union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register + union PIEIER_REG PIEIER6; // PIE INT6 IER register + union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register + union PIEIER_REG PIEIER7; // PIE INT7 IER register + union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register + union PIEIER_REG PIEIER8; // PIE INT8 IER register + union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register + union PIEIER_REG PIEIER9; // PIE INT9 IER register + union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register + union PIEIER_REG PIEIER10; // PIE int10 IER register + union PIEIFR_REG PIEIFR10; // PIE int10 IFR register + union PIEIER_REG PIEIER11; // PIE int11 IER register + union PIEIFR_REG PIEIFR11; // PIE int11 IFR register + union PIEIER_REG PIEIER12; // PIE int12 IER register + union PIEIFR_REG PIEIFR12; // PIE int12 IFR register +}; + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +// +// PIE Control Registers External References & Function Declarations +// +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_CTRL_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_PieVect.h b/F28335/DSP2833x_PieVect.h new file mode 100644 index 0000000..2f9be8f --- /dev/null +++ b/F28335/DSP2833x_PieVect.h @@ -0,0 +1,234 @@ +//########################################################################### +// +// FILE: DSP2833x_PieVect.h +// +// TITLE: DSP2833x Devices PIE Vector Table Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_PIE_VECT_H +#define DSP2833x_PIE_VECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// PIE Interrupt Vector Table Definition +// + +// +// Typedef used to create a user type called PINT (pointer to interrupt) +// +typedef interrupt void(*PINT)(void); + +// +// Vector Table Define +// +struct PIE_VECT_TABLE { + // + // Reset is never fetched from this table. It will always be fetched from + // 0x3FFFC0 in boot ROM + // + PINT PIE1_RESERVED; + PINT PIE2_RESERVED; + PINT PIE3_RESERVED; + PINT PIE4_RESERVED; + PINT PIE5_RESERVED; + PINT PIE6_RESERVED; + PINT PIE7_RESERVED; + PINT PIE8_RESERVED; + PINT PIE9_RESERVED; + PINT PIE10_RESERVED; + PINT PIE11_RESERVED; + PINT PIE12_RESERVED; + PINT PIE13_RESERVED; + + // + // Non-Peripheral Interrupts + // + PINT XINT13; // XINT13 / CPU-Timer1 + PINT TINT2; // CPU-Timer2 + PINT DATALOG; // Datalogging interrupt + PINT RTOSINT; // RTOS interrupt + PINT EMUINT; // Emulation interrupt + PINT XNMI; // Non-maskable interrupt + PINT ILLEGAL; // Illegal operation TRAP + PINT USER1; // User Defined trap 1 + PINT USER2; // User Defined trap 2 + PINT USER3; // User Defined trap 3 + PINT USER4; // User Defined trap 4 + PINT USER5; // User Defined trap 5 + PINT USER6; // User Defined trap 6 + PINT USER7; // User Defined trap 7 + PINT USER8; // User Defined trap 8 + PINT USER9; // User Defined trap 9 + PINT USER10; // User Defined trap 10 + PINT USER11; // User Defined trap 11 + PINT USER12; // User Defined trap 12 + + // + // Group 1 PIE Peripheral Vectors + // + PINT SEQ1INT; + PINT SEQ2INT; + PINT rsvd1_3; + PINT XINT1; + PINT XINT2; + PINT ADCINT; // ADC + PINT TINT0; // Timer 0 + PINT WAKEINT; // WD + + // + // Group 2 PIE Peripheral Vectors + // + PINT EPWM1_TZINT; // EPWM-1 + PINT EPWM2_TZINT; // EPWM-2 + PINT EPWM3_TZINT; // EPWM-3 + PINT EPWM4_TZINT; // EPWM-4 + PINT EPWM5_TZINT; // EPWM-5 + PINT EPWM6_TZINT; // EPWM-6 + PINT rsvd2_7; + PINT rsvd2_8; + + // + // Group 3 PIE Peripheral Vectors + // + PINT EPWM1_INT; // EPWM-1 + PINT EPWM2_INT; // EPWM-2 + PINT EPWM3_INT; // EPWM-3 + PINT EPWM4_INT; // EPWM-4 + PINT EPWM5_INT; // EPWM-5 + PINT EPWM6_INT; // EPWM-6 + PINT rsvd3_7; + PINT rsvd3_8; + + // + // Group 4 PIE Peripheral Vectors + // + PINT ECAP1_INT; // ECAP-1 + PINT ECAP2_INT; // ECAP-2 + PINT ECAP3_INT; // ECAP-3 + PINT ECAP4_INT; // ECAP-4 + PINT ECAP5_INT; // ECAP-5 + PINT ECAP6_INT; // ECAP-6 + PINT rsvd4_7; + PINT rsvd4_8; + + // + // Group 5 PIE Peripheral Vectors + // + PINT EQEP1_INT; // EQEP-1 + PINT EQEP2_INT; // EQEP-2 + PINT rsvd5_3; + PINT rsvd5_4; + PINT rsvd5_5; + PINT rsvd5_6; + PINT rsvd5_7; + PINT rsvd5_8; + + // + // Group 6 PIE Peripheral Vectors + // + PINT SPIRXINTA; // SPI-A + PINT SPITXINTA; // SPI-A + PINT MRINTB; // McBSP-B + PINT MXINTB; // McBSP-B + PINT MRINTA; // McBSP-A + PINT MXINTA; // McBSP-A + PINT rsvd6_7; + PINT rsvd6_8; + + // + // Group 7 PIE Peripheral Vectors + // + PINT DINTCH1; // DMA + PINT DINTCH2; // DMA + PINT DINTCH3; // DMA + PINT DINTCH4; // DMA + PINT DINTCH5; // DMA + PINT DINTCH6; // DMA + PINT rsvd7_7; + PINT rsvd7_8; + + // + // Group 8 PIE Peripheral Vectors + // + PINT I2CINT1A; // I2C-A + PINT I2CINT2A; // I2C-A + PINT rsvd8_3; + PINT rsvd8_4; + PINT SCIRXINTC; // SCI-C + PINT SCITXINTC; // SCI-C + PINT rsvd8_7; + PINT rsvd8_8; + + // + // Group 9 PIE Peripheral Vectors + // + PINT SCIRXINTA; // SCI-A + PINT SCITXINTA; // SCI-A + PINT SCIRXINTB; // SCI-B + PINT SCITXINTB; // SCI-B + PINT ECAN0INTA; // eCAN-A + PINT ECAN1INTA; // eCAN-A + PINT ECAN0INTB; // eCAN-B + PINT ECAN1INTB; // eCAN-B + + // + // Group 10 PIE Peripheral Vectors + // + PINT rsvd10_1; + PINT rsvd10_2; + PINT rsvd10_3; + PINT rsvd10_4; + PINT rsvd10_5; + PINT rsvd10_6; + PINT rsvd10_7; + PINT rsvd10_8; + + // + // Group 11 PIE Peripheral Vectors + // + PINT rsvd11_1; + PINT rsvd11_2; + PINT rsvd11_3; + PINT rsvd11_4; + PINT rsvd11_5; + PINT rsvd11_6; + PINT rsvd11_7; + PINT rsvd11_8; + + // + // Group 12 PIE Peripheral Vectors + // + PINT XINT3; // External interrupt + PINT XINT4; + PINT XINT5; + PINT XINT6; + PINT XINT7; + PINT rsvd12_6; + PINT LVF; // Latched overflow + PINT LUF; // Latched underflow +}; + +// +// PIE Interrupt Vector Table External References & Function Declarations +// +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_PIE_VECT_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_Sci.h b/F28335/DSP2833x_Sci.h new file mode 100644 index 0000000..8b4ce1a --- /dev/null +++ b/F28335/DSP2833x_Sci.h @@ -0,0 +1,220 @@ +//########################################################################### +// +// FILE: DSP2833x_Sci.h +// +// TITLE: DSP2833x Device SCI Register Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_SCI_H +#define DSP2833x_SCI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SCI Individual Register Bit Definitions +// + +// +// SCICCR communication control register bit definitions +// +struct SCICCR_BITS { // bit description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +// +// SCICTL1 control register 1 bit definitions +// +struct SCICTL1_BITS { // bit description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd:1; // 4 reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable + Uint16 rsvd1:9; // 15:7 reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +// +// SCICTL2 control register 2 bit definitions +// +struct SCICTL2_BITS { // bit description + Uint16 TXINTENA:1; // 0 Transmit interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd:4; // 5:2 reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd1:8; // 15:8 reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +// +// SCIRXST Receiver status register bit definitions +// +struct SCIRXST_BITS { // bit description + Uint16 rsvd:1; // 0 reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +// +// SCIRXBUF Receiver Data Buffer with FIFO bit definitions +// +struct SCIRXBUF_BITS { // bits description + Uint16 RXDT:8; // 7:0 Receive word + Uint16 rsvd:6; // 13:8 reserved + Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode + Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +// +// SCIPRI Priority control register bit definitions +// +struct SCIPRI_BITS { // bit description + Uint16 rsvd:3; // 2:0 reserved + Uint16 FREE:1; // 3 Free emulation suspend mode + Uint16 SOFT:1; // 4 Soft emulation suspend mode + Uint16 rsvd1:3; // 7:5 reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +// +// SCI FIFO Transmit register bit definitions +// +struct SCIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFOXRESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +// +// SCI FIFO recieve register bit definitions +// +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +// +// SCI FIFO control register bit definitions +// +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:5; // 12:8 reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +// +// SCI Register File +// +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + Uint16 SCIHBAUD; // Baud rate (high) register + Uint16 SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + Uint16 SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // reserved + Uint16 SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + union SCIPRI_REG SCIPRI; // FIFO Priority control +}; + +// +// SCI External References & Function Declarations +// +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SCI_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_Spi.h b/F28335/DSP2833x_Spi.h new file mode 100644 index 0000000..6c3cf94 --- /dev/null +++ b/F28335/DSP2833x_Spi.h @@ -0,0 +1,177 @@ +//########################################################################### +// +// FILE: DSP2833x_Spi.h +// +// TITLE: DSP2833x Device SPI Register Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_SPI_H +#define DSP2833x_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// SPI Individual Register Bit Definitions +// + +// +// SPI FIFO Transmit register bit definitions +// +struct SPIFFTX_BITS { // bit description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFO:1; // 13 FIFO reset + Uint16 SPIFFENA:1; // 14 Enhancement enable + Uint16 SPIRST:1; // 15 Reset SPI +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +// +// SPI FIFO recieve register bit definitions +// +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVFCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +// +// SPI FIFO control register bit definitions +// +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd:8; // 15:8 reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +// +// SPI configuration register bit definitions +// +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character length control + Uint16 SPILBK:1; // 4 Loop-back enable/disable + Uint16 rsvd1:1; // 5 reserved + Uint16 CLKPOLARITY:1; // 6 Clock polarity + Uint16 SPISWRESET:1; // 7 SPI SW Reset + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +// +// SPI operation control register bit definitions +// +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 Interrupt enable + Uint16 TALK:1; // 1 Master/Slave transmit enable + Uint16 MASTER_SLAVE:1; // 2 Network control mode + Uint16 CLK_PHASE:1; // 3 Clock phase select + Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable + Uint16 rsvd:11; // 15:5 reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +// +// SPI status register bit definitions +// +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag + Uint16 INT_FLAG:1; // 6 SPI interrupt flag + Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag + Uint16 rsvd2:8; // 15:8 reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +// +// SPI priority control register bit definitions +// +struct SPIPRI_BITS { // bits description + Uint16 rsvd1:4; // 3:0 reserved + Uint16 FREE:1; // 4 Free emulation mode control + Uint16 SOFT:1; // 5 Soft emulation mode control + Uint16 rsvd2:1; // 6 reserved + Uint16 rsvd3:9; // 15:7 reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +// +// SPI Register File +// +struct SPI_REGS { + union SPICCR_REG SPICCR; // Configuration register + union SPICTL_REG SPICTL; // Operation control register + union SPISTS_REG SPISTS; // Status register + Uint16 rsvd1; // reserved + Uint16 SPIBRR; // Baud Rate + Uint16 rsvd2; // reserved + Uint16 SPIRXEMU; // Emulation buffer + Uint16 SPIRXBUF; // Serial input buffer + Uint16 SPITXBUF; // Serial output buffer + Uint16 SPIDAT; // Serial data + union SPIFFTX_REG SPIFFTX; // FIFO transmit register + union SPIFFRX_REG SPIFFRX; // FIFO recieve register + union SPIFFCT_REG SPIFFCT; // FIFO control register + Uint16 rsvd3[2]; // reserved + union SPIPRI_REG SPIPRI; // FIFO Priority control +}; + +// +// SPI External References & Function Declarations +// +extern volatile struct SPI_REGS SpiaRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SPI_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_SysCtrl.h b/F28335/DSP2833x_SysCtrl.h new file mode 100644 index 0000000..f04697f --- /dev/null +++ b/F28335/DSP2833x_SysCtrl.h @@ -0,0 +1,453 @@ +//########################################################################### +// +// FILE: DSP2833x_SysCtrl.h +// +// TITLE: DSP2833x Device System Control Register Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_SYS_CTRL_H +#define DSP2833x_SYS_CTRL_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// System Control Individual Register Bit Definitions +// + +// +// PLL Status Register +// +struct PLLSTS_BITS { // bits description + Uint16 PLLLOCKS:1; // 0 PLL lock status + Uint16 rsvd1:1; // 1 reserved + Uint16 PLLOFF:1; // 2 PLL off bit + Uint16 MCLKSTS:1; // 3 Missing clock status bit + Uint16 MCLKCLR:1; // 4 Missing clock clear bit + Uint16 OSCOFF:1; // 5 Oscillator clock off + Uint16 MCLKOFF:1; // 6 Missing clock detect + Uint16 DIVSEL:2; // 7 Divide Select + Uint16 rsvd2:7; // 15:7 reserved +}; + +union PLLSTS_REG { + Uint16 all; + struct PLLSTS_BITS bit; +}; + +// +// High speed peripheral clock register bit definitions +// +struct HISPCP_BITS { // bits description + Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union HISPCP_REG { + Uint16 all; + struct HISPCP_BITS bit; +}; + +// +// Low speed peripheral clock register bit definitions +// +struct LOSPCP_BITS { // bits description + Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT + Uint16 rsvd1:13; // 15:3 reserved +}; + +union LOSPCP_REG { + Uint16 all; + struct LOSPCP_BITS bit; +}; + +// +// Peripheral clock control register 0 bit definitions +// +struct PCLKCR0_BITS { // bits description + Uint16 rsvd1:2; // 1:0 reserved + Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync + Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC + Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A + Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C + Uint16 rsvd2:2; // 7:6 reserved + Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A + Uint16 rsvd3:1; // 9 reserved + Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A + Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B + Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A + Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B + Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A + Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B +}; + +union PCLKCR0_REG { + Uint16 all; + struct PCLKCR0_BITS bit; +}; + +// +// Peripheral clock control register 1 bit definitions +// +struct PCLKCR1_BITS { // bits description + Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 + Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 + Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 + Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 + Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 + Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 + Uint16 rsvd1:2; // 7:6 reserved + Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 + Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 + Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 + Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 + Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5 + Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6 + Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1 + Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2 +}; + +union PCLKCR1_REG { + Uint16 all; + struct PCLKCR1_BITS bit; +}; + +// +// Peripheral clock control register 2 bit definitions +// +struct PCLKCR3_BITS { // bits description + Uint16 rsvd1:8; // 7:0 reserved + Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0 + Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1 + Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2 + Uint16 DMAENCLK:1; // 11 Enable the DMA clock + Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF + Uint16 GPIOINENCLK:1; // Enable GPIO input clock + Uint16 rsvd2:2; // 15:14 reserved +}; + +union PCLKCR3_REG { + Uint16 all; + struct PCLKCR3_BITS bit; +}; + +// +// PLL control register bit definitions +// +struct PLLCR_BITS { // bits description + Uint16 DIV:4; // 3:0 Set clock ratio for the PLL + Uint16 rsvd1:12; // 15:4 reserved +}; + +union PLLCR_REG { + Uint16 all; + struct PLLCR_BITS bit; +}; + +// +// Low Power Mode 0 control register bit definitions +// +struct LPMCR0_BITS { // bits description + Uint16 LPM:2; // 1:0 Set the low power mode + Uint16 QUALSTDBY:6; // 7:2 Qualification + Uint16 rsvd1:7; // 14:8 reserved + Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY +}; + +union LPMCR0_REG { + Uint16 all; + struct LPMCR0_BITS bit; +}; + +// +// Dual-mapping configuration register bit definitions +// +struct MAPCNF_BITS { // bits description + Uint16 MAPEPWM:1; // 0 EPWM dual-map enable + Uint16 rsvd1:15; // 15:1 reserved +}; + +union MAPCNF_REG { + Uint16 all; + struct MAPCNF_BITS bit; +}; + +// +// System Control Register File +// +struct SYS_CTRL_REGS { + Uint16 rsvd1; // 0 + union PLLSTS_REG PLLSTS; // 1 + Uint16 rsvd2[8]; // 2-9 + + // + // 10: High-speed peripheral clock pre-scaler + // + union HISPCP_REG HISPCP; + + union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler + union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register + union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register + union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 + Uint16 rsvd3; // 15: reserved + union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register + union PLLCR_REG PLLCR; // 17: PLL control register + + // + // No bit definitions are defined for SCSR because + // a read-modify-write instruction can clear the WDOVERRIDE bit + // + Uint16 SCSR; // 18: System control and status register + + Uint16 WDCNTR; // 19: WD counter register + Uint16 rsvd4; // 20 + Uint16 WDKEY; // 21: WD reset key register + Uint16 rsvd5[3]; // 22-24 + + // + // No bit definitions are defined for WDCR because + // the proper value must be written to the WDCHK field + // whenever writing to this register. + // + Uint16 WDCR; // 25: WD timer control register + + Uint16 rsvd6[4]; // 26-29 + union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register + Uint16 rsvd7[1]; // 31 +}; + +// +// CSM Registers +// + +// +// CSM Status & Control register bit definitions +// +struct CSMSCR_BITS { // bit description + Uint16 SECURE:1; // 0 Secure flag + Uint16 rsvd1:14; // 14-1 reserved + Uint16 FORCESEC:1; // 15 Force Secure control bit +}; + +// +// Allow access to the bit fields or entire register +// +union CSMSCR_REG { + Uint16 all; + struct CSMSCR_BITS bit; +}; + +// +// CSM Register File +// +struct CSM_REGS { + Uint16 KEY0; // KEY reg bits 15-0 + Uint16 KEY1; // KEY reg bits 31-16 + Uint16 KEY2; // KEY reg bits 47-32 + Uint16 KEY3; // KEY reg bits 63-48 + Uint16 KEY4; // KEY reg bits 79-64 + Uint16 KEY5; // KEY reg bits 95-80 + Uint16 KEY6; // KEY reg bits 111-96 + Uint16 KEY7; // KEY reg bits 127-112 + Uint16 rsvd1; // reserved + Uint16 rsvd2; // reserved + Uint16 rsvd3; // reserved + Uint16 rsvd4; // reserved + Uint16 rsvd5; // reserved + Uint16 rsvd6; // reserved + Uint16 rsvd7; // reserved + union CSMSCR_REG CSMSCR; // CSM Status & Control register +}; + +// +// Password locations +// +struct CSM_PWL { + Uint16 PSWD0; // PSWD bits 15-0 + Uint16 PSWD1; // PSWD bits 31-16 + Uint16 PSWD2; // PSWD bits 47-32 + Uint16 PSWD3; // PSWD bits 63-48 + Uint16 PSWD4; // PSWD bits 79-64 + Uint16 PSWD5; // PSWD bits 95-80 + Uint16 PSWD6; // PSWD bits 111-96 + Uint16 PSWD7; // PSWD bits 127-112 +}; + +// +// Defines for Flash Registers +// +#define FLASH_SLEEP 0x0000; +#define FLASH_STANDBY 0x0001; +#define FLASH_ACTIVE 0x0003; + +// +// Flash Option Register bit definitions +// +struct FOPT_BITS { // bit description + Uint16 ENPIPE:1; // 0 Enable Pipeline Mode + Uint16 rsvd:15; // 1-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOPT_REG { + Uint16 all; + struct FOPT_BITS bit; +}; + +// +// Flash Power Modes Register bit definitions +// +struct FPWR_BITS { // bit description + Uint16 PWR:2; // 0-1 Power Mode bits + Uint16 rsvd:14; // 2-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FPWR_REG { + Uint16 all; + struct FPWR_BITS bit; +}; + +// +// Flash Status Register bit definitions +// +struct FSTATUS_BITS { // bit description + Uint16 PWRS:2; // 0-1 Power Mode Status bits + Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits + Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 V3STAT:1; // 8 VDD3V Status Latch bit + Uint16 rsvd2:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTATUS_REG { + Uint16 all; + struct FSTATUS_BITS bit; +}; + +// +// Flash Sleep to Standby Wait Counter Register bit definitions +// +struct FSTDBYWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Sleep to Standby Wait Count bits + // + Uint16 STDBYWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FSTDBYWAIT_REG { + Uint16 all; + struct FSTDBYWAIT_BITS bit; +}; + +// +// Flash Standby to Active Wait Counter Register bit definitions +// +struct FACTIVEWAIT_BITS { // bit description + // + // 0-8 Bank/Pump Standby to Active Wait Count bits + // + Uint16 ACTIVEWAIT:9; + + Uint16 rsvd:7; // 9-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FACTIVEWAIT_REG { + Uint16 all; + struct FACTIVEWAIT_BITS bit; +}; + +// +// Bank Read Access Wait State Register bit definitions +// +struct FBANKWAIT_BITS { // bit description + Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits + Uint16 rsvd1:4; // 4-7 reserved + Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits + Uint16 rsvd2:4; // 12-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FBANKWAIT_REG { + Uint16 all; + struct FBANKWAIT_BITS bit; +}; + +// +// OTP Read Access Wait State Register bit definitions +// +struct FOTPWAIT_BITS { // bit description + Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits + Uint16 rsvd:11; // 5-15 reserved +}; + +// +// Allow access to the bit fields or entire register +// +union FOTPWAIT_REG { + Uint16 all; + struct FOTPWAIT_BITS bit; +}; + +struct FLASH_REGS { + union FOPT_REG FOPT; // Option Register + Uint16 rsvd1; // reserved + union FPWR_REG FPWR; // Power Modes Register + union FSTATUS_REG FSTATUS; // Status Register + + // + // Pump/Bank Sleep to Standby Wait State Register + // + union FSTDBYWAIT_REG FSTDBYWAIT; + + // + // Pump/Bank Standby to Active Wait State Register + // + union FACTIVEWAIT_REG FACTIVEWAIT; + + union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register + union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register +}; + +// +// System Control External References & Function Declarations +// +extern volatile struct SYS_CTRL_REGS SysCtrlRegs; +extern volatile struct CSM_REGS CsmRegs; +extern volatile struct CSM_PWL CsmPwl; +extern volatile struct FLASH_REGS FlashRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_SYS_CTRL_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_XIntrupt.h b/F28335/DSP2833x_XIntrupt.h new file mode 100644 index 0000000..e0422b0 --- /dev/null +++ b/F28335/DSP2833x_XIntrupt.h @@ -0,0 +1,78 @@ +//########################################################################### +// +// FILE: DSP2833x_XIntrupt.h +// +// TITLE: DSP2833x Device External Interrupt Register Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_XINTRUPT_H +#define DSP2833x_XINTRUPT_H + + +#ifdef __cplusplus +extern "C" { +#endif + +struct XINTCR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 rsvd1:1; // 1 reserved + Uint16 POLARITY:2; // 3:2 pos/neg, both triggered + Uint16 rsvd2:12; //15:4 reserved +}; + +union XINTCR_REG { + Uint16 all; + struct XINTCR_BITS bit; +}; + +struct XNMICR_BITS { + Uint16 ENABLE:1; // 0 enable/disable + Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 + Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered + Uint16 rsvd2:12; // 15:4 reserved +}; + +union XNMICR_REG { + Uint16 all; + struct XNMICR_BITS bit; +}; + +// +// External Interrupt Register File +// +struct XINTRUPT_REGS { + union XINTCR_REG XINT1CR; + union XINTCR_REG XINT2CR; + union XINTCR_REG XINT3CR; + union XINTCR_REG XINT4CR; + union XINTCR_REG XINT5CR; + union XINTCR_REG XINT6CR; + union XINTCR_REG XINT7CR; + union XNMICR_REG XNMICR; + Uint16 XINT1CTR; + Uint16 XINT2CTR; + Uint16 rsvd[5]; + Uint16 XNMICTR; +}; + +// +// External Interrupt References & Function Declarations +// +extern volatile struct XINTRUPT_REGS XIntruptRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of file +// + diff --git a/F28335/DSP2833x_Xintf.h b/F28335/DSP2833x_Xintf.h new file mode 100644 index 0000000..1ebbf9a --- /dev/null +++ b/F28335/DSP2833x_Xintf.h @@ -0,0 +1,123 @@ +//########################################################################### +// +// FILE: DSP2833x_Xintf.h +// +// TITLE: DSP2833x Device External Interface Register Definitions. +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP2833x_XINTF_H +#define DSP2833x_XINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// XINTF timing register bit definitions +// +struct XTIMING_BITS { // bits description + Uint16 XWRTRAIL:2; // 1:0 Write access trail timing + Uint16 XWRACTIVE:3; // 4:2 Write access active timing + Uint16 XWRLEAD:2; // 6:5 Write access lead timing + Uint16 XRDTRAIL:2; // 8:7 Read access trail timing + Uint16 XRDACTIVE:3; // 11:9 Read access active timing + Uint16 XRDLEAD:2; // 13:12 Read access lead timing + Uint16 USEREADY:1; // 14 Extend access using HW waitstates + Uint16 READYMODE:1; // 15 Ready mode + Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b + Uint16 rsvd1:4; // 21:18 reserved + Uint16 X2TIMING:1; // 22 Double lead/active/trail timing + Uint16 rsvd3:9; // 31:23 reserved +}; + +union XTIMING_REG { + Uint32 all; + struct XTIMING_BITS bit; +}; + +// +// XINTF control register bit definitions +// +struct XINTCNF2_BITS { // bits description + Uint16 WRBUFF:2; // 1:0 Write buffer depth + Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK + Uint16 CLKOFF:1; // 3 Disable XCLKOUT + Uint16 rsvd1:2; // 5:4 reserved + Uint16 WLEVEL:2; // 7:6 Current level of the write buffer + Uint16 rsvd2:1; // 8 reserved + Uint16 HOLD:1; // 9 Hold enable/disable + Uint16 HOLDS:1; // 10 Current state of HOLDn input + Uint16 HOLDAS:1; // 11 Current state of HOLDAn output + Uint16 rsvd3:4; // 15:12 reserved + Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK + Uint16 rsvd4:13; // 31:19 reserved +}; + +union XINTCNF2_REG { + Uint32 all; + struct XINTCNF2_BITS bit; +}; + +// +// XINTF bank switching register bit definitions +// +struct XBANK_BITS { // bits description + Uint16 BANK:3; // 2:0 Zone for which banking is enabled + Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add + Uint16 rsvd:10; // 15:6 reserved +}; + +union XBANK_REG { + Uint16 all; + struct XBANK_BITS bit; +}; + +struct XRESET_BITS { + Uint16 XHARDRESET:1; + Uint16 rsvd1:15; +}; + +union XRESET_REG { + Uint16 all; + struct XRESET_BITS bit; +}; + +// +// XINTF Register File +// +struct XINTF_REGS { + union XTIMING_REG XTIMING0; + Uint32 rsvd1[5]; + union XTIMING_REG XTIMING6; + union XTIMING_REG XTIMING7; + Uint32 rsvd2[2]; + union XINTCNF2_REG XINTCNF2; + Uint32 rsvd3; + union XBANK_REG XBANK; + Uint16 rsvd4; + Uint16 XREVISION; + Uint16 rsvd5[2]; + union XRESET_REG XRESET; +}; + +// +// XINTF External References & Function Declarations +// +extern volatile struct XINTF_REGS XintfRegs; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of DSP2833x_XINTF_H definition + +// +// End of File +// + diff --git a/F28335/DSP28x_Project.h b/F28335/DSP28x_Project.h new file mode 100644 index 0000000..10a894e --- /dev/null +++ b/F28335/DSP28x_Project.h @@ -0,0 +1,22 @@ + +//########################################################################### +// +// FILE: DSP28x_Project.h +// +// TITLE: DSP28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $ +// $Release Date: November 1, 2016 $ +// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated - +// http://www.ti.com/ ALL RIGHTS RESERVED $ +//########################################################################### + +#ifndef DSP28x_PROJECT_H +#define DSP28x_PROJECT_H + +#include "F28335/DSP2833x_Device.h" // DSP2833x Headerfile Include File +#include "F28335/DSP2833x_Examples.h" // DSP2833x Examples Include File + +#endif // end of DSP28x_PROJECT_H definition + diff --git a/F28335/Flash2833x_API_Config.h b/F28335/Flash2833x_API_Config.h new file mode 100644 index 0000000..5cfc9de --- /dev/null +++ b/F28335/Flash2833x_API_Config.h @@ -0,0 +1,80 @@ +// TI File $Revision: /main/2 $ +// Checkin $Date: June 22, 2007 13:11:24 $ +//########################################################################### +// +// FILE: Flash2833x_API_Config.h +// +// TITLE: F2833x Flash Algo's - User Settings +// +// NOTE: This file contains user defined settings that +// are used by the F2833x Flash APIs. +// +//########################################################################### +// $TI Release:$ +// $Release Date:$ +//########################################################################### + +#ifndef FLASH2833X_API_CONFIG_H +#define FLASH2833X_API_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +// Variables that can be configured by the user. + +/*----------------------------------------------------------------------------- + 1. Specify the device. + Define the device to be programmed as "1" (no quotes). + Define all other devices as "0" (no quotes). +-----------------------------------------------------------------------------*/ + +#define FLASH_F28335 1 +#define FLASH_F28334 0 +#define FLASH_F28332 0 + +/*----------------------------------------------------------------------------- + 2. Specify the clock rate of the CPU (SYSCLKOUT) in nS. + + Take into account the input clock frequency and the PLL multiplier + that your application will use. + + Use one of the values provided, or define your own. + The trailing L is required tells the compiler to treat + the number as a 64-bit value. + + Only one statement should be uncommented. + + Example: CLKIN is a 30MHz crystal. + + If the application will set PLLCR = 0xA then the CPU clock + will be 150Mhz (SYSCLKOUT = 150MHz). + + In this case, the CPU_RATE will be 6.667L + Uncomment the line: #define CPU_RATE 6.667L +-----------------------------------------------------------------------------*/ + +#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) + +//---------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +// **** DO NOT modify the code below this line **** +//----------------------------------------------------------------------------- +#define SCALE_FACTOR 1048576.0L*( (200L/CPU_RATE) ) // IQ20 + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // -- end FLASH2833X_API_CONFIG_H diff --git a/F28335/Flash2833x_API_Library.h b/F28335/Flash2833x_API_Library.h new file mode 100644 index 0000000..ace1793 --- /dev/null +++ b/F28335/Flash2833x_API_Library.h @@ -0,0 +1,272 @@ +// TI File $Revision: /main/3 $ +// Checkin $Date: February 5, 2008 11:10:02 $ +//########################################################################### +// +// FILE: Flash2833x_API_Library.h +// +// TITLE: F2833x Flash Algo's main include file +// +// DESCRIPTION: +// +// This file should be included in any project that uses any of the +// the F2833x flash APIs. +// +//########################################################################### +// $TI Release:$ +// $Release Date:$ +//########################################################################### + +#ifndef FLASH2833X_API_LIBRARY_H +#define FLASH2833X_API_LIBRARY_H + +#include "F28335/Flash2833x_API_Config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + + +/*--------------------------------------------------------------------------- + 28x Datatypes + + For Portability, User Is Recommended To Use Following Data Type Size + Definitions For 16/32/64-Bit Signed/Unsigned Integers and floating point + variables: +---------------------------------------------------------------------------*/ + +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +/*--------------------------------------------------------------------------- + API Status Messages + + The following status values are returned from the API to the calling + program. These can be used to determine if the API function passed + or failed. +---------------------------------------------------------------------------*/ + // Operation passed, no errors were flagged +#define STATUS_SUCCESS 0 + +// The CSM is preventing the function from performing its operation +#define STATUS_FAIL_CSM_LOCKED 10 + +// Device REVID does not match that required by the API +#define STATUS_FAIL_REVID_INVALID 11 + +// Invalid address passed to the API +#define STATUS_FAIL_ADDR_INVALID 12 + +// Incorrect PARTID +// For example the F2806 API was used on a F2808 device. +#define STATUS_FAIL_INCORRECT_PARTID 13 + +// API/Silicon missmatch. An old version of the +// API is being used on silicon it is not valid for +// Please update to the latest API. +#define STATUS_FAIL_API_SILICON_MISMATCH 14 + +// ---- Erase Specific errors ---- +#define STATUS_FAIL_NO_SECTOR_SPECIFIED 20 +#define STATUS_FAIL_PRECONDITION 21 +#define STATUS_FAIL_ERASE 22 +#define STATUS_FAIL_COMPACT 23 +#define STATUS_FAIL_PRECOMPACT 24 + +// ---- Program Specific errors ---- +#define STATUS_FAIL_PROGRAM 30 +#define STATUS_FAIL_ZERO_BIT_ERROR 31 + +// ---- Verify Specific errors ---- +#define STATUS_FAIL_VERIFY 40 + +// Busy is set by each API function before it determines +// a pass or fail condition for that operation. +// The calling function will will not receive this +// status condition back from the API +#define STATUS_BUSY 999 + +/*--------------------------------------------------------------------------- + Flash sector mask definitions + + The following macros can be used to form a mask specifying which sectors + will be erased by the erase API function. + + Bit0 = Sector A + Bit1 = Sector B + Bit2 = Sector C + Bit3 = Sector D + Bit4 = Sector E + Bit5 = Sector F + Bit6 = Sector G + Bit7 = Sector H +---------------------------------------------------------------------------*/ + +#define SECTORA (Uint16)0x0001 +#define SECTORB (Uint16)0x0002 +#define SECTORC (Uint16)0x0004 +#define SECTORD (Uint16)0x0008 +#define SECTORE (Uint16)0x0010 +#define SECTORF (Uint16)0x0020 +#define SECTORG (Uint16)0x0040 +#define SECTORH (Uint16)0x0080 + + +#if FLASH_F28335 +// All sectors on an F28335 - Sectors A - H +#define SECTOR_F28335 (SECTORA|SECTORB|SECTORC|\ + SECTORD|SECTORE|SECTORF|\ + SECTORG|SECTORH) +#endif // -- end FLASH_F28335 + +#if FLASH_F28334 +// All sectors on an F28334 - Sectors A - H +#define SECTOR_F28334 (SECTORA|SECTORB|SECTORC|\ + SECTORD|SECTORE|SECTORF|\ + SECTORG|SECTORH) +#endif // -- end FLASH_F28334 + +#if FLASH_F28332 +// All sectors on an F28332 - Sectors A - D +#define SECTOR_F28332 (SECTORA|SECTORB|SECTORC|\ + SECTORD) +#endif // -- end FLASH_F28332 + + +/*--------------------------------------------------------------------------- + API Status Structure + + This structure is used to pass debug data back to the calling routine. + Note that the Erase API function has 3 parts: precondition, erase and + and compaction. Erase and compaction failures will not populate + the expected and actual data fields. +---------------------------------------------------------------------------*/ + +typedef struct { + Uint32 FirstFailAddr; + Uint16 ExpectedData; + Uint16 ActualData; +}FLASH_ST; + +/*--------------------------------------------------------------------------- + Interface Function prototypes + + For each 28x Flash API library, the function names are of the form: + Flash_() + + Where is the device: ie 2808, 2806, 2801 + is the operation such as Erase, Program... + + For portability for users who may move between the F2808, F2806 and + F2801, the following macro definitions are supplied. + + Using these macro definitions, the user can use instead make a generic + call: Flash_ and the macro will map the call to the proper + device function + + Note except for the toggle test function, all of the function prototypes + are compatible with F281x devices as well. +---------------------------------------------------------------------------*/ + +#if FLASH_F28335 +#define Flash_Erase(a,b) Flash28335_Erase(a,b) +#define Flash_Program(a,b,c,d) Flash28335_Program(a,b,c,d) +#define Flash_Verify(a,b,c,d) Flash28335_Verify(a,b,c,d) +#define Flash_ToggleTest(a,b) Flash28335_ToggleTest(a,b) +#define Flash_DepRecover() Flash28335_DepRecover() +#define Flash_APIVersionHex() Flash28335_APIVersionHex() +#define Flash_APIVersion() Flash28335_APIVersion() +#endif + +#if FLASH_F28334 +#define Flash_Erase(a,b) Flash28334_Erase(a,b) +#define Flash_Program(a,b,c,d) Flash28334_Program(a,b,c,d) +#define Flash_Verify(a,b,c,d) Flash28334_Verify(a,b,c,d) +#define Flash_ToggleTest(a,b) Flash28334_ToggleTest(a,b) +#define Flash_DepRecover() Flash28334_DepRecover() +#define Flash_APIVersionHex() Flash28334_APIVersionHex() +#define Flash_APIVersion() Flash28334_APIVersion() +#endif + +#if FLASH_F28332 +#define Flash_Erase(a,b) Flash28332_Erase(a,b) +#define Flash_Program(a,b,c,d) Flash28332_Program(a,b,c,d) +#define Flash_Verify(a,b,c,d) Flash28332_Verify(a,b,c,d) +#define Flash_ToggleTest(a,b) Flash28332_ToggleTest(a,b) +#define Flash_DepRecover() Flash28332_DepRecover() +#define Flash_APIVersionHex() Flash28332_APIVersionHex() +#define Flash_APIVersion() Flash28332_APIVersion() +#endif + +extern Uint16 Flash_Erase(Uint16 SectorMask, FLASH_ST *FEraseStat); +extern Uint16 Flash_Program(Uint16 *FlashAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FProgStatus); +extern Uint16 Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FVerifyStat); +extern void Flash_ToggleTest(volatile Uint32 *ToggleReg, Uint32 Mask); +extern Uint16 Flash_DepRecover(); +extern float32 Flash_APIVersion(); +extern Uint16 Flash_APIVersionHex(); + +/*--------------------------------------------------------------------------- + Frequency Scale factor: + The calling program must provide this global parameter used + for frequency scaling the algo's. +----------------------------------------------------------------------------*/ + +extern Uint32 Flash_CPUScaleFactor; + +/*--------------------------------------------------------------------------- + Callback Function Pointer: + A callback function can be specified. This function will be called + at safe times during erase, program and verify. This function can + then be used to service an external watchdog or send a communications + packet. + + Note: + THE FLASH AND OTP ARE NOT AVAILABLE DURING THIS FUNCTION CALL. + THE FLASH/OTP CANNOT BE READ NOR CAN CODE EXECUTE FROM IT DURING THIS CALL + DO NOT CALL ANY OF THE THE FLASH API FUNCTIONS DURING THIS CALL +----------------------------------------------------------------------------*/ +extern void (*Flash_CallbackPtr) (void); + +/*--------------------------------------------------------------------------- + API load/run symbols: + These symbols are defined by the linker during the link. Refer to the + Flash28_API section in the example .cmd file: + + Flash28_API: + { + Flash28335_API_Library.lib(.econst) + Flash28335_API_Library.lib(.text) + } LOAD = FLASH, + RUN = SARAM, + LOAD_START(_Flash28_API_LoadStart), + LOAD_END(_Flash28_API_LoadEnd), + RUN_START(_Flash28_API_RunStart), + PAGE = 0 + + These are used to copy the flash API from flash to SARAM + +----------------------------------------------------------------------------*/ + +extern Uint16 Flash28_API_LoadStart; +extern Uint16 Flash28_API_LoadEnd; +extern Uint16 Flash28_API_RunStart; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // -- end FLASH2833x_API_LIBRARY_H + +// --------- END OF FILE ---------------------------------- + diff --git a/Periphery.cpp b/Periphery.cpp index 74a9bcb..80de701 100644 --- a/Periphery.cpp +++ b/Periphery.cpp @@ -1,42 +1,48 @@ -#include "DSP2833x_Device.h" -#include "DSP28x_Project.h" -#include "Protocol/CAN.h" -#include "Protocol/CAN_data.h" -#include "Protocol/DigitalIO.h" -#include "Protocol/MemoryMap.h" #include "Periphery.h" Periphery::Periphery() : - _canb(canSpace::CANA), + _cana(canSpace::CANA), _digitalIO(), _zone6_ptr(reinterpret_cast(0x100000)), - _modbusSettingsMsg(), - _modbusInit(false) + _scib(ScibRegs), + _modbusInitFlag(false), + _modbusRegCounter(0), + modbusRTU(CpuTimer2, _scib) { _softVersion.DSP = 202; _softVersion.CPLD = 0; + + test_hmi_float_reg_400_test = 0; + test_hmi_float_reg_401_test = 0; + test_hmi_float_reg_402_test = 0; + test_hmi_float_reg_403_test = 0; + test_hmi_float_reg_404_test = 0; } void Periphery::config(){ //--------------------------------------Init CAN interface---------------------------------------------------------- - _canb.initGpio(); - _canb.config(); + _cana.initGpio(); + _cana.config(); // Data Frame MBOX - _canb.configRxMBox(canSpace::MODBUS_SETTINGS_MBOX, canSpace::MsgID(0x0), canSpace::MsgCtrlReg(0x6)); // Modbus settings - // _canb.configTxMBox(canSpace::MODBUS_DATA_COMM_TO_CPU_MBOX, canSpace::MsgID(0x29), canSpace::MsgCtrlReg(0x26)); // Send Modbus data to CPU - // _canb.configRxMBox(canSpace::MODBUS_DATA_CPU_TO_COMM_MBOX, canSpace::MsgID(0x28), canSpace::MsgCtrlReg(0x6)); // Receive Modbus data from CPU - _canb.configTxMBox(canSpace::DIGITAL_INPUT_MBOX, canSpace::MsgID(0x30), canSpace::MsgCtrlReg(0x2)); // Receive DI - _canb.configRxMBox(canSpace::DIGITAL_OUTPUT_MBOX, canSpace::MsgID(0x31), canSpace::MsgCtrlReg(0x2)); // Send DO + _cana.configRxMBox(canSpace::MODBUS_SETTINGS_MBOX, canSpace::MsgID(0x0), canSpace::MsgCtrlReg(0x6)); // Modbus settings + _cana.configTxMBox(canSpace::MODBUS_DATA_COMM_TO_CPU_MBOX, canSpace::MsgID(0x29), canSpace::MsgCtrlReg(0x28)); // Send Modbus data to CPU + _cana.configRxMBox(canSpace::MODBUS_DATA_CPU_TO_COMM_MBOX, canSpace::MsgID(0x28), canSpace::MsgCtrlReg(0x8)); // Receive Modbus data from CPU + _cana.configTxMBox(canSpace::DIGITAL_INPUT_MBOX, canSpace::MsgID(0x30), canSpace::MsgCtrlReg(0x2)); // Receive DI + _cana.configRxMBox(canSpace::DIGITAL_OUTPUT_MBOX, canSpace::MsgID(0x31), canSpace::MsgCtrlReg(0x2)); // Send DO // Remote frame MBOX - _canb.configTxMBox(canSpace::COMM_VERSION_MBOX, canSpace::MsgID(0x1, false, true), canSpace::MsgCtrlReg(0)); + // _cana.configRxMBox(canSpace::MODBUS_SETTINGS_MBOX, canSpace::MsgID(0x0), canSpace::MsgCtrlReg(0x10)); + _cana.configTxMBox(canSpace::COMM_VERSION_MBOX, canSpace::MsgID(0x1, false, true), canSpace::MsgCtrlReg(0x4)); + + _cana.enableTimeOutControl(canSpace::MODBUS_SETTINGS_MBOX); + _cana.setTimeOutValue(canSpace::MODBUS_SETTINGS_MBOX, 1000); // Interrupts - _canb.configSystemIsr(canSpace::I0EN_ENABLE | - canSpace::EPIM_ENABLE | canSpace::WLIM_ENABLE | canSpace::AAIM_ENABLE); + _cana.configSystemIsr(canSpace::I0EN_ENABLE | + canSpace::EPIM_ENABLE | canSpace::WLIM_ENABLE | canSpace::AAIM_ENABLE); //--------------------------------------Init XINTF interface---------------------------------------------------------- @@ -47,6 +53,23 @@ void Periphery::config(){ _digitalIO.setup(_zone6_ptr); _digitalIO.setMemoryOffset(interface::DISCRETE_DATA_OFFSET); + + //---------------------------------------Init SCI interface---------------------------------------------------------- + DSP28335::SCISetup sciBSetup; + sciBSetup.config.baudrate = SCIB_BAUDRATE_DEFAULT; + sciBSetup.config.parity = SCIB_PARITY_DEFAULT; + sciBSetup.config.stopbits = SCIB_STOPBITS_DEFAULT; + sciBSetup.config.lenght = SCIB_LENGHT_DEFAULT; + sciBSetup.gpio_setup = SCIB_GPIO_SETUP_DEFAULT; + + _scib.setup(sciBSetup); + + + //------------------------------------------Init Modbus---------------------------------------------------------- + MODBUSRTU::modbusSetup.gpio_re_de_setup = &DSP28335::GPIO::gpio_scib_re_de_setup; + MODBUSRTU::modbusSetup.gpio_driver_enable = &DSP28335::GPIO::gpio_scib_re_de_set; + MODBUSRTU::modbusSetup.gpio_receiver_enable = &DSP28335::GPIO::gpio_scib_re_de_clear; + modbusRTU.setup(MODBUSRTU::modbusSetup); } @@ -58,32 +81,136 @@ Uint16 Periphery::getVersionFPGA(){ void Periphery::updateVersionFPGA(){ - _softVersion.CPLD = getVersionFPGA() & 0x3FF; // no more than 1023 (9.9.9) should be limit + _softVersion.CPLD = getVersionFPGA() & 0x3FF; // no more than 1023. (9.9.9) should be limit _message.mdl.word.LOW_WORD = _softVersion.DSP; _message.mdl.word.HI_WORD = _softVersion.CPLD; - _canb.updateTXMessage(canSpace::COMM_VERSION_MBOX, _message); + _cana.updateTXMessage(canSpace::COMM_VERSION_MBOX, _message); +} + + +void Periphery::initModbusTable(){ + modbusRTU.setInputRegsAddr(400); + modbusRTU.setOutputRegsAddr(400); + + modbusRTU.addInputReg(0, test_hmi_float_reg_400_test); + modbusRTU.addInputReg(1, test_hmi_float_reg_401_test); + modbusRTU.addInputReg(2, test_hmi_float_reg_402_test); + modbusRTU.addInputReg(3, test_hmi_float_reg_403_test); + modbusRTU.addInputReg(4, test_hmi_float_reg_404_test); + + modbusRTU.addOutputReg(0, test_hmi_float_reg_400_test); + modbusRTU.addOutputReg(1, test_hmi_float_reg_401_test); + modbusRTU.addOutputReg(2, test_hmi_float_reg_402_test); + modbusRTU.addOutputReg(3, test_hmi_float_reg_403_test); + modbusRTU.addOutputReg(4, test_hmi_float_reg_404_test); +} + + +void Periphery::receiveModbusParameters(){ + if (_cana.isNewMessage(canSpace::MODBUS_SETTINGS_MBOX)) { + _cana.receiveMsg(canSpace::MODBUS_SETTINGS_MBOX, _message); + + MODBUSRTU::modbusConfiguration.node_id = _message.mdl.byte.BYTE0; + MODBUSRTU::modbusConfiguration.config.lenght = static_cast(_message.mdl.byte.BYTE1); + MODBUSRTU::modbusConfiguration.config.baudrate = static_cast(_message.mdl.word.LOW_WORD); + MODBUSRTU::modbusConfiguration.config.parity = static_cast(_message.mdh.byte.BYTE4); + MODBUSRTU::modbusConfiguration.config.stopbits = static_cast(_message.mdh.byte.BYTE5); + + modbusRTU.configure(MODBUSRTU::modbusConfiguration); + _modbusRegCounter = 0; + } +} + + +void Periphery::getModbusConfiguration(){ + _cana.resetTimeStampCounter(); + _cana.clearTimeOutFlag(canSpace::MODBUS_SETTINGS_MBOX); + bool requestIsSent = false; + + while(!_cana.isNewMessage(canSpace::MODBUS_SETTINGS_MBOX)){ + if(_cana.isTimeOut(canSpace::MODBUS_SETTINGS_MBOX)){ + if (!requestIsSent) { + _cana.resetTimeStampCounter(); + _cana.clearTimeOutFlag(canSpace::MODBUS_SETTINGS_MBOX); + + _message.mdl.word.LOW_WORD = _softVersion.DSP; + _message.mdl.word.HI_WORD = _softVersion.CPLD; + _cana.transmitMsg(canSpace::COMM_VERSION_MBOX, _message); + + requestIsSent = true; + } + else{ + _cana.clearTimeOutFlag(canSpace::MODBUS_SETTINGS_MBOX); + _cana.disableTimeOutControl(canSpace::MODBUS_SETTINGS_MBOX); + _error = true; + return; + } + } + } + + _cana.receiveMsg(canSpace::MODBUS_SETTINGS_MBOX, _message); + MODBUSRTU::modbusConfiguration.node_id = _message.mdl.byte.BYTE0; + MODBUSRTU::modbusConfiguration.config.lenght = static_cast(_message.mdl.byte.BYTE1); + MODBUSRTU::modbusConfiguration.config.baudrate = static_cast(_message.mdl.word.LOW_WORD); + MODBUSRTU::modbusConfiguration.config.parity = static_cast(_message.mdh.byte.BYTE4); + MODBUSRTU::modbusConfiguration.config.stopbits = static_cast(_message.mdh.byte.BYTE5); + + modbusRTU.configure(MODBUSRTU::modbusConfiguration); + _modbusRegCounter = 0; } void Periphery::processDigitalInput(){ Uint16 data = 0; _digitalIO.readDigitalIO(data); - _canb.transmitMsg(canSpace::DIGITAL_INPUT_MBOX, (data)); + _cana.transmitMsg(canSpace::DIGITAL_INPUT_MBOX, (data)); } void Periphery::processDigitalOutput(){ - if(_canb.isNewMessage(canSpace::DIGITAL_OUTPUT_MBOX)){ - _canb.receiveMsg(canSpace::DIGITAL_OUTPUT_MBOX, _message); + if(_cana.isNewMessage(canSpace::DIGITAL_OUTPUT_MBOX)){ + _cana.receiveMsg(canSpace::DIGITAL_OUTPUT_MBOX, _message); Uint16 data = _message.mdl.word.LOW_WORD; _digitalIO.writeDigitalIO(data); } } -void Periphery::initExternalModbus(){ - if (!_modbusInit && (_canb.isNewMessage(canSpace::MODBUS_SETTINGS_MBOX))) { - _canb.receiveMsg(canSpace::MODBUS_SETTINGS_MBOX, _modbusSettingsMsg); - _modbusInit = true; // TODO modbus init function must be here +void Periphery::sendModbusDataToCPU(){ + _message.mdl.all = 0; // TODO delete maybe? + _message.mdh.all = 0; + + WEINBUS::WeinbusTableRegister reg; + reg = modbusRTU.dataHandler.outputRegisters.get_register_cursor(_modbusRegCounter); + + if(modbusRTU.dataHandler.outputRegisters.address_range(reg.get_address())){ + _message.mdl.all = reg.get_address(); + reg.read(_message.mdh.all); + + _modbusRegCounter++; + } + else { + _modbusRegCounter = 0; + reg = modbusRTU.dataHandler.outputRegisters.get_register_cursor(_modbusRegCounter); + + _message.mdl.all = reg.get_address(); + reg.read(_message.mdh.all); + + _modbusRegCounter++; + } + + _cana.transmitMsg(canSpace::MODBUS_DATA_COMM_TO_CPU_MBOX, _message); +} + + +void Periphery::receiveCpuModbusData(){ + if (_cana.isNewMessage(canSpace::MODBUS_DATA_CPU_TO_COMM_MBOX)) { + _cana.receiveMsg(canSpace::MODBUS_DATA_CPU_TO_COMM_MBOX, _message); + + WEINBUS::WeinbusTableRegister reg; + + uint32_t addr = _message.mdl.all; + reg = modbusRTU.dataHandler.inputRegisters.get_register_cursor(addr - modbusRTU.dataHandler.inputRegisters.get_start_address()); + reg.write_data(_message.mdh.all); } } diff --git a/Periphery.h b/Periphery.h index e592ea3..0b75f31 100644 --- a/Periphery.h +++ b/Periphery.h @@ -1,5 +1,7 @@ #pragma once +#include + #include "DSP28x_Project.h" #include "DSP2833x_Device.h" #include "Protocol/CAN.h" @@ -7,6 +9,11 @@ #include "Protocol/DigitalIO.h" #include "Protocol/MemoryMap.h" +#include "DSP28335/SCIBase.h" +#include "DSP28335/SCIB.h" + +#include "ModbusRTU.h" + struct SoftwareVersion{ Uint16 DSP; @@ -19,22 +26,39 @@ public: void config(); Uint16 getVersionFPGA(); void updateVersionFPGA(); + + void receiveModbusParameters(); + void getModbusConfiguration(); + void initModbusTable(); // TODO Must be outside periphery! + void processDigitalInput(); void processDigitalOutput(); - void initExternalModbus(); - void processExternalModbus(); // TODO - void processCPUModbus(); // TODO + + void sendModbusDataToCPU(); + void receiveCpuModbusData(); private: - canSpace::CAN _canb; + canSpace::CAN _cana; interface::DigitalIO _digitalIO; Uint16* _zone6_ptr; + DSP28335::SCIB _scib; + SoftwareVersion _softVersion; - canSpace::CANMessage _modbusSettingsMsg; canSpace::CANMessage _message; - bool _modbusInit; + bool _modbusInitFlag; + bool _error; + uint16_t _modbusRegCounter; + + float test_hmi_float_reg_400_test; + float test_hmi_float_reg_401_test; + float test_hmi_float_reg_402_test; + float test_hmi_float_reg_403_test; + float test_hmi_float_reg_404_test; - Uint16 tempIn; - Uint16 tempOut; +public: + MODBUSRTU::ModbusRTU modbusRTU; }; + + + diff --git a/Protocol/CAN.cpp b/Protocol/CAN.cpp index a3c3b18..7c68c06 100644 --- a/Protocol/CAN.cpp +++ b/Protocol/CAN.cpp @@ -253,7 +253,7 @@ bool CAN::isNewMessage(Uint16 boxNumber){ void CAN::resetTimeStampCounter(){ EALLOW; - ECanbRegs.CANTSC = 0; + p_CanRegs_->CANTSC = 0; EDIS; } diff --git a/Protocol/DigitalIO.cpp b/Protocol/DigitalIO.cpp index 24d7147..37e3a63 100644 --- a/Protocol/DigitalIO.cpp +++ b/Protocol/DigitalIO.cpp @@ -18,7 +18,7 @@ void DigitalIO::setMemoryOffset(Uint16 offset){ void DigitalIO::readDigitalIO(Uint16& data){ - asm(" NOP"); + asm(" NOP"); // TODO Add normal NOP asm(" NOP"); asm(" NOP"); data = *m_pointer; diff --git a/RUDRIVEFRAMEWORK/DataType.h b/RUDRIVEFRAMEWORK/DataType.h new file mode 100644 index 0000000..bb0d6d5 --- /dev/null +++ b/RUDRIVEFRAMEWORK/DataType.h @@ -0,0 +1,174 @@ +/* + * DataType.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include +#include + +#ifndef SYSTEM_DATATYPE_H_ +#define SYSTEM_DATATYPE_H_ + + + +typedef void (*pGPIO_FUNCTION)(); +typedef void (*pGPIO_FUNCTION_UINT)(uint16_t& data); + + + +struct Register16BitField +{ + uint16_t b00: 1; + uint16_t b01: 1; + uint16_t b02: 1; + uint16_t b03: 1; + uint16_t b04: 1; + uint16_t b05: 1; + uint16_t b06: 1; + uint16_t b07: 1; + uint16_t b08: 1; + uint16_t b09: 1; + uint16_t b10: 1; + uint16_t b11: 1; + uint16_t b12: 1; + uint16_t b13: 1; + uint16_t b14: 1; + uint16_t b15: 1; +};//Register16BitField + +struct Register16ByteField +{ + uint16_t low :8; + uint16_t high :8; +};//Register16ByteField + +struct Register16WordField +{ + uint16_t wL :16; +};//Register16WordField + + +union Register16 +{ + uint16_t all; + Register16BitField bit; + Register16ByteField byte; +};//Register16 + + +struct Register32BitField +{ + uint16_t b00: 1; + uint16_t b01: 1; + uint16_t b02: 1; + uint16_t b03: 1; + uint16_t b04: 1; + uint16_t b05: 1; + uint16_t b06: 1; + uint16_t b07: 1; + uint16_t b08: 1; + uint16_t b09: 1; + uint16_t b10: 1; + uint16_t b11: 1; + uint16_t b12: 1; + uint16_t b13: 1; + uint16_t b14: 1; + uint16_t b15: 1; + uint16_t b16: 1; + uint16_t b17: 1; + uint16_t b18: 1; + uint16_t b19: 1; + uint16_t b20: 1; + uint16_t b21: 1; + uint16_t b22: 1; + uint16_t b23: 1; + uint16_t b24: 1; + uint16_t b25: 1; + uint16_t b26: 1; + uint16_t b27: 1; + uint16_t b28: 1; + uint16_t b29: 1; + uint16_t b30: 1; + uint16_t b31: 1; +};//Register32BitField + + +struct Register32ByteField +{ + uint16_t bt0 :8; + uint16_t bt1 :8; + uint16_t bt2 :8; + uint16_t bt3 :8; +};//Register32ByteField + +struct Register32WordField +{ + uint16_t wL :16; + uint16_t wH :16; +};//Register32WordField + + +union UIntRegister32 +{ + uint32_t all; + Register32BitField bit; + Register32ByteField byte; + Register32WordField word; +};//UIntRegister32 + + + +struct BoolRegisterBitField +{ + uint16_t b0 :1; +};//BoolRegisterBitField + +union BoolRegister +{ + uint16_t all; + BoolRegisterBitField boolbit; + BoolRegister(): + all(0) + {} +};//BoolRegister + + +struct AnalogFaultRegister16BitField +{ + uint16_t a0: 1; + uint16_t a1: 1; + uint16_t a2: 1; +};//AnalogFaultRegister16BitField + +union AnalogFaultRegister +{ + uint16_t all; + AnalogFaultRegister16BitField bit; + AnalogFaultRegister(): + all(0) + {} +};//AnalogFaultRegister + + +struct HardFaultRegister16BitField +{ + uint16_t h0: 1; + uint16_t h1: 1; + uint16_t h2: 1; +};//HardFaultRegister16BitField + +union HardFaultRegister +{ + uint16_t all; + HardFaultRegister16BitField bit; + HardFaultRegister(): + all(0) + {} +};//HardFaultRegister + + + + +#endif /* SYSTEM_DATATYPE_H_ */ diff --git a/RUDRIVEFRAMEWORK/DataTypesDefinitions.h b/RUDRIVEFRAMEWORK/DataTypesDefinitions.h new file mode 100644 index 0000000..fa3f2ca --- /dev/null +++ b/RUDRIVEFRAMEWORK/DataTypesDefinitions.h @@ -0,0 +1,43 @@ +/* + * DataTypesDefinitions.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + + + +#include +#include + +#include "F28335/DSP2833x_Device.h" + + +#ifndef SYSCTRL_DATATYPESDEFINITIONS_H_ +#define SYSCTRL_DATATYPESDEFINITIONS_H_ + + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifndef DSP28_BYTE_DATA_TYPES +#define DSP28_BYTE_DATA_TYPES +typedef signed char int8; +typedef unsigned char Uint8; +#endif + + +#ifndef STD_BYTE_DATA_TYPES +#define STD_BYTE_DATA_TYPES +typedef signed char int8_t; +typedef unsigned char uint8_t; +#endif + + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif /* SYSCTRL_DATATYPESDEFINITIONS_H_ */ diff --git a/RUDRIVEFRAMEWORK/SystemDefinitions.h b/RUDRIVEFRAMEWORK/SystemDefinitions.h new file mode 100644 index 0000000..2cf03af --- /dev/null +++ b/RUDRIVEFRAMEWORK/SystemDefinitions.h @@ -0,0 +1,48 @@ +/* + * SystemDefinitions.h + * + * Author: Aleksey Gerasimenko + * gerasimenko.aleksey.n@gmail.com + */ + +#include +#include + +#ifndef SYSTEM_SYSTEMDEFINITIONS_H_ +#define SYSTEM_SYSTEMDEFINITIONS_H_ + + +#ifndef NOP +#define NOP asm(" NOP") +#endif + + +#ifndef FP_PI +#define FP_PI (float)3.14159265359 // Pi +#endif + +#ifndef FP_2PI +#define FP_2PI (float)6.28318530718 // 2Pi +#endif + +#ifndef FP_DAMP_FACTOR +#define FP_DAMP_FACTOR 0.70710678118654752440 // 1/sqrt(2) +#endif + + +// +// Voltage PLL-ABC Parameters +// +#define PLLABC_FREQUENCY_NOMINAL (float)(2.0*FP_PI*50.0) +#define PLLABC_FREQUENCY_CUT (float)(2.0*FP_PI*10.0) +#define PLLABC_FILTER_TIME (float)(1.0/PLLABC_FREQUENCY_CUT) +#define PLLABC_CONTROLLER_GAIN (float)(PLLABC_FREQUENCY_CUT/2.0) +#define PLLABC_CONTROLLER_TIME (float)(4.0/PLLABC_FREQUENCY_CUT) + +#define PLLABC_FREQUENCY_LIMIT_HI PLLABC_FREQUENCY_CUT +#define PLLABC_FREQUENCY_LIMIT_LOW -PLLABC_FREQUENCY_CUT + + + + +#endif /* SYSTEM_SYSTEMDEFINITIONS_H_ */ diff --git a/System/ModbusTable.cpp b/System/ModbusTable.cpp new file mode 100644 index 0000000..9e2cd05 --- /dev/null +++ b/System/ModbusTable.cpp @@ -0,0 +1,24 @@ +#include "Periphery.h" +#include "SystemVars.h" + +namespace SYSCTRL { + + +void initModbusTable(Periphery& periphery){ + periphery.modbusRTU.setInputRegsAddr(400); + periphery.modbusRTU.setOutputRegsAddr(400); + + periphery.modbusRTU.addInputReg(0, test_float_reg); + periphery.modbusRTU.addInputReg(1, test_int16_reg); + periphery.modbusRTU.addInputReg(2, test_uint16_reg); + periphery.modbusRTU.addInputReg(3, test_int32_reg); + periphery.modbusRTU.addInputReg(4, test_uint32_reg); + + periphery.modbusRTU.addOutputReg(0, test_float_reg); + periphery.modbusRTU.addOutputReg(1, test_int16_reg); + periphery.modbusRTU.addOutputReg(2, test_uint16_reg); + periphery.modbusRTU.addOutputReg(3, test_int32_reg); + periphery.modbusRTU.addOutputReg(4, test_uint32_reg); +} + +} diff --git a/System/SystemContol.h b/System/SystemContol.h new file mode 100644 index 0000000..0fc1ec8 --- /dev/null +++ b/System/SystemContol.h @@ -0,0 +1,10 @@ +#pragma once + +#include "Periphery.h" +#include "System/SystemVars.h" + +namespace SYSCTRL { + + void initModbusTable(Periphery& periphery); + +} diff --git a/System/SystemVars.cpp b/System/SystemVars.cpp new file mode 100644 index 0000000..478d5e6 --- /dev/null +++ b/System/SystemVars.cpp @@ -0,0 +1,10 @@ +#include "System/SystemVars.h" + +namespace SYSCTRL { + + float test_float_reg = 0; + int16_t test_int16_reg = 0; + uint16_t test_uint16_reg = 0; + int32_t test_int32_reg = 0; + uint32_t test_uint32_reg = 0; +} diff --git a/System/SystemVars.h b/System/SystemVars.h new file mode 100644 index 0000000..803a908 --- /dev/null +++ b/System/SystemVars.h @@ -0,0 +1,12 @@ +#pragma once + +#include + +namespace SYSCTRL { + + extern float test_float_reg; + extern int16_t test_int16_reg; + extern uint16_t test_uint16_reg; + extern int32_t test_int32_reg; + extern uint32_t test_uint32_reg; +} diff --git a/main.cpp b/main.cpp index 896cd93..ef0766a 100644 --- a/main.cpp +++ b/main.cpp @@ -7,9 +7,14 @@ #include "DSP2833x_Device.h" #include "DSP28x_Project.h" // Device Headerfile and Examples Include File #include "DSP2833x_Examples.h" -#include "Protocol/CAN.h" -#include "Protocol/CAN_data.h" -#include "Protocol/DigitalIO.h" +// #include "Protocol/CAN.h" +// #include "Protocol/CAN_data.h" +// #include "Protocol/DigitalIO.h" +#include "Periphery.h" +#include "System/SystemContol.h" + +#include "DSP28335/SCIB.h" +#include "DSP28335/SCIBase.h" //Functions declarations @@ -20,29 +25,7 @@ interrupt void cpu_timer1_isr(void); interrupt void canb_isr(void); interrupt void canb_box_isr(void); -canSpace::CAN canTest(canSpace::CANB); - -interface::DigitalIO digitalIO; -interface::DigitalIODataRegister digitalInputReg; -interface::DigitalIODataRegister digitalOutputReg; - -// RX -canSpace::CANMessage DOMessage; -canSpace::CANMessage messageSettings; -canSpace::CANMessage MODBUS_CPU_COMM_Message; - -// TX -canSpace::CANMessage DIMessage; -canSpace::CANMessage MODBUS_COMM_CPU_Message; -canSpace::CANMessage SoftVersionMessage; -Uint32 array[25] = {0}; - -struct SoftwareVersion{ - Uint16 DSP; - Uint16 CPLD; -}; - -SoftwareVersion softVersion = { .DSP = 101, .CPLD = 202 }; +Periphery periphery; volatile Uint16 infCounter = 0; volatile Uint16 canISRcounter = 0; @@ -57,6 +40,7 @@ volatile bool sendRemote = false; Uint16 modbusInit = 0; int32 testVar = 0; +float test = 55; void main() { @@ -93,33 +77,16 @@ void main() PieCtrlRegs.PIEIER9.bit.INTx7 = 1; // from 5 to 8 PieCtrlRegs.PIEIER9.bit.INTx8 = 1; - canTest.initGpio(); - canTest.config(); - canTest.configTxMBox(canSpace::DIGITAL_INPUT_MBOX, canSpace::MsgID(0x30), canSpace::MsgCtrlReg(0x3)); - - DIMessage.dataLength = 3; - DIMessage.mdl.byte.BYTE0 = 0x11; - DIMessage.mdl.byte.BYTE1 = 0x22; - DIMessage.mdl.byte.BYTE2 = 0x33; - - MODBUS_COMM_CPU_Message.dataLength = 6; - MODBUS_COMM_CPU_Message.mdl.byte.BYTE0 = 0xA; - MODBUS_COMM_CPU_Message.mdl.byte.BYTE1 = 0xB; - MODBUS_COMM_CPU_Message.mdl.byte.BYTE2 = 0xC; - MODBUS_COMM_CPU_Message.mdl.byte.BYTE3 = 0xD; - MODBUS_COMM_CPU_Message.mdh.byte.BYTE4 = 0xE; - MODBUS_COMM_CPU_Message.mdh.byte.BYTE5 = 0xF; - - SoftVersionMessage.dataLength = 2; - SoftVersionMessage.mdl.byte.BYTE0 = softVersion.DSP; - SoftVersionMessage.mdl.byte.BYTE0 = softVersion.CPLD; - - digitalIO.setup((Uint16*)0x4000); + periphery.config(); + periphery.updateVersionFPGA(); + periphery.getModbusConfiguration(); + SYSCTRL::initModbusTable(periphery); // Enable global Interrupts and higher priority real-time debug events: EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM + CpuTimer0.RegsAddr->TCR.bit.TSS = 0; CpuTimer1.RegsAddr->TCR.bit.TSS = 0; @@ -135,19 +102,15 @@ void idle_loop() { infCounter++; - // ожидать получения данных при remote frame - // get cpld version with xintf here - // if (init){ - // init = false; - // // в main положить - // canTest.updateTXMessage(canSpace::COMM_VERSION_MBOX, SoftVersionMessage); - // } + periphery.receiveModbusParameters(); - // if (canTest.isNewMessage(canSpace::MODBUS_SETTINGS_MBOX)){ - // canTest.receiveMsg(canSpace::MODBUS_SETTINGS_MBOX, messageSettings); - // modbusInit++; - // } + // + // MODBUS RTU HMI Service + // + periphery.modbusRTU.execute(); + periphery.receiveCpuModbusData(); + }//end while }//end idle_loop() @@ -155,15 +118,8 @@ void idle_loop() interrupt void cpu_timer0_isr(void) { - CpuTimer0.InterruptCount++; - // if(canTest.isNewMessage()){ - // canTest.receiveMsg(canSpace::DIGITAL_OUTPUT_MBOX, DOMessage); - // canTest.receiveMsg(canSpace::MODBUS_DATA_CPU_TO_COMM_MBOX, MODBUS_CPU_COMM_Message); - // testCounter++; - // } - - // digitalOutputReg.all = digitalOutputReg.all; - // digitalIO.writeDigitalIO(digitalOutputReg.all); + periphery.processDigitalOutput(); + periphery.sendModbusDataToCPU(); PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; }//end @@ -172,10 +128,7 @@ interrupt void cpu_timer0_isr(void) interrupt void cpu_timer1_isr(){ CpuTimer1.InterruptCount++; - // digitalIO.readDigitalIO(DIMessage.mdl.all); - // digitalIO.readDigitalIO(digitalInputReg.all); - // DIMessage.mdl.all = digitalInputReg.all; - canTest.transmitMsg(canSpace::DIGITAL_INPUT_MBOX, DIMessage); + periphery.processDigitalInput(); } diff --git a/main2.cpp b/main2.cpp deleted file mode 100644 index 24c3a6a..0000000 --- a/main2.cpp +++ /dev/null @@ -1,166 +0,0 @@ -// Some comments about author -#include -#include -#include -#include - -#include "DSP2833x_Device.h" -#include "DSP28x_Project.h" // Device Headerfile and Examples Include File -#include "DSP2833x_Examples.h" -#include "Protocol/CAN.h" -#include "Protocol/CAN_data.h" -#include "Protocol/DigitalIO.h" -#include "Periphery.h" - - -//Functions declarations -void idle_loop(void); - -interrupt void cpu_timer0_isr(void); -interrupt void cpu_timer1_isr(void); -interrupt void canb_isr(void); -interrupt void canb_box_isr(void); - -Periphery periphery; - -volatile Uint16 infCounter = 0; -volatile Uint16 canISRcounter = 0; -volatile Uint16 canBoxISRcounter = 0; -volatile Uint16 testCounter = 0; - -volatile bool init = true; -volatile bool startTX = false; -volatile bool update = false; -volatile bool sendRemote = false; - -Uint16 modbusInit = 0; -int32 testVar = 0; - -void main() -{ - ServiceDog(); - DisableDog(); - - InitSysCtrl(); - - DINT; - - InitPieCtrl(); - - IER = 0x0000; - IFR = 0x0000; - - InitPieVectTable(); - - EALLOW; - PieVectTable.TINT0 = &cpu_timer0_isr; - PieVectTable.XINT13 = &cpu_timer1_isr; - PieVectTable.ECAN0INTB = &canb_isr; - PieVectTable.ECAN1INTB = &canb_box_isr; - EDIS; - - InitCpuTimers(); - ConfigCpuTimer(&CpuTimer0, 150, 1000); // 1ms - ConfigCpuTimer(&CpuTimer1, 150, 5000); // 5ms - - IER |= M_INT1; // Enable CPU Interrupt 1 - IER |= M_INT9; // Enable CPU Interrupt 9 - IER |= M_INT13; // Enable CPU Interrupt 13 - - PieCtrlRegs.PIEIER1.bit.INTx7 = 1; - PieCtrlRegs.PIEIER9.bit.INTx7 = 1; // from 5 to 8 - PieCtrlRegs.PIEIER9.bit.INTx8 = 1; - - periphery.config(); - - // Enable global Interrupts and higher priority real-time debug events: - EINT; // Enable Global interrupt INTM - ERTM; // Enable Global realtime interrupt DBGM - - periphery.updateVersionFPGA(); - - CpuTimer0.RegsAddr->TCR.bit.TSS = 0; - CpuTimer1.RegsAddr->TCR.bit.TSS = 0; - - idle_loop(); - // -}//end main() -// -// - -void idle_loop() -{ - while (true) - { - infCounter++; - - periphery.initExternalModbus(); - - }//end while - -}//end idle_loop() - - -interrupt void cpu_timer0_isr(void) -{ - periphery.processDigitalOutput(); - - PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1; -}//end - - -interrupt void cpu_timer1_isr(){ - CpuTimer1.InterruptCount++; - - periphery.processDigitalInput(); -} - - -interrupt void canb_isr(void){ - canISRcounter++; - - CANGIF0_REG CANGIF0_SHADOW; - volatile Uint32 resetBit; - - CANGIF0_SHADOW.all = ECanbRegs.CANGIF0.all; - - if (CANGIF0_SHADOW.bit.WLIF0){ - resetBit = 256; - ECanbRegs.CANGIF0.all = 256ul; - } - - if (CANGIF0_SHADOW.bit.EPIF0){ - ECanbRegs.CANGIF0.all = 528ul; - } - - PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9; -} - -interrupt void canb_box_isr(void){ - canBoxISRcounter++; - - // Just example - // - // volatile Uint32 boxNumberIsr; - // boxNumberIsr = ECanbRegs.CANGIF1.bit.MIV1; - - // CANRMP_REG temp; - // temp.all = 0; - // temp.all = 1ul << 27; - - // ECanbRegs.CANRMP.all = temp.all; - - // MODBUS_COMM_CPU_Message27.mdh.all = ECanbMboxes.MBOX27.MDH.all; - // MODBUS_COMM_CPU_Message27.mdl.all = ECanbMboxes.MBOX27.MDL.all; - - // temp.all = ECanbRegs.CANRMP.all; - // if (temp.bit.RMP25){ - // temp.all = 1ul << 25; - // ECanbRegs.CANRMP.all = temp.all; - - // MODBUS_COMM_CPU_Message25.mdh.all = ECanbMboxes.MBOX25.MDH.all; - // MODBUS_COMM_CPU_Message25.mdl.all = ECanbMboxes.MBOX25.MDL.all; - // } - - PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9; -}