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feature/CA
| Author | SHA1 | Date |
|---|---|---|
Oleg
|
8cbdce2192 | 8 months ago |
|
Oleg
|
61b34218ff | 8 months ago |
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Oleg
|
a450de810f | 8 months ago |
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Oleg
|
cc59948011 | 8 months ago |
|
Oleg
|
d864977511 | 8 months ago |
|
Oleg
|
c692668f7b | 8 months ago |
|
Oleg
|
dbbd22524b | 8 months ago |
|
Oleg
|
07bb5edd57 | 8 months ago |
|
Oleg
|
7cd6a2ea9e | 8 months ago |
|
Oleg
|
b884754d93 | 8 months ago |
|
Oleg
|
182ada3bba | 8 months ago |
|
Oleg
|
ac023187cd | 8 months ago |
|
Oleg
|
714f0265cc | 8 months ago |
|
Oleg
|
0246107428 | 8 months ago |
|
Oleg
|
0efa3cb375 | 8 months ago |
|
Oleg
|
de707c052a | 9 months ago |
|
Oleg
|
fd72d2833b | 9 months ago |
|
Oleg
|
dfb90e3ee8 | 9 months ago |
|
Oleg
|
4446eb970a | 9 months ago |
|
Oleg
|
82df69c385 | 9 months ago |
|
Oleg
|
34fe93213f | 9 months ago |
|
Oleg
|
eee4c90277 | 9 months ago |
@ -0,0 +1,45 @@
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||||
;; TI File $Revision: /main/1 $
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;; Checkin $Date: July 30, 2007 10:29:23 $
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;;###########################################################################
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;;
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;; FILE: ADC_cal.asm
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;;
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;; TITLE: 2833x Boot Rom ADC Cal routine.
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;;
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;; Functions:
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;;
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;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and
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;; ADCOFFTRIM registers
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;; Notes:
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;;
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;;###########################################################################
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;; $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
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;; $Release Date: November 1, 2016 $
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;; $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
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;; http://www.ti.com/ ALL RIGHTS RESERVED $
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;;###########################################################################
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.def _ADC_cal
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.asg "0x711C", ADCREFSEL_LOC
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;-----------------------------------------------
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; _ADC_cal
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;-----------------------------------------------
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;-----------------------------------------------
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; This is the ADC cal routine.This routine is programmed into
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; reserved memory by the factory. 0xAAAA and 0xBBBB are place-
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; holders for calibration data.
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;The actual values programmed by TI are device specific.
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;
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; This function assumes that the clocks have been
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; enabled to the ADC module.
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;-----------------------------------------------
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.sect ".adc_cal"
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_ADC_cal
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MOVW DP, #ADCREFSEL_LOC >> 6
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MOV @28, #0xAAAA ; actual value may not be 0xAAAA
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MOV @29, #0xBBBB ; actual value may not be 0xBBBB
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LRETR
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;eof ----------
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@ -0,0 +1,88 @@
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;// TI File $Revision: /main/1 $
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;// Checkin $Date: August 18, 2006 13:45:55 $
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;//###########################################################################
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;//
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;// FILE: DSP2833x_CodeStartBranch.asm
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;//
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;// TITLE: Branch for redirecting code execution after boot.
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;//
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;// For these examples, code_start is the first code that is executed after
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;// exiting the boot ROM code.
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;//
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;// The codestart section in the linker cmd file is used to physically place
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;// this code at the correct memory location. This section should be placed
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;// at the location the BOOT ROM will re-direct the code to. For example,
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;// for boot to FLASH this code will be located at 0x3f7ff6.
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;//
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;// In addition, the example DSP2833x projects are setup such that the codegen
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;// entry point is also set to the code_start label. This is done by linker
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;// option -e in the project build options. When the debugger loads the code,
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;// it will automatically set the PC to the "entry point" address indicated by
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;// the -e linker option. In this case the debugger is simply assigning the PC,
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;// it is not the same as a full reset of the device.
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;//
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;// The compiler may warn that the entry point for the project is other then
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;// _c_init00. _c_init00 is the C environment setup and is run before
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;// main() is entered. The code_start code will re-direct the execution
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;// to _c_init00 and thus there is no worry and this warning can be ignored.
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;//
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;//###########################################################################
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;// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
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;// $Release Date: November 1, 2016 $
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;// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
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;// http://www.ti.com/ ALL RIGHTS RESERVED $
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;//###########################################################################
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***********************************************************************
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WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0
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.ref _c_int00
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.global code_start
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***********************************************************************
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* Function: codestart section
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*
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* Description: Branch to code starting point
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***********************************************************************
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.sect "codestart"
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code_start:
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.if WD_DISABLE == 1
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LB wd_disable ;Branch to watchdog disable code
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.else
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LB _c_int00 ;Branch to start of boot.asm in RTS library
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.endif
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;end codestart section
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***********************************************************************
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* Function: wd_disable
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*
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* Description: Disables the watchdog timer
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***********************************************************************
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.if WD_DISABLE == 1
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.text
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wd_disable:
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SETC OBJMODE ;Set OBJMODE for 28x object code
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EALLOW ;Enable EALLOW protected register access
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MOVZ DP, #7029h>>6 ;Set data page for WDCR register
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MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
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EDIS ;Disable EALLOW protected register access
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LB _c_int00 ;Branch to start of boot.asm in RTS library
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.endif
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;end wd_disable
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.end
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;//===========================================================================
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;// End of file.
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;//===========================================================================
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@ -0,0 +1,164 @@
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//###########################################################################
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//
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// FILE: DSP2833x_CpuTimers.c
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//
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// TITLE: CPU 32-bit Timers Initialization & Support Functions.
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//
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// NOTES: CpuTimer2 is reserved for use with DSP BIOS and
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// other realtime operating systems.
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//
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// Do not use these this timer in your application if you ever plan
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// on integrating DSP-BIOS or another realtime OS.
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//
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//###########################################################################
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// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
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// $Release Date: November 1, 2016 $
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||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
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// http://www.ti.com/ ALL RIGHTS RESERVED $
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//###########################################################################
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//
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// Included Files
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//
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#include "DSP2833x_Device.h" // Headerfile Include File
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#include "DSP2833x_Examples.h" // Examples Include File
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//
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// Defines
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//
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struct CPUTIMER_VARS CpuTimer0;
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//
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// When using DSP BIOS & other RTOS, comment out CPU Timer 2 code.
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//
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struct CPUTIMER_VARS CpuTimer1;
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struct CPUTIMER_VARS CpuTimer2;
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//
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// InitCpuTimers - This function initializes all three CPU timers to a known
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// state.
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//
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void
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InitCpuTimers(void)
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{
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//
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// CPU Timer 0 - Initialize address pointers to respective timer registers
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//
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CpuTimer0.RegsAddr = &CpuTimer0Regs;
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//
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// Initialize timer period to maximum
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//
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CpuTimer0Regs.PRD.all = 0xFFFFFFFF;
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//
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// Initialize pre-scale counter to divide by 1 (SYSCLKOUT)
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//
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CpuTimer0Regs.TPR.all = 0;
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CpuTimer0Regs.TPRH.all = 0;
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//
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// Make sure timer is stopped
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//
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CpuTimer0Regs.TCR.bit.TSS = 1;
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//
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// Reload all counter register with period value
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//
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CpuTimer0Regs.TCR.bit.TRB = 1;
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//
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// Reset interrupt counters
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//
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CpuTimer0.InterruptCount = 0;
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//
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// CpuTimer2 is reserved for DSP BIOS & other RTOS
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// Do not use this timer if you ever plan on integrating
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// DSP-BIOS or another realtime OS.
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//
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//
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// Initialize address pointers to respective timer registers
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//
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CpuTimer1.RegsAddr = &CpuTimer1Regs;
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CpuTimer2.RegsAddr = &CpuTimer2Regs;
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//
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// Initialize timer period to maximum
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//
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CpuTimer1Regs.PRD.all = 0xFFFFFFFF;
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CpuTimer2Regs.PRD.all = 0xFFFFFFFF;
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//
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// Make sure timers are stopped
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//
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CpuTimer1Regs.TCR.bit.TSS = 1;
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CpuTimer2Regs.TCR.bit.TSS = 1;
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//
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// Reload all counter register with period value
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//
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CpuTimer1Regs.TCR.bit.TRB = 1;
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CpuTimer2Regs.TCR.bit.TRB = 1;
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//
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// Reset interrupt counters
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//
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CpuTimer1.InterruptCount = 0;
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CpuTimer2.InterruptCount = 0;
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}
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//
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// ConfigCpuTimer - This function initializes the selected timer to the period
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// specified by the "Freq" and "Period" parameters. The "Freq" is entered as
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// "MHz" and the period in "uSeconds". The timer is held in the stopped state
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// after configuration.
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//
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void
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ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
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{
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Uint32 temp;
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//
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// Initialize timer period
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//
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Timer->CPUFreqInMHz = Freq;
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Timer->PeriodInUSec = Period;
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temp = (long) (Freq * Period);
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Timer->RegsAddr->PRD.all = temp;
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//
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// Set pre-scale counter to divide by 1 (SYSCLKOUT)
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//
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Timer->RegsAddr->TPR.all = 0;
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Timer->RegsAddr->TPRH.all = 0;
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//
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// Initialize timer control register
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//
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//
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// 1 = Stop timer, 0 = Start/Restart Timer
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//
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Timer->RegsAddr->TCR.bit.TSS = 1;
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Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
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Timer->RegsAddr->TCR.bit.SOFT = 1;
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Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run
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//
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// 0 = Disable/ 1 = Enable Timer Interrupt
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//
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Timer->RegsAddr->TCR.bit.TIE = 1;
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//
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// Reset interrupt counter
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//
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Timer->InterruptCount = 0;
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}
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//
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// End of File
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//
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,464 @@
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//###########################################################################
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//
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// FILE: DSP2833x_ECan.c
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//
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// TITLE: DSP2833x Enhanced CAN Initialization & Support Functions.
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//
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//###########################################################################
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||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
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//
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||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
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#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
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|
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//
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// InitECan - This function initializes the eCAN module to a known state.
|
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//
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void
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InitECan(void)
|
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{
|
||||
InitECana();
|
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#if DSP28_ECANB
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InitECanb();
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#endif // if DSP28_ECANB
|
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}
|
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|
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//
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// InitECana - Initialize eCAN-A module
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//
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void
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InitECana(void)
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{
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//
|
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// Create a shadow register structure for the CAN control registers. This
|
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// is needed, since only 32-bit access is allowed to these registers.
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// 16-bit access to these registers could potentially corrupt the register
|
||||
// contents or return false data. This is especially true while writing
|
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// to/reading from a bit (or group of bits) among bits 16 - 31
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//
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struct ECAN_REGS ECanaShadow;
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|
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EALLOW; // EALLOW enables access to protected bits
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|
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//
|
||||
// Configure eCAN RX and TX pins for CAN operation using eCAN regs
|
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//
|
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ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
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ECanaShadow.CANTIOC.bit.TXFUNC = 1;
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ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
|
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|
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ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
|
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ECanaShadow.CANRIOC.bit.RXFUNC = 1;
|
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ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
|
||||
|
||||
//
|
||||
// Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31)
|
||||
// HECC mode also enables time-stamping feature
|
||||
//
|
||||
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
|
||||
ECanaShadow.CANMC.bit.SCB = 1;
|
||||
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
|
||||
|
||||
//
|
||||
// Initialize all bits of 'Master Control Field' to zero
|
||||
// Some bits of MSGCTRL register come up in an unknown state. For proper
|
||||
// operation, all bits (including reserved bits) of MSGCTRL must be
|
||||
// initialized to zero
|
||||
//
|
||||
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
|
||||
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
|
||||
|
||||
//
|
||||
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
|
||||
// as a matter of precaution.
|
||||
//
|
||||
ECanaRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits
|
||||
|
||||
ECanaRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits
|
||||
|
||||
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits
|
||||
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
|
||||
|
||||
//
|
||||
// Configure bit timing parameters for eCANA
|
||||
//
|
||||
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
|
||||
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
|
||||
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
|
||||
|
||||
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||
|
||||
do
|
||||
{
|
||||
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set
|
||||
|
||||
ECanaShadow.CANBTC.all = 0;
|
||||
|
||||
//
|
||||
// CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
|
||||
//
|
||||
#if (CPU_FRQ_150MHZ)
|
||||
//
|
||||
// The following block for all 150 MHz SYSCLKOUT
|
||||
// (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at End of File
|
||||
//
|
||||
ECanaShadow.CANBTC.bit.BRPREG = 4;
|
||||
ECanaShadow.CANBTC.bit.TSEG2REG = 2;
|
||||
ECanaShadow.CANBTC.bit.TSEG1REG = 10;
|
||||
#endif
|
||||
|
||||
//
|
||||
// CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
|
||||
//
|
||||
#if (CPU_FRQ_100MHZ)
|
||||
//
|
||||
// The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock).
|
||||
// Bit rate = 1 Mbps See Note at End of File
|
||||
//
|
||||
ECanaShadow.CANBTC.bit.BRPREG = 4;
|
||||
ECanaShadow.CANBTC.bit.TSEG2REG = 1;
|
||||
ECanaShadow.CANBTC.bit.TSEG1REG = 6;
|
||||
#endif
|
||||
|
||||
ECanaShadow.CANBTC.bit.SAM = 1;
|
||||
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
|
||||
|
||||
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
|
||||
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
|
||||
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
|
||||
|
||||
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||
|
||||
do
|
||||
{
|
||||
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
|
||||
} while(ECanaShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared
|
||||
|
||||
//
|
||||
// Disable all Mailboxes
|
||||
//
|
||||
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
#if (DSP28_ECANB)
|
||||
//
|
||||
// Initialize eCAN-B module
|
||||
//
|
||||
void
|
||||
InitECanb(void)
|
||||
{
|
||||
//
|
||||
// Create a shadow register structure for the CAN control registers. This
|
||||
// is needed, since only 32-bit access is allowed to these registers.
|
||||
// 16-bit access to these registers could potentially corrupt the register
|
||||
// contents or return false data. This is especially true while writing
|
||||
// to/reading from a bit (or group of bits) among bits 16 - 31
|
||||
//
|
||||
struct ECAN_REGS ECanbShadow;
|
||||
|
||||
EALLOW; // EALLOW enables access to protected bits
|
||||
|
||||
//
|
||||
// Configure eCAN RX and TX pins for CAN operation using eCAN regs
|
||||
//
|
||||
ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
|
||||
ECanbShadow.CANTIOC.bit.TXFUNC = 1;
|
||||
ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;
|
||||
|
||||
ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
|
||||
ECanbShadow.CANRIOC.bit.RXFUNC = 1;
|
||||
ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;
|
||||
|
||||
//
|
||||
// Configure eCAN for HECC mode - (read to access mailboxes 16 thru 31)
|
||||
//
|
||||
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
|
||||
ECanbShadow.CANMC.bit.SCB = 1;
|
||||
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
|
||||
|
||||
//
|
||||
// Initialize all bits of 'Master Control Field' to zero
|
||||
// Some bits of MSGCTRL register come up in an unknown state. For proper
|
||||
// operation, all bits (including reserved bits) of MSGCTRL must be
|
||||
// initialized to zero
|
||||
//
|
||||
ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
|
||||
ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;
|
||||
|
||||
//
|
||||
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
|
||||
// as a matter of precaution.
|
||||
//
|
||||
ECanbRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn bits
|
||||
|
||||
ECanbRegs.CANRMP.all = 0xFFFFFFFF; // Clear all RMPn bits
|
||||
|
||||
ECanbRegs.CANGIF0.all = 0xFFFFFFFF; // Clear all interrupt flag bits
|
||||
ECanbRegs.CANGIF1.all = 0xFFFFFFFF;
|
||||
|
||||
//
|
||||
// Configure bit timing parameters for eCANB
|
||||
//
|
||||
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
|
||||
ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
|
||||
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
|
||||
|
||||
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||
|
||||
do
|
||||
{
|
||||
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||
} while(ECanbShadow.CANES.bit.CCE != 1); // Wait for CCE bit to be cleared
|
||||
|
||||
ECanbShadow.CANBTC.all = 0;
|
||||
|
||||
//
|
||||
// CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
|
||||
//
|
||||
#if (CPU_FRQ_150MHZ)
|
||||
//
|
||||
// The following block for all 150 MHz SYSCLKOUT
|
||||
// (75 MHz CAN clock) - default. Bit rate = 1 Mbps See Note at end of file
|
||||
//
|
||||
ECanbShadow.CANBTC.bit.BRPREG = 4;
|
||||
ECanbShadow.CANBTC.bit.TSEG2REG = 2;
|
||||
ECanbShadow.CANBTC.bit.TSEG1REG = 10;
|
||||
#endif
|
||||
|
||||
//
|
||||
// CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
|
||||
//
|
||||
#if (CPU_FRQ_100MHZ)
|
||||
//
|
||||
// The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock).
|
||||
// Bit rate = 1 Mbps See Note at end of file
|
||||
//
|
||||
ECanbShadow.CANBTC.bit.BRPREG = 4;
|
||||
ECanbShadow.CANBTC.bit.TSEG2REG = 1;
|
||||
ECanbShadow.CANBTC.bit.TSEG1REG = 6;
|
||||
#endif
|
||||
|
||||
ECanbShadow.CANBTC.bit.SAM = 1;
|
||||
ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;
|
||||
|
||||
ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
|
||||
ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
|
||||
ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;
|
||||
|
||||
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||
|
||||
do
|
||||
{
|
||||
ECanbShadow.CANES.all = ECanbRegs.CANES.all;
|
||||
} while(ECanbShadow.CANES.bit.CCE != 0 );// Wait for CCE bit to be cleared
|
||||
|
||||
//
|
||||
// Disable all Mailboxes
|
||||
//
|
||||
ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // if DSP28_ECANB
|
||||
|
||||
//
|
||||
// InitECanGpio - This function initializes GPIO pins to function as eCAN pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// Only one GPIO pin should be enabled for CANTXA/B operation.
|
||||
// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
void
|
||||
InitECanGpio(void)
|
||||
{
|
||||
InitECanaGpio();
|
||||
#if (DSP28_ECANB)
|
||||
InitECanbGpio();
|
||||
#endif // if DSP28_ECANB
|
||||
}
|
||||
|
||||
//
|
||||
// InitECanaGpio - This function initializes GPIO pins to function as eCAN- A
|
||||
//
|
||||
void
|
||||
InitECanaGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected CAN pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (CANRXA)
|
||||
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; //Enable pull-up for GPIO31 (CANTXA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up for GPIO19 (CANTXA)
|
||||
|
||||
//
|
||||
// Set qualification for selected CAN pins to asynch only
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
//
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch qual for GPIO18 (CANRXA)
|
||||
|
||||
//
|
||||
// Configure eCAN-A pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be eCAN functional
|
||||
// pins.
|
||||
//
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 for CANRXA
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 for CANTXA
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
#if (DSP28_ECANB)
|
||||
//
|
||||
// InitECanbGpio - This function initializes GPIO pins to function as eCAN-B
|
||||
//
|
||||
void
|
||||
InitECanbGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected CAN pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; //Enable pull-up for GPIO8 (CANTXB)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; //Enable pull-up for GPIO12(CANTXB)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; //Enable pull-up for GPIO16(CANTXB)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; //Enable pull-up for GPIO20(CANTXB)
|
||||
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10(CANRXB)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up for GPIO13(CANRXB)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up for GPIO17(CANRXB)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up for GPIO21(CANRXB)
|
||||
|
||||
//
|
||||
// Set qualification for selected CAN pins to asynch only
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
// GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
|
||||
//GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)
|
||||
|
||||
//
|
||||
// Configure eCAN-B pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be eCAN functional
|
||||
// pins.
|
||||
//
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2; // Configure GPIO12 for CANTXB
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // Configure GPIO16 for CANTXB
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 for CANTXB
|
||||
|
||||
// GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2; // Configure GPIO13 for CANRXB
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // Configure GPIO17 for CANRXB
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 for CANRXB
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // if DSP28_ECANB
|
||||
|
||||
//
|
||||
// Note: Bit timing parameters must be chosen based on the network parameters
|
||||
// such as the sampling point desired and the propagation delay of the network.
|
||||
// The propagation delay is a function of length of the cable, delay introduced
|
||||
// by the transceivers and opto/galvanic-isolators (if any).
|
||||
//
|
||||
// The parameters used in this file must be changed taking into account the
|
||||
// above mentioned factors in order to arrive at the bit-timing parameters
|
||||
// suitable for a network.
|
||||
//
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
|
||||
@ -0,0 +1,273 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_ECap.c
|
||||
//
|
||||
// TITLE: DSP2833x eCAP Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//
|
||||
// InitECap - This function initializes the eCAP(s) to a known state.
|
||||
//
|
||||
void
|
||||
InitECap(void)
|
||||
{
|
||||
//
|
||||
// Initialize eCAP1/2/3
|
||||
//
|
||||
}
|
||||
|
||||
//
|
||||
// InitECapGpio - This function initializes GPIO pins to function as ECAP pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// For each eCAP peripheral
|
||||
// Only one GPIO pin should be enabled for ECAP operation.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
void
|
||||
InitECapGpio()
|
||||
{
|
||||
InitECap1Gpio();
|
||||
#if (DSP28_ECAP2)
|
||||
InitECap2Gpio();
|
||||
#endif // endif DSP28_ECAP2
|
||||
#if (DSP28_ECAP3)
|
||||
InitECap3Gpio();
|
||||
#endif // endif DSP28_ECAP3
|
||||
#if (DSP28_ECAP4)
|
||||
InitECap4Gpio();
|
||||
#endif // endif DSP28_ECAP4
|
||||
#if (DSP28_ECAP5)
|
||||
InitECap5Gpio();
|
||||
#endif // endif DSP28_ECAP5
|
||||
#if (DSP28_ECAP6)
|
||||
InitECap6Gpio();
|
||||
#endif // endif DSP28_ECAP6
|
||||
}
|
||||
|
||||
//
|
||||
// InitECap1Gpio -
|
||||
//
|
||||
void
|
||||
InitECap1Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (CAP1)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (CAP1)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pull-up on GPIO34 (CAP1)
|
||||
|
||||
//
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 0; //Synch to SYSCLKOUT GPIO5 (CAP1)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; //Synch to SYSCLKOUT GPIO24 (CAP1)
|
||||
//GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; //Synch to SYSCLKOUT GPIO34 (CAP1)
|
||||
|
||||
//
|
||||
// Configure eCAP-1 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be eCAP1 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Configure GPIO5 as CAP1
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // Configure GPIO24 as CAP1
|
||||
//GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 1; // Configure GPIO24 as CAP1
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
#if DSP28_ECAP2
|
||||
//
|
||||
// InitECap2Gpio -
|
||||
//
|
||||
void
|
||||
InitECap2Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (CAP2)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (CAP2)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pull-up on GPIO37 (CAP2)
|
||||
|
||||
//
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; //Synch to SYSCLKOUT GPIO7 (CAP2)
|
||||
//GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; //Synch to SYSCLKOUT GPIO25 (CAP2)
|
||||
//GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; //Synch to SYSCLKOUT GPIO37 (CAP2)
|
||||
|
||||
//
|
||||
// Configure eCAP-2 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be eCAP2 functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 3; // Configure GPIO7 as CAP2
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 1; // Configure GPIO25 as CAP2
|
||||
//GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // Configure GPIO37 as CAP2
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_ECAP2
|
||||
|
||||
#if DSP28_ECAP3
|
||||
//
|
||||
// InitECap3Gpio -
|
||||
//
|
||||
void
|
||||
InitECap3Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (CAP3)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (CAP3)
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Synch to SYSCLKOUT GPIO9 (CAP3)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Synch to SYSCLKOUT GPIO26 (CAP3)
|
||||
|
||||
/* Configure eCAP-3 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAP3 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 3; // Configure GPIO9 as CAP3
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 1; // Configure GPIO26 as CAP3
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_ECAP3
|
||||
|
||||
|
||||
#if DSP28_ECAP4
|
||||
void InitECap4Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (CAP4)
|
||||
// GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (CAP4)
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Synch to SYSCLKOUT GPIO11 (CAP4)
|
||||
// GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Synch to SYSCLKOUT GPIO27 (CAP4)
|
||||
|
||||
/* Configure eCAP-4 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAP4 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as CAP4
|
||||
// GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 1; // Configure GPIO27 as CAP4
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_ECAP4
|
||||
|
||||
|
||||
#if DSP28_ECAP5
|
||||
void InitECap5Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (CAP5)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO48 = 0; // Enable pull-up on GPIO48 (CAP5)
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Synch to SYSCLKOUT GPIO3 (CAP5)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 0; // Synch to SYSCLKOUT GPIO48 (CAP5)
|
||||
|
||||
/* Configure eCAP-5 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAP5 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as CAP5
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 1; // Configure GPIO48 as CAP5
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_ECAP5
|
||||
|
||||
|
||||
#if DSP28_ECAP6
|
||||
void InitECap6Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
/* Enable internal pull-up for the selected pins */
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (CAP6)
|
||||
// GpioCtrlRegs.GPBPUD.bit.GPIO49 = 0; // Enable pull-up on GPIO49 (CAP6)
|
||||
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Synch to SYSCLKOUT GPIO1 (CAP6)
|
||||
// GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 0; // Synch to SYSCLKOUT GPIO49 (CAP6)
|
||||
|
||||
/* Configure eCAP-5 pins using GPIO regs*/
|
||||
// This specifies which of the possible GPIO pins will be eCAP6 functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; // Configure GPIO1 as CAP6
|
||||
// GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 1; // Configure GPIO49 as CAP6
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_ECAP6
|
||||
|
||||
|
||||
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
@ -0,0 +1,376 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EPwm.c
|
||||
//
|
||||
// TITLE: DSP2833x ePWM Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//
|
||||
// InitEPwm - This function initializes the ePWM(s) to a known state.
|
||||
//
|
||||
void
|
||||
InitEPwm(void)
|
||||
{
|
||||
//
|
||||
// Initialize ePWM1/2/3/4/5/6
|
||||
//
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwmGpio - This function initializes GPIO pins to function as ePWM pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
void
|
||||
InitEPwmGpio(void)
|
||||
{
|
||||
InitEPwm1Gpio();
|
||||
InitEPwm2Gpio();
|
||||
InitEPwm3Gpio();
|
||||
#if DSP28_EPWM4
|
||||
InitEPwm4Gpio();
|
||||
#endif // endif DSP28_EPWM4
|
||||
#if DSP28_EPWM5
|
||||
InitEPwm5Gpio();
|
||||
#endif // endif DSP28_EPWM5
|
||||
#if DSP28_EPWM6
|
||||
InitEPwm6Gpio();
|
||||
#endif // endif DSP28_EPWM6
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm1Gpio - This function initializes GPIO pins to function as ePWM1
|
||||
//
|
||||
void
|
||||
InitEPwm1Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pull-up on GPIO1 (EPWM1B)
|
||||
|
||||
//
|
||||
// Configure ePWM-1 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be ePWM1 functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm2Gpio - This function initializes GPIO pins to function as ePWM2
|
||||
//
|
||||
void
|
||||
InitEPwm2Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pull-up on GPIO2 (EPWM2A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (EPWM3B)
|
||||
|
||||
//
|
||||
// Configure ePWM-2 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be ePWM2 functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitEPwm3Gpio - This function initializes GPIO pins to function as ePWM3
|
||||
//
|
||||
void
|
||||
InitEPwm3Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pull-up on GPIO4 (EPWM3A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (EPWM3B)
|
||||
|
||||
//
|
||||
// Configure ePWM-3 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be ePWM3 functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
#if DSP28_EPWM4
|
||||
//
|
||||
// InitEPwm4Gpio - This function initializes GPIO pins to function as ePWM4
|
||||
//
|
||||
void
|
||||
InitEPwm4Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pull-up on GPIO6 (EPWM4A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pull-up on GPIO7 (EPWM4B)
|
||||
|
||||
//
|
||||
// Configure ePWM-4 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be ePWM4 functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_EPWM4
|
||||
|
||||
#if DSP28_EPWM5
|
||||
//
|
||||
// InitEPwm5Gpio - This function initializes GPIO pins to function as ePWM5
|
||||
//
|
||||
void
|
||||
InitEPwm5Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up on GPIO8 (EPWM5A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up on GPIO9 (EPWM5B)
|
||||
|
||||
//
|
||||
// Configure ePWM-5 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be ePWM5 functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_EPWM5
|
||||
|
||||
#if DSP28_EPWM6
|
||||
//
|
||||
// InitEPwm6Gpio - This function initializes GPIO pins to function as ePWM6
|
||||
//
|
||||
void
|
||||
InitEPwm6Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up on GPIO10 (EPWM6A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up on GPIO11 (EPWM6B)
|
||||
|
||||
//
|
||||
// Configure ePWM-6 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be ePWM6 functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_EPWM6
|
||||
|
||||
//
|
||||
// InitEPwmSyncGpio - This function initializes GPIO pins to function as ePWM
|
||||
// Synch pins
|
||||
//
|
||||
void
|
||||
InitEPwmSyncGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Configure EPWMSYNCI
|
||||
//
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; //Enable pull-up on GPIO6 (EPWMSYNCI)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;//Enable pull-up on GPIO32 (EPWMSYNCI)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
// This will select synch to SYSCLKOUT for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
|
||||
//
|
||||
// Synch to SYSCLKOUT GPIO6 (EPWMSYNCI)
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0;
|
||||
|
||||
//
|
||||
//Synch to SYSCLKOUT GPIO32 (EPWMSYNCI)
|
||||
//
|
||||
//GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0;
|
||||
|
||||
//
|
||||
// Configure EPwmSync pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be EPwmSync
|
||||
// functional pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 2; //Enable pull-up on GPIO6(EPWMSYNCI)
|
||||
//GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 2;//Enable pull-up on GPIO32(EPWMSYNCI)
|
||||
|
||||
//
|
||||
// Configure EPWMSYNC0
|
||||
//
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
|
||||
//
|
||||
// Enable pull-up on GPIO6 (EPWMSYNC0)
|
||||
//
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0;
|
||||
|
||||
//
|
||||
// Enable pull-up on GPIO33 (EPWMSYNC0)
|
||||
//
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0;
|
||||
|
||||
//
|
||||
// Enable pull-up on GPIO6 (EPWMSYNC0)
|
||||
//
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3;
|
||||
|
||||
//
|
||||
// Enable pull-up on GPIO33 (EPWMSYNC0)
|
||||
//
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 2;
|
||||
}
|
||||
|
||||
//
|
||||
// InitTzGpio - This function initializes GPIO pins to function as Trip Zone
|
||||
// (TZ) pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
void
|
||||
InitTzGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pull-up on GPIO12 (TZ1)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pull-up on GPIO13 (TZ2)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up on GPIO14 (TZ3)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up on GPIO15 (TZ4)
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (TZ5)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up on GPIO28 (TZ5)
|
||||
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (TZ6)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up on GPIO29 (TZ6)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Asynch input GPIO12 (TZ1)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch input GPIO13 (TZ2)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Asynch input GPIO14 (TZ3)
|
||||
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (TZ4)
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (TZ5)
|
||||
//GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (TZ5)
|
||||
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (TZ6)
|
||||
//GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3; // Asynch input GPIO29 (TZ6)
|
||||
|
||||
//
|
||||
// Configure TZ pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be TZ functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as TZ1
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as TZ2
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as TZ3
|
||||
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as TZ4
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as TZ5
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // Configure GPIO28 as TZ5
|
||||
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as TZ6
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // Configure GPIO29 as TZ6
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_EQep.c
|
||||
//
|
||||
// TITLE: DSP2833x eQEP Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//
|
||||
// InitEQep - This function initializes the eQEP(s) to a known state.
|
||||
//
|
||||
void
|
||||
InitEQep(void)
|
||||
{
|
||||
//
|
||||
// Initialize eQEP1/2
|
||||
//
|
||||
}
|
||||
|
||||
//
|
||||
// InitEQepGpio - This function initializes GPIO pins to function as eQEP pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// For each eQEP peripheral
|
||||
// Only one GPIO pin should be enabled for EQEPxA operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxB operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxS operation.
|
||||
// Only one GPIO pin should be enabled for EQEPxI operation.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
void
|
||||
InitEQepGpio()
|
||||
{
|
||||
#if DSP28_EQEP1
|
||||
InitEQep1Gpio();
|
||||
#endif // endif DSP28_EQEP1
|
||||
#if DSP28_EQEP2
|
||||
InitEQep2Gpio();
|
||||
#endif // endif DSP28_EQEP2
|
||||
}
|
||||
|
||||
//
|
||||
// InitEQep1Gpio - This function initializes GPIO pins to function as eQEP1
|
||||
//
|
||||
#if DSP28_EQEP1
|
||||
void
|
||||
InitEQep1Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pull-up on GPIO20 (EQEP1A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pull-up on GPIO21 (EQEP1B)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up on GPIO22 (EQEP1S)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up on GPIO23 (EQEP1I)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pull-up on GPIO50 (EQEP1A)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pull-up on GPIO51 (EQEP1B)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0; // Enable pull-up on GPIO52 (EQEP1S)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0; // Enable pull-up on GPIO53 (EQEP1I)
|
||||
|
||||
//
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync to SYSCLKOUT GPIO20 (EQEP1A)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync to SYSCLKOUT GPIO21 (EQEP1B)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync to SYSCLKOUT GPIO22 (EQEP1S)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync to SYSCLKOUT GPIO23 (EQEP1I)
|
||||
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; //Sync to SYSCLKOUT GPIO50(EQEP1A)
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; //Sync to SYSCLKOUT GPIO51(EQEP1B)
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; //Sync to SYSCLKOUT GPIO52(EQEP1S)
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; //Sync to SYSCLKOUT GPIO53(EQEP1I)
|
||||
|
||||
//
|
||||
// Configure eQEP-1 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be eQEP1 functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I
|
||||
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // if DSP28_EQEP1
|
||||
|
||||
//
|
||||
// InitEQep2Gpio - This function initializes GPIO pins to function as eQEP2
|
||||
//
|
||||
#if DSP28_EQEP2
|
||||
void
|
||||
InitEQep2Gpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pull-up on GPIO24 (EQEP2A)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pull-up on GPIO25 (EQEP2B)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO26 = 0; // Enable pull-up on GPIO26 (EQEP2I)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO27 = 0; // Enable pull-up on GPIO27 (EQEP2S)
|
||||
|
||||
//
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync to SYSCLKOUT GPIO24 (EQEP2A)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync to SYSCLKOUT GPIO25 (EQEP2B)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync to SYSCLKOUT GPIO26 (EQEP2I)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync to SYSCLKOUT GPIO27 (EQEP2S)
|
||||
|
||||
//
|
||||
// Configure eQEP-2 pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be eQEP2 functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2I
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2S
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // endif DSP28_EQEP2
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,376 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_GlobalVariableDefs.c
|
||||
//
|
||||
// TITLE: DSP2833x Global Variables and Data Section Pragmas.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
|
||||
//
|
||||
// Define Global Peripheral Variables
|
||||
//
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcRegs,"AdcRegsFile");
|
||||
#endif
|
||||
volatile struct ADC_REGS AdcRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("AdcMirrorFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(AdcMirror,"AdcMirrorFile");
|
||||
#endif
|
||||
volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuTimer0RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile");
|
||||
#endif
|
||||
volatile struct CPUTIMER_REGS CpuTimer0Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuTimer1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile");
|
||||
#endif
|
||||
volatile struct CPUTIMER_REGS CpuTimer1Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CpuTimer2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile");
|
||||
#endif
|
||||
volatile struct CPUTIMER_REGS CpuTimer2Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CsmPwlFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CsmPwl,"CsmPwlFile");
|
||||
#endif
|
||||
volatile struct CSM_PWL CsmPwl;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("CsmRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(CsmRegs,"CsmRegsFile");
|
||||
#endif
|
||||
volatile struct CSM_REGS CsmRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DevEmuRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile");
|
||||
#endif
|
||||
volatile struct DEV_EMU_REGS DevEmuRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("DmaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(DmaRegs,"DmaRegsFile");
|
||||
#endif
|
||||
volatile struct DMA_REGS DmaRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECanaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile");
|
||||
#endif
|
||||
volatile struct ECAN_REGS ECanaRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECanaMboxesFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile");
|
||||
#endif
|
||||
volatile struct ECAN_MBOXES ECanaMboxes;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECanaLAMRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile");
|
||||
#endif
|
||||
volatile struct LAM_REGS ECanaLAMRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECanaMOTSRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile");
|
||||
#endif
|
||||
volatile struct MOTS_REGS ECanaMOTSRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECanaMOTORegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile");
|
||||
#endif
|
||||
volatile struct MOTO_REGS ECanaMOTORegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECanbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECanbRegs,"ECanbRegsFile");
|
||||
#endif
|
||||
volatile struct ECAN_REGS ECanbRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECanbMboxesFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECanbMboxes,"ECanbMboxesFile");
|
||||
#endif
|
||||
volatile struct ECAN_MBOXES ECanbMboxes;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECanbLAMRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECanbLAMRegs,"ECanbLAMRegsFile");
|
||||
#endif
|
||||
volatile struct LAM_REGS ECanbLAMRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECanbMOTSRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECanbMOTSRegs,"ECanbMOTSRegsFile");
|
||||
#endif
|
||||
volatile struct MOTS_REGS ECanbMOTSRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECanbMOTORegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECanbMOTORegs,"ECanbMOTORegsFile");
|
||||
#endif
|
||||
volatile struct MOTO_REGS ECanbMOTORegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm1Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm2Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm3RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm3Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm4RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm4Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm5RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm5Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EPwm6RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile");
|
||||
#endif
|
||||
volatile struct EPWM_REGS EPwm6Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap1Regs;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap2Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap3RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap3Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap4RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap4Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap5RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap5Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ECap6RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile");
|
||||
#endif
|
||||
volatile struct ECAP_REGS ECap6Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EQep1RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile");
|
||||
#endif
|
||||
volatile struct EQEP_REGS EQep1Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("EQep2RegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile");
|
||||
#endif
|
||||
volatile struct EQEP_REGS EQep2Regs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("GpioCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("GpioDataRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile");
|
||||
#endif
|
||||
volatile struct GPIO_DATA_REGS GpioDataRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("GpioIntRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(GpioIntRegs,"GpioIntRegsFile");
|
||||
#endif
|
||||
volatile struct GPIO_INT_REGS GpioIntRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("I2caRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(I2caRegs,"I2caRegsFile");
|
||||
#endif
|
||||
volatile struct I2C_REGS I2caRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("McbspaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile");
|
||||
#endif
|
||||
volatile struct MCBSP_REGS McbspaRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("McbspbRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile");
|
||||
#endif
|
||||
volatile struct MCBSP_REGS McbspbRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("PartIdRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(PartIdRegs,"PartIdRegsFile");
|
||||
#endif
|
||||
volatile struct PARTID_REGS PartIdRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("PieCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct PIE_CTRL_REGS PieCtrlRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("PieVectTableFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(PieVectTable,"PieVectTableFile");
|
||||
#endif
|
||||
volatile struct PIE_VECT_TABLE PieVectTable;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SciaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SciaRegs,"SciaRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS SciaRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ScibRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ScibRegs,"ScibRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS ScibRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("ScicRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(ScicRegs,"ScicRegsFile");
|
||||
#endif
|
||||
volatile struct SCI_REGS ScicRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SpiaRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile");
|
||||
#endif
|
||||
volatile struct SPI_REGS SpiaRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("SysCtrlRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile");
|
||||
#endif
|
||||
volatile struct SYS_CTRL_REGS SysCtrlRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("FlashRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(FlashRegs,"FlashRegsFile");
|
||||
#endif
|
||||
volatile struct FLASH_REGS FlashRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("XIntruptRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile");
|
||||
#endif
|
||||
volatile struct XINTRUPT_REGS XIntruptRegs;
|
||||
|
||||
#ifdef __cplusplus
|
||||
#pragma DATA_SECTION("XintfRegsFile")
|
||||
#else
|
||||
#pragma DATA_SECTION(XintfRegs,"XintfRegsFile");
|
||||
#endif
|
||||
volatile struct XINTF_REGS XintfRegs;
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,77 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Gpio.c
|
||||
//
|
||||
// TITLE: DSP2833x General Purpose I/O Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//
|
||||
// InitGpio - This function initializes the Gpio to a known (default) state.
|
||||
//
|
||||
// For more details on configuring GPIO's as peripheral functions,
|
||||
// refer to the individual peripheral examples and/or GPIO setup example.
|
||||
//
|
||||
void
|
||||
InitGpio(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Each GPIO pin can be:
|
||||
// a) a GPIO input/output
|
||||
// b) peripheral function 1
|
||||
// c) peripheral function 2
|
||||
// d) peripheral function 3
|
||||
// By default, all are GPIO Inputs
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15
|
||||
GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31
|
||||
GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39
|
||||
GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63
|
||||
GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79
|
||||
GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95
|
||||
|
||||
GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs
|
||||
GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs
|
||||
GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs
|
||||
|
||||
//
|
||||
// Each input can have different qualification
|
||||
// a) input synchronized to SYSCLKOUT
|
||||
// b) input qualified by a sampling window
|
||||
// c) input sent asynchronously (valid for peripheral inputs only)
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT
|
||||
GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT
|
||||
|
||||
//
|
||||
// Pull-ups can be enabled or disabled
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31
|
||||
GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63
|
||||
GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79
|
||||
//GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31
|
||||
//GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34
|
||||
//GpioCtrlRegs.GPCPUD.all = 0xFFFF; // Pullup's disabled GPIO64-GPIO79
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,79 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_I2C.c
|
||||
//
|
||||
// TITLE: DSP2833x SCI Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//
|
||||
// InitI2C - This function initializes the I2C to a known state.
|
||||
//
|
||||
void
|
||||
InitI2C(void)
|
||||
{
|
||||
//
|
||||
// Initialize I2C-A
|
||||
//
|
||||
}
|
||||
|
||||
//
|
||||
// InitI2CGpio - This function initializes GPIO pins to function as I2C pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// Only one GPIO pin should be enabled for SDAA operation.
|
||||
// Only one GPIO pin shoudl be enabled for SCLA operation.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
void
|
||||
InitI2CGpio()
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pull-up for GPIO32 (SDAA)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pull-up for GPIO33 (SCLA)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // Asynch input GPIO32 (SDAA)
|
||||
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input GPIO33 (SCLA)
|
||||
|
||||
//
|
||||
// Configure SCI pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be I2C functional
|
||||
// pins. Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // Configure GPIO32 to SDAA
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // Configure GPIO33 to SCLA
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,50 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_MemCopy.c
|
||||
//
|
||||
// TITLE: Memory Copy Utility
|
||||
//
|
||||
// ASSUMPTIONS:
|
||||
//
|
||||
// DESCRIPTION:
|
||||
//
|
||||
// This function will copy the specified memory contents from
|
||||
// one location to another.
|
||||
//
|
||||
// Uint16 *SourceAddr Pointer to the first word to be moved
|
||||
// SourceAddr < SourceEndAddr
|
||||
// Uint16* SourceEndAddr Pointer to the last word to be moved
|
||||
// Uint16* DestAddr Pointer to the first destination word
|
||||
//
|
||||
// No checks are made for invalid memory locations or that the
|
||||
// end address is > then the first start address.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h"
|
||||
|
||||
//
|
||||
// MemCopy -
|
||||
//
|
||||
void
|
||||
MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr)
|
||||
{
|
||||
while(SourceAddr < SourceEndAddr)
|
||||
{
|
||||
*DestAddr++ = *SourceAddr++;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,95 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_PieCtrl.c
|
||||
//
|
||||
// TITLE: DSP2833x Device PIE Control Register Initialization Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//
|
||||
// InitPieCtrl - This function initializes the PIE control registers to a known
|
||||
// state.
|
||||
//
|
||||
void
|
||||
InitPieCtrl(void)
|
||||
{
|
||||
//
|
||||
// Disable Interrupts at the CPU level
|
||||
//
|
||||
DINT;
|
||||
|
||||
//
|
||||
// Disable the PIE
|
||||
//
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
|
||||
|
||||
//
|
||||
// Clear all PIEIER registers
|
||||
//
|
||||
PieCtrlRegs.PIEIER1.all = 0;
|
||||
PieCtrlRegs.PIEIER2.all = 0;
|
||||
PieCtrlRegs.PIEIER3.all = 0;
|
||||
PieCtrlRegs.PIEIER4.all = 0;
|
||||
PieCtrlRegs.PIEIER5.all = 0;
|
||||
PieCtrlRegs.PIEIER6.all = 0;
|
||||
PieCtrlRegs.PIEIER7.all = 0;
|
||||
PieCtrlRegs.PIEIER8.all = 0;
|
||||
PieCtrlRegs.PIEIER9.all = 0;
|
||||
PieCtrlRegs.PIEIER10.all = 0;
|
||||
PieCtrlRegs.PIEIER11.all = 0;
|
||||
PieCtrlRegs.PIEIER12.all = 0;
|
||||
|
||||
//
|
||||
// Clear all PIEIFR registers
|
||||
//
|
||||
PieCtrlRegs.PIEIFR1.all = 0;
|
||||
PieCtrlRegs.PIEIFR2.all = 0;
|
||||
PieCtrlRegs.PIEIFR3.all = 0;
|
||||
PieCtrlRegs.PIEIFR4.all = 0;
|
||||
PieCtrlRegs.PIEIFR5.all = 0;
|
||||
PieCtrlRegs.PIEIFR6.all = 0;
|
||||
PieCtrlRegs.PIEIFR7.all = 0;
|
||||
PieCtrlRegs.PIEIFR8.all = 0;
|
||||
PieCtrlRegs.PIEIFR9.all = 0;
|
||||
PieCtrlRegs.PIEIFR10.all = 0;
|
||||
PieCtrlRegs.PIEIFR11.all = 0;
|
||||
PieCtrlRegs.PIEIFR12.all = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// EnableInterrupts - This function enables the PIE module and CPU interrupts
|
||||
//
|
||||
void
|
||||
EnableInterrupts()
|
||||
{
|
||||
//
|
||||
// Enable the PIE
|
||||
//
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
|
||||
//
|
||||
// Enables PIE to drive a pulse into the CPU
|
||||
//
|
||||
PieCtrlRegs.PIEACK.all = 0xFFFF;
|
||||
|
||||
//
|
||||
// Enable Interrupts at the CPU level
|
||||
//
|
||||
EINT;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,231 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_PieVect.c
|
||||
//
|
||||
// TITLE: DSP2833x Devices PIE Vector Table Initialization Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
const struct PIE_VECT_TABLE PieVectTableInit =
|
||||
{
|
||||
PIE_RESERVED, // 0 Reserved space
|
||||
PIE_RESERVED, // 1 Reserved space
|
||||
PIE_RESERVED, // 2 Reserved space
|
||||
PIE_RESERVED, // 3 Reserved space
|
||||
PIE_RESERVED, // 4 Reserved space
|
||||
PIE_RESERVED, // 5 Reserved space
|
||||
PIE_RESERVED, // 6 Reserved space
|
||||
PIE_RESERVED, // 7 Reserved space
|
||||
PIE_RESERVED, // 8 Reserved space
|
||||
PIE_RESERVED, // 9 Reserved space
|
||||
PIE_RESERVED, // 10 Reserved space
|
||||
PIE_RESERVED, // 11 Reserved space
|
||||
PIE_RESERVED, // 12 Reserved space
|
||||
|
||||
//
|
||||
// Non-Peripheral Interrupts
|
||||
//
|
||||
INT13_ISR, // XINT13 or CPU-Timer 1
|
||||
INT14_ISR, // CPU-Timer2
|
||||
DATALOG_ISR, // Datalogging interrupt
|
||||
RTOSINT_ISR, // RTOS interrupt
|
||||
EMUINT_ISR, // Emulation interrupt
|
||||
NMI_ISR, // Non-maskable interrupt
|
||||
ILLEGAL_ISR, // Illegal operation TRAP
|
||||
USER1_ISR, // User Defined trap 1
|
||||
USER2_ISR, // User Defined trap 2
|
||||
USER3_ISR, // User Defined trap 3
|
||||
USER4_ISR, // User Defined trap 4
|
||||
USER5_ISR, // User Defined trap 5
|
||||
USER6_ISR, // User Defined trap 6
|
||||
USER7_ISR, // User Defined trap 7
|
||||
USER8_ISR, // User Defined trap 8
|
||||
USER9_ISR, // User Defined trap 9
|
||||
USER10_ISR, // User Defined trap 10
|
||||
USER11_ISR, // User Defined trap 11
|
||||
USER12_ISR, // User Defined trap 12
|
||||
|
||||
//
|
||||
// Group 1 PIE Vectors
|
||||
//
|
||||
SEQ1INT_ISR, // 1.1 ADC
|
||||
SEQ2INT_ISR, // 1.2 ADC
|
||||
rsvd_ISR, // 1.3
|
||||
XINT1_ISR, // 1.4
|
||||
XINT2_ISR, // 1.5
|
||||
ADCINT_ISR, // 1.6 ADC
|
||||
TINT0_ISR, // 1.7 Timer 0
|
||||
WAKEINT_ISR, // 1.8 WD, Low Power
|
||||
|
||||
//
|
||||
// Group 2 PIE Vectors
|
||||
//
|
||||
EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone
|
||||
EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone
|
||||
EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone
|
||||
EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone
|
||||
EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone
|
||||
EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone
|
||||
rsvd_ISR, // 2.7
|
||||
rsvd_ISR, // 2.8
|
||||
|
||||
//
|
||||
// Group 3 PIE Vectors
|
||||
//
|
||||
EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt
|
||||
EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt
|
||||
EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt
|
||||
EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt
|
||||
EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt
|
||||
EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt
|
||||
rsvd_ISR, // 3.7
|
||||
rsvd_ISR, // 3.8
|
||||
|
||||
//
|
||||
// Group 4 PIE Vectors
|
||||
//
|
||||
ECAP1_INT_ISR, // 4.1 ECAP-1
|
||||
ECAP2_INT_ISR, // 4.2 ECAP-2
|
||||
ECAP3_INT_ISR, // 4.3 ECAP-3
|
||||
ECAP4_INT_ISR, // 4.4 ECAP-4
|
||||
ECAP5_INT_ISR, // 4.5 ECAP-5
|
||||
ECAP6_INT_ISR, // 4.6 ECAP-6
|
||||
rsvd_ISR, // 4.7
|
||||
rsvd_ISR, // 4.8
|
||||
|
||||
//
|
||||
// Group 5 PIE Vectors
|
||||
//
|
||||
EQEP1_INT_ISR, // 5.1 EQEP-1
|
||||
EQEP2_INT_ISR, // 5.2 EQEP-2
|
||||
rsvd_ISR, // 5.3
|
||||
rsvd_ISR, // 5.4
|
||||
rsvd_ISR, // 5.5
|
||||
rsvd_ISR, // 5.6
|
||||
rsvd_ISR, // 5.7
|
||||
rsvd_ISR, // 5.8
|
||||
|
||||
//
|
||||
// Group 6 PIE Vectors
|
||||
//
|
||||
SPIRXINTA_ISR, // 6.1 SPI-A
|
||||
SPITXINTA_ISR, // 6.2 SPI-A
|
||||
MRINTA_ISR, // 6.3 McBSP-A
|
||||
MXINTA_ISR, // 6.4 McBSP-A
|
||||
MRINTB_ISR, // 6.5 McBSP-B
|
||||
MXINTB_ISR, // 6.6 McBSP-B
|
||||
rsvd_ISR, // 6.7
|
||||
rsvd_ISR, // 6.8
|
||||
|
||||
//
|
||||
// Group 7 PIE Vectors
|
||||
//
|
||||
DINTCH1_ISR, // 7.1 DMA channel 1
|
||||
DINTCH2_ISR, // 7.2 DMA channel 2
|
||||
DINTCH3_ISR, // 7.3 DMA channel 3
|
||||
DINTCH4_ISR, // 7.4 DMA channel 4
|
||||
DINTCH5_ISR, // 7.5 DMA channel 5
|
||||
DINTCH6_ISR, // 7.6 DMA channel 6
|
||||
rsvd_ISR, // 7.7
|
||||
rsvd_ISR, // 7.8
|
||||
|
||||
//
|
||||
// Group 8 PIE Vectors
|
||||
//
|
||||
I2CINT1A_ISR, // 8.1 I2C
|
||||
I2CINT2A_ISR, // 8.2 I2C
|
||||
rsvd_ISR, // 8.3
|
||||
rsvd_ISR, // 8.4
|
||||
SCIRXINTC_ISR, // 8.5 SCI-C
|
||||
SCITXINTC_ISR, // 8.6 SCI-C
|
||||
rsvd_ISR, // 8.7
|
||||
rsvd_ISR, // 8.8
|
||||
|
||||
//
|
||||
// Group 9 PIE Vectors
|
||||
//
|
||||
SCIRXINTA_ISR, // 9.1 SCI-A
|
||||
SCITXINTA_ISR, // 9.2 SCI-A
|
||||
SCIRXINTB_ISR, // 9.3 SCI-B
|
||||
SCITXINTB_ISR, // 9.4 SCI-B
|
||||
ECAN0INTA_ISR, // 9.5 eCAN-A
|
||||
ECAN1INTA_ISR, // 9.6 eCAN-A
|
||||
ECAN0INTB_ISR, // 9.7 eCAN-B
|
||||
ECAN1INTB_ISR, // 9.8 eCAN-B
|
||||
|
||||
//
|
||||
// Group 10 PIE Vectors
|
||||
//
|
||||
rsvd_ISR, // 10.1
|
||||
rsvd_ISR, // 10.2
|
||||
rsvd_ISR, // 10.3
|
||||
rsvd_ISR, // 10.4
|
||||
rsvd_ISR, // 10.5
|
||||
rsvd_ISR, // 10.6
|
||||
rsvd_ISR, // 10.7
|
||||
rsvd_ISR, // 10.8
|
||||
|
||||
//
|
||||
// Group 11 PIE Vectors
|
||||
//
|
||||
rsvd_ISR, // 11.1
|
||||
rsvd_ISR, // 11.2
|
||||
rsvd_ISR, // 11.3
|
||||
rsvd_ISR, // 11.4
|
||||
rsvd_ISR, // 11.5
|
||||
rsvd_ISR, // 11.6
|
||||
rsvd_ISR, // 11.7
|
||||
rsvd_ISR, // 11.8
|
||||
|
||||
//
|
||||
// Group 12 PIE Vectors
|
||||
//
|
||||
XINT3_ISR, // 12.1
|
||||
XINT4_ISR, // 12.2
|
||||
XINT5_ISR, // 12.3
|
||||
XINT6_ISR, // 12.4
|
||||
XINT7_ISR, // 12.5
|
||||
rsvd_ISR, // 12.6
|
||||
LVF_ISR, // 12.7
|
||||
LUF_ISR, // 12.8
|
||||
};
|
||||
|
||||
//
|
||||
// InitPieVectTable - This function initializes the PIE vector table to a known
|
||||
// state. This function must be executed after boot time.
|
||||
//
|
||||
void
|
||||
InitPieVectTable(void)
|
||||
{
|
||||
int16 i;
|
||||
Uint32 *Source = (void *) &PieVectTableInit;
|
||||
volatile Uint32 *Dest = (void *) &PieVectTable;
|
||||
|
||||
EALLOW;
|
||||
for(i=0; i < 128; i++)
|
||||
{
|
||||
*Dest++ = *Source++;
|
||||
}
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Enable the PIE Vector Table
|
||||
//
|
||||
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,193 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Sci.c
|
||||
//
|
||||
// TITLE: DSP2833x SCI Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//
|
||||
// InitSci - This function initializes the SCI(s) to a known state.
|
||||
//
|
||||
void
|
||||
InitSci(void)
|
||||
{
|
||||
//
|
||||
// Initialize SCI-A
|
||||
//
|
||||
|
||||
//
|
||||
// Initialize SCI-B
|
||||
//
|
||||
|
||||
//
|
||||
// Initialize SCI-C
|
||||
//
|
||||
}
|
||||
|
||||
//
|
||||
// InitSciGpio - This function initializes GPIO to function as SCI-A, SCI-B, or
|
||||
// SCI-C
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// Only one GPIO pin should be enabled for SCITXDA/B operation.
|
||||
// Only one GPIO pin shoudl be enabled for SCIRXDA/B operation.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
void
|
||||
InitSciGpio()
|
||||
{
|
||||
InitSciaGpio();
|
||||
#if DSP28_SCIB
|
||||
InitScibGpio();
|
||||
#endif // if DSP28_SCIB
|
||||
|
||||
#if DSP28_SCIC
|
||||
InitScicGpio();
|
||||
#endif // if DSP28_SCIC
|
||||
}
|
||||
|
||||
//
|
||||
// InitSciaGpio - This function initializes GPIO pins to function as SCI-A pins
|
||||
//
|
||||
void
|
||||
InitSciaGpio()
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA)
|
||||
|
||||
//
|
||||
// Configure SCI-A pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be SCI functional
|
||||
// pins.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 to SCIRXDA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 to SCITXDA
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
#if DSP28_SCIB
|
||||
//
|
||||
// InitScibGpio - This function initializes GPIO pins to function as SCI-B pins
|
||||
//
|
||||
void
|
||||
InitScibGpio()
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; //Enable pull-up for GPIO9 (SCITXDB)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; //Enable pull-up for GPIO14 (SCITXDB)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; //Enable pull-up for GPIO18 (SCITXDB)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; //Enable pull-up for GPIO22 (SCITXDB)
|
||||
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; //Enable pull-up for GPIO11 (SCIRXDB)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; //Enable pull-up for GPIO15 (SCIRXDB)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up for GPIO19 (SCIRXDB)
|
||||
//GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; //Enable pull-up for GPIO23 (SCIRXDB)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB)
|
||||
//GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB)
|
||||
//GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB)
|
||||
|
||||
//
|
||||
// Configure SCI-B pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be SCI functional
|
||||
// pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; //Configure GPIO9 to SCITXDB
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; //Configure GPIO14 to SCITXDB
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; //Configure GPIO18 to SCITXDB
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; //Configure GPIO22 to SCITXDB
|
||||
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; //Configure GPIO11 for SCIRXDB
|
||||
//GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; //Configure GPIO15 for SCIRXDB
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; //Configure GPIO19 for SCIRXDB
|
||||
//GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; //Configure GPIO23 for SCIRXDB
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // if DSP28_SCIB
|
||||
|
||||
#if DSP28_SCIC
|
||||
//
|
||||
// InitScicGpio - This function initializes GPIO pins to function as SCI-C pins
|
||||
//
|
||||
void
|
||||
InitScicGpio()
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
//
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC)
|
||||
GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
// Inputs are synchronized to SYSCLKOUT by default.
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
//
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC)
|
||||
|
||||
//
|
||||
// Configure SCI-C pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be SCI functional
|
||||
// pins.
|
||||
//
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 to SCIRXDC
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 to SCITXDC
|
||||
|
||||
EDIS;
|
||||
}
|
||||
#endif // if DSP28_SCIC
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,113 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Spi.c
|
||||
//
|
||||
// TITLE: DSP2833x SPI Initialization & Support Functions.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//
|
||||
// InitSPI - This function initializes the SPI(s) to a known state.
|
||||
//
|
||||
void
|
||||
InitSpi(void)
|
||||
{
|
||||
//
|
||||
// Initialize SPI-A/B/C/D
|
||||
//
|
||||
}
|
||||
|
||||
//
|
||||
// InitSpiGpio - This function initializes GPIO pins to function as SPI pins
|
||||
//
|
||||
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
|
||||
// peripheral functional pins. By default all pins come up as GPIO
|
||||
// inputs after reset.
|
||||
//
|
||||
// Caution:
|
||||
// For each SPI peripheral
|
||||
// Only one GPIO pin should be enabled for SPISOMO operation.
|
||||
// Only one GPIO pin should be enabled for SPISOMI operation.
|
||||
// Only one GPIO pin should be enabled for SPICLKA operation.
|
||||
// Only one GPIO pin should be enabled for SPISTEA operation.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
void
|
||||
InitSpiGpio()
|
||||
{
|
||||
InitSpiaGpio();
|
||||
}
|
||||
|
||||
//
|
||||
// InitSpiaGpio - This function initializes GPIO poins to function as SPI pins
|
||||
//
|
||||
void
|
||||
InitSpiaGpio()
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable internal pull-up for the selected pins
|
||||
// Pull-ups can be enabled or disabled by the user.
|
||||
// This will enable the pullups for the specified pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; //Enable pull-up on GPIO16 (SPISIMOA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; //Enable pull-up on GPIO17 (SPISOMIA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; //Enable pull-up on GPIO18 (SPICLKA)
|
||||
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; //Enable pull-up on GPIO19 (SPISTEA)
|
||||
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; //Enable pull-up on GPIO54 (SPISIMOA)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; //Enable pull-up on GPIO55 (SPISOMIA)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; //Enable pull-up on GPIO56 (SPICLKA)
|
||||
//GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; //Enable pull-up on GPIO57 (SPISTEA)
|
||||
|
||||
//
|
||||
// Set qualification for selected pins to asynch only
|
||||
// This will select asynch (no qualification) for the selected pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA)
|
||||
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA)
|
||||
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA)
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA)
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA)
|
||||
//GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA)
|
||||
|
||||
//
|
||||
// Configure SPI-A pins using GPIO regs
|
||||
// This specifies which of the possible GPIO pins will be SPI
|
||||
// functional pins.
|
||||
// Comment out other unwanted lines.
|
||||
//
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA
|
||||
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA
|
||||
//GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,422 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_SysCtrl.c
|
||||
//
|
||||
// TITLE: DSP2833x Device System Control Initialization & Support Functions.
|
||||
//
|
||||
// DESCRIPTION: Example initialization of system resources.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // Examples Include File
|
||||
|
||||
//
|
||||
// Functions that will be run from RAM need to be assigned to
|
||||
// a different section. This section will then be mapped to a load and
|
||||
// run address using the linker cmd file.
|
||||
//
|
||||
#pragma CODE_SECTION(InitFlash, "ramfuncs");
|
||||
|
||||
//
|
||||
// InitSysCtrl - This function initializes the System Control registers to a
|
||||
// known state.
|
||||
// - Disables the watchdog
|
||||
// - Set the PLLCR for proper SYSCLKOUT frequency
|
||||
// - Set the pre-scaler for the high and low frequency peripheral clocks
|
||||
// - Enable the clocks to the peripherals
|
||||
//
|
||||
void
|
||||
InitSysCtrl(void)
|
||||
{
|
||||
//
|
||||
// Disable the watchdog
|
||||
//
|
||||
DisableDog();
|
||||
|
||||
//
|
||||
// Initialize the PLL control: PLLCR and DIVSEL
|
||||
// DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
|
||||
//
|
||||
InitPll(DSP28_PLLCR,DSP28_DIVSEL);
|
||||
|
||||
//
|
||||
// Initialize the peripheral clocks
|
||||
//
|
||||
InitPeripheralClocks();
|
||||
}
|
||||
|
||||
//
|
||||
// InitFlash - This function initializes the Flash Control registers
|
||||
// CAUTION
|
||||
// This function MUST be executed out of RAM. Executing it
|
||||
// out of OTP/Flash will yield unpredictable results
|
||||
//
|
||||
void
|
||||
InitFlash(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Enable Flash Pipeline mode to improve performance
|
||||
// of code executed from Flash.
|
||||
//
|
||||
FlashRegs.FOPT.bit.ENPIPE = 1;
|
||||
|
||||
//
|
||||
// CAUTION
|
||||
// Minimum waitstates required for the flash operating
|
||||
// at a given CPU rate must be characterized by TI.
|
||||
// Refer to the datasheet for the latest information.
|
||||
//
|
||||
#if CPU_FRQ_150MHZ
|
||||
//
|
||||
// Set the Paged Waitstate for the Flash
|
||||
//
|
||||
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;
|
||||
|
||||
//
|
||||
// Set the Random Waitstate for the Flash
|
||||
//
|
||||
FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;
|
||||
|
||||
//
|
||||
// Set the Waitstate for the OTP
|
||||
//
|
||||
FlashRegs.FOTPWAIT.bit.OTPWAIT = 8;
|
||||
#endif
|
||||
|
||||
#if CPU_FRQ_100MHZ
|
||||
//
|
||||
// Set the Paged Waitstate for the Flash
|
||||
//
|
||||
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
|
||||
|
||||
//
|
||||
// Set the Random Waitstate for the Flash
|
||||
//
|
||||
FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
|
||||
|
||||
//
|
||||
// Set the Waitstate for the OTP
|
||||
//
|
||||
FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
|
||||
#endif
|
||||
//
|
||||
// CAUTION
|
||||
// ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
|
||||
//
|
||||
FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
|
||||
FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Force a pipeline flush to ensure that the write to
|
||||
// the last register configured occurs before returning.
|
||||
//
|
||||
asm(" RPT #7 || NOP");
|
||||
}
|
||||
|
||||
//
|
||||
// ServiceDog - This function resets the watchdog timer.
|
||||
// Enable this function for using ServiceDog in the application
|
||||
//
|
||||
void
|
||||
ServiceDog(void)
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.WDKEY = 0x0055;
|
||||
SysCtrlRegs.WDKEY = 0x00AA;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// DisableDog - This function disables the watchdog timer.
|
||||
//
|
||||
void
|
||||
DisableDog(void)
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.WDCR= 0x0068;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// InitPll - This function initializes the PLLCR register.
|
||||
//
|
||||
void
|
||||
InitPll(Uint16 val, Uint16 divsel)
|
||||
{
|
||||
//
|
||||
// Make sure the PLL is not running in limp mode
|
||||
//
|
||||
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
|
||||
{
|
||||
//
|
||||
// Missing external clock has been detected
|
||||
// Replace this line with a call to an appropriate
|
||||
// SystemShutdown(); function.
|
||||
//
|
||||
asm(" ESTOP0");
|
||||
}
|
||||
|
||||
//
|
||||
// DIVSEL MUST be 0 before PLLCR can be changed from
|
||||
// 0x0000. It is set to 0 by an external reset XRSn
|
||||
// This puts us in 1/4
|
||||
//
|
||||
if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// Change the PLLCR
|
||||
//
|
||||
if (SysCtrlRegs.PLLCR.bit.DIV != val)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// Before setting PLLCR turn off missing clock detect logic
|
||||
//
|
||||
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
|
||||
SysCtrlRegs.PLLCR.bit.DIV = val;
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Optional: Wait for PLL to lock.
|
||||
// During this time the CPU will switch to OSCCLK/2 until
|
||||
// the PLL is stable. Once the PLL is stable the CPU will
|
||||
// switch to the new PLL value.
|
||||
//
|
||||
// This time-to-lock is monitored by a PLL lock counter.
|
||||
//
|
||||
// Code is not required to sit and wait for the PLL to lock.
|
||||
// However, if the code does anything that is timing critical,
|
||||
// and requires the correct clock be locked, then it is best to
|
||||
// wait until this switching has completed.
|
||||
//
|
||||
|
||||
//
|
||||
// Wait for the PLL lock bit to be set.
|
||||
//
|
||||
|
||||
//
|
||||
// The watchdog should be disabled before this loop, or fed within
|
||||
// the loop via ServiceDog().
|
||||
//
|
||||
|
||||
//
|
||||
// Uncomment to disable the watchdog
|
||||
//
|
||||
DisableDog();
|
||||
|
||||
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
|
||||
{
|
||||
//
|
||||
// Uncomment to service the watchdog
|
||||
//
|
||||
//ServiceDog();
|
||||
}
|
||||
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// If switching to 1/2
|
||||
//
|
||||
if((divsel == 1)||(divsel == 2))
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// NOTE: ONLY USE THIS SETTING IF PLL IS BYPASSED (I.E. PLLCR = 0) OR OFF
|
||||
// If switching to 1/1
|
||||
// * First go to 1/2 and let the power settle
|
||||
// The time required will depend on the system, this is only an example
|
||||
// * Then switch to 1/1
|
||||
//
|
||||
if(divsel == 3)
|
||||
{
|
||||
EALLOW;
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
|
||||
DELAY_US(50L);
|
||||
SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
|
||||
EDIS;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// InitPeripheralClocks - This function initializes the clocks to the
|
||||
// peripheral modules. First the high and low clock prescalers are set
|
||||
// Second the clocks are enabled to each peripheral. To reduce power, leave
|
||||
// clocks to unused peripherals disabled
|
||||
//
|
||||
// Note: If a peripherals clock is not enabled then you cannot
|
||||
// read or write to the registers for that peripheral
|
||||
//
|
||||
void
|
||||
InitPeripheralClocks(void)
|
||||
{
|
||||
EALLOW;
|
||||
|
||||
//
|
||||
// HISPCP/LOSPCP prescale register settings, normally it will be set to
|
||||
// default values
|
||||
//
|
||||
SysCtrlRegs.HISPCP.all = 0x0001;
|
||||
SysCtrlRegs.LOSPCP.all = 0x0002;
|
||||
|
||||
//
|
||||
// XCLKOUT to SYSCLKOUT ratio. By default XCLKOUT = 1/4 SYSCLKOUT
|
||||
// XTIMCLK = SYSCLKOUT/2
|
||||
//
|
||||
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
|
||||
|
||||
//
|
||||
// XCLKOUT = XTIMCLK/2
|
||||
//
|
||||
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
|
||||
|
||||
//
|
||||
// Enable XCLKOUT
|
||||
//
|
||||
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
|
||||
|
||||
//
|
||||
// Peripheral clock enables set for the selected peripherals.
|
||||
// If you are not using a peripheral leave the clock off
|
||||
// to save on power.
|
||||
//
|
||||
// Note: not all peripherals are available on all 2833x derivates.
|
||||
// Refer to the datasheet for your particular device.
|
||||
//
|
||||
// This function is not written to be an example of efficient code.
|
||||
//
|
||||
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
|
||||
|
||||
//
|
||||
// *IMPORTANT*
|
||||
// The ADC_cal function, which copies the ADC calibration values from TI
|
||||
// reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs
|
||||
// automatically in the Boot ROM. If the boot ROM code is bypassed during
|
||||
// the debug process, the following function MUST be called for the ADC to
|
||||
// function according to specification. The clocks to the ADC MUST be
|
||||
// enabled before calling this function.
|
||||
// See the device data manual and/or the ADC Reference
|
||||
// Manual for more information.
|
||||
//
|
||||
ADC_cal();
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 1; // I2C
|
||||
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // SCI-A
|
||||
SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // SCI-B
|
||||
SysCtrlRegs.PCLKCR0.bit.SCICENCLK = 1; // SCI-C
|
||||
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // SPI-A
|
||||
SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK = 1; // McBSP-A
|
||||
SysCtrlRegs.PCLKCR0.bit.MCBSPBENCLK = 1; // McBSP-B
|
||||
SysCtrlRegs.PCLKCR0.bit.ECANAENCLK=1; // eCAN-A
|
||||
SysCtrlRegs.PCLKCR0.bit.ECANBENCLK=1; // eCAN-B
|
||||
|
||||
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
|
||||
SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
|
||||
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
|
||||
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP3ENCLK = 1; // eCAP3
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP4ENCLK = 1; // eCAP4
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP5ENCLK = 1; // eCAP5
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP6ENCLK = 1; // eCAP6
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 1; // eCAP1
|
||||
SysCtrlRegs.PCLKCR1.bit.ECAP2ENCLK = 1; // eCAP2
|
||||
SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK = 1; // eQEP1
|
||||
SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK = 1; // eQEP2
|
||||
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER0ENCLK = 1; // CPU Timer 0
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER1ENCLK = 1; // CPU Timer 1
|
||||
SysCtrlRegs.PCLKCR3.bit.CPUTIMER2ENCLK = 1; // CPU Timer 2
|
||||
|
||||
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1; // DMA Clock
|
||||
SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; // XTIMCLK
|
||||
SysCtrlRegs.PCLKCR3.bit.GPIOINENCLK = 1; // GPIO input clock
|
||||
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with
|
||||
// current password for the DSP. Returns 1 if unlock is successful.
|
||||
//
|
||||
#define STATUS_FAIL 0
|
||||
#define STATUS_SUCCESS 1
|
||||
Uint16
|
||||
CsmUnlock()
|
||||
{
|
||||
volatile Uint16 temp;
|
||||
|
||||
//
|
||||
// Load the key registers with the current password. The 0xFFFF's are dummy
|
||||
// passwords. User should replace them with the correct password for the
|
||||
// DSP.
|
||||
//
|
||||
EALLOW;
|
||||
CsmRegs.KEY0 = 0xFFFF;
|
||||
CsmRegs.KEY1 = 0xFFFF;
|
||||
CsmRegs.KEY2 = 0xFFFF;
|
||||
CsmRegs.KEY3 = 0xFFFF;
|
||||
CsmRegs.KEY4 = 0xFFFF;
|
||||
CsmRegs.KEY5 = 0xFFFF;
|
||||
CsmRegs.KEY6 = 0xFFFF;
|
||||
CsmRegs.KEY7 = 0xFFFF;
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Perform a dummy read of the password locations if they match the key
|
||||
// values, the CSM will unlock
|
||||
//
|
||||
temp = CsmPwl.PSWD0;
|
||||
temp = CsmPwl.PSWD1;
|
||||
temp = CsmPwl.PSWD2;
|
||||
temp = CsmPwl.PSWD3;
|
||||
temp = CsmPwl.PSWD4;
|
||||
temp = CsmPwl.PSWD5;
|
||||
temp = CsmPwl.PSWD6;
|
||||
temp = CsmPwl.PSWD7;
|
||||
|
||||
//
|
||||
// If the CSM unlocked, return succes, otherwise return failure.
|
||||
//
|
||||
if (CsmRegs.CSMSCR.bit.SECURE == 0)
|
||||
{
|
||||
return STATUS_SUCCESS;
|
||||
}
|
||||
else
|
||||
{
|
||||
return STATUS_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// End of file
|
||||
//
|
||||
|
||||
@ -0,0 +1,303 @@
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Xintf.c
|
||||
//
|
||||
// TITLE: DSP2833x Device External Interface Init & Support Functions.
|
||||
//
|
||||
// DESCRIPTION:
|
||||
//
|
||||
// Example initialization function for the external interface (XINTF).
|
||||
// This example configures the XINTF to its default state. For an
|
||||
// example of how this function being used refer to the
|
||||
// examples/run_from_xintf project.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
|
||||
//
|
||||
// Included Files
|
||||
//
|
||||
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
|
||||
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
|
||||
|
||||
//
|
||||
// InitXINTF - This function initializes the External Interface the default
|
||||
// reset state.
|
||||
//
|
||||
// Do not modify the timings of the XINTF while running from the XINTF. Doing
|
||||
// so can yield unpredictable results
|
||||
//
|
||||
void
|
||||
InitXintf(void)
|
||||
{
|
||||
//
|
||||
// This shows how to write to the XINTF registers. The
|
||||
// values used here are the default state after reset.
|
||||
// Different hardware will require a different configuration.
|
||||
//
|
||||
|
||||
//
|
||||
// For an example of an XINTF configuration used with the
|
||||
// F28335 eZdsp, refer to the examples/run_from_xintf project.
|
||||
//
|
||||
|
||||
//
|
||||
// Any changes to XINTF timing should only be made by code
|
||||
// running outside of the XINTF.
|
||||
//
|
||||
|
||||
//
|
||||
// All Zones
|
||||
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
|
||||
//
|
||||
EALLOW;
|
||||
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
|
||||
|
||||
//
|
||||
// No write buffering
|
||||
//
|
||||
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
|
||||
|
||||
//
|
||||
// XCLKOUT is enabled
|
||||
//
|
||||
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
|
||||
|
||||
//
|
||||
// XCLKOUT = XTIMCLK/2
|
||||
//
|
||||
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
|
||||
|
||||
//
|
||||
// Zone 0
|
||||
// When using ready, ACTIVE must be 1 or greater
|
||||
// Lead must always be 1 or greater
|
||||
// Zone write timing
|
||||
//
|
||||
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
|
||||
XintfRegs.XTIMING0.bit.XWRACTIVE = 5;
|
||||
XintfRegs.XTIMING0.bit.XWRTRAIL = 1;
|
||||
|
||||
//
|
||||
// Zone read timing
|
||||
//
|
||||
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
|
||||
XintfRegs.XTIMING0.bit.XRDACTIVE = 5;
|
||||
XintfRegs.XTIMING0.bit.XRDTRAIL = 1;
|
||||
|
||||
//
|
||||
// double all Zone read/write lead/active/trail timing
|
||||
//
|
||||
XintfRegs.XTIMING0.bit.X2TIMING = 1;
|
||||
|
||||
//
|
||||
// Zone will sample XREADY signal
|
||||
//
|
||||
XintfRegs.XTIMING0.bit.USEREADY = 1;
|
||||
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
|
||||
|
||||
//
|
||||
// Size must be either:
|
||||
// 0,1 = x32 or
|
||||
// 1,1 = x16 other values are reserved
|
||||
//
|
||||
XintfRegs.XTIMING0.bit.XSIZE = 3;
|
||||
|
||||
//
|
||||
// Zone 6
|
||||
// When using ready, ACTIVE must be 1 or greater
|
||||
// Lead must always be 1 or greater
|
||||
// Zone write timing
|
||||
//
|
||||
XintfRegs.XTIMING6.bit.XWRLEAD = 3;
|
||||
XintfRegs.XTIMING6.bit.XWRACTIVE = 5;
|
||||
XintfRegs.XTIMING6.bit.XWRTRAIL = 1;
|
||||
|
||||
//
|
||||
// Zone read timing
|
||||
//
|
||||
XintfRegs.XTIMING6.bit.XRDLEAD = 3;
|
||||
XintfRegs.XTIMING6.bit.XRDACTIVE = 5;
|
||||
XintfRegs.XTIMING6.bit.XRDTRAIL = 1;
|
||||
|
||||
//
|
||||
// double all Zone read/write lead/active/trail timing
|
||||
//
|
||||
XintfRegs.XTIMING6.bit.X2TIMING = 1;
|
||||
|
||||
//
|
||||
// Zone will sample XREADY signal
|
||||
//
|
||||
XintfRegs.XTIMING6.bit.USEREADY = 0;
|
||||
XintfRegs.XTIMING6.bit.READYMODE = 0; // sample asynchronous
|
||||
|
||||
//
|
||||
// Size must be either:
|
||||
// 0,1 = x32 or
|
||||
// 1,1 = x16 other values are reserved
|
||||
//
|
||||
XintfRegs.XTIMING6.bit.XSIZE = 3;
|
||||
|
||||
//
|
||||
// Zone 7
|
||||
// When using ready, ACTIVE must be 1 or greater
|
||||
// Lead must always be 1 or greater
|
||||
// Zone write timing
|
||||
//
|
||||
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
|
||||
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
|
||||
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
|
||||
|
||||
//
|
||||
// Zone read timing
|
||||
//
|
||||
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
|
||||
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
|
||||
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
|
||||
|
||||
//
|
||||
// double all Zone read/write lead/active/trail timing
|
||||
//
|
||||
XintfRegs.XTIMING7.bit.X2TIMING = 1;
|
||||
|
||||
//
|
||||
// Zone will sample XREADY signal
|
||||
//
|
||||
XintfRegs.XTIMING7.bit.USEREADY = 1;
|
||||
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
|
||||
|
||||
//
|
||||
// Size must be either:
|
||||
// 0,1 = x32 or
|
||||
// 1,1 = x16 other values are reserved
|
||||
//
|
||||
XintfRegs.XTIMING7.bit.XSIZE = 3;
|
||||
|
||||
//
|
||||
// Bank switching
|
||||
// Assume Zone 7 is slow, so add additional BCYC cycles
|
||||
// when ever switching from Zone 7 to another Zone.
|
||||
// This will help avoid bus contention.
|
||||
//
|
||||
XintfRegs.XBANK.bit.BANK = 7;
|
||||
XintfRegs.XBANK.bit.BCYC = 7;
|
||||
EDIS;
|
||||
|
||||
//
|
||||
// Force a pipeline flush to ensure that the write to the last register
|
||||
// configured occurs before returning.
|
||||
//
|
||||
InitXintf16Gpio();
|
||||
//InitXintf32Gpio();
|
||||
|
||||
asm(" RPT #7 || NOP");
|
||||
}
|
||||
|
||||
//
|
||||
// InitXintf32Gpio -
|
||||
//
|
||||
void
|
||||
InitXintf32Gpio()
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17
|
||||
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16
|
||||
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input
|
||||
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input
|
||||
|
||||
InitXintf16Gpio();
|
||||
}
|
||||
|
||||
//
|
||||
// InitXintf16Gpio -
|
||||
//
|
||||
void
|
||||
InitXintf16Gpio()
|
||||
{
|
||||
EALLOW;
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1
|
||||
GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7
|
||||
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14
|
||||
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0
|
||||
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0
|
||||
GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7
|
||||
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6
|
||||
EDIS;
|
||||
}
|
||||
|
||||
//
|
||||
// End of File
|
||||
//
|
||||
|
||||
@ -0,0 +1,78 @@
|
||||
;// TI File $Revision: /main/4 $
|
||||
;// Checkin $Date: July 30, 2007 10:28:57 $
|
||||
;//###########################################################################
|
||||
;//
|
||||
;// FILE: DSP2833x_usDelay.asm
|
||||
;//
|
||||
;// TITLE: Simple delay function
|
||||
;//
|
||||
;// DESCRIPTION:
|
||||
;//
|
||||
;// This is a simple delay function that can be used to insert a specified
|
||||
;// delay into code.
|
||||
;//
|
||||
;// This function is only accurate if executed from internal zero-waitstate
|
||||
;// SARAM. If it is executed from waitstate memory then the delay will be
|
||||
;// longer then specified.
|
||||
;//
|
||||
;// To use this function:
|
||||
;//
|
||||
;// 1 - update the CPU clock speed in the DSP2833x_Examples.h
|
||||
;// file. For example:
|
||||
;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed
|
||||
;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed
|
||||
;//
|
||||
;// 2 - Call this function by using the DELAY_US(A) macro
|
||||
;// that is defined in the DSP2833x_Examples.h file. This macro
|
||||
;// will convert the number of microseconds specified
|
||||
;// into a loop count for use with this function.
|
||||
;// This count will be based on the CPU frequency you specify.
|
||||
;//
|
||||
;// 3 - For the most accurate delay
|
||||
;// - Execute this function in 0 waitstate RAM.
|
||||
;// - Disable interrupts before calling the function
|
||||
;// If you do not disable interrupts, then think of
|
||||
;// this as an "at least" delay function as the actual
|
||||
;// delay may be longer.
|
||||
;//
|
||||
;// The C assembly call from the DELAY_US(time) macro will
|
||||
;// look as follows:
|
||||
;//
|
||||
;// extern void Delay(long LoopCount);
|
||||
;//
|
||||
;// MOV AL,#LowLoopCount
|
||||
;// MOV AH,#HighLoopCount
|
||||
;// LCR _Delay
|
||||
;//
|
||||
;// Or as follows (if count is less then 16-bits):
|
||||
;//
|
||||
;// MOV ACC,#LoopCount
|
||||
;// LCR _Delay
|
||||
;//
|
||||
;//
|
||||
;//###########################################################################
|
||||
;// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
;// $Release Date: November 1, 2016 $
|
||||
;// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
;// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
;//###########################################################################
|
||||
|
||||
.def _DSP28x_usDelay
|
||||
.sect "ramfuncs"
|
||||
|
||||
.global __DSP28x_usDelay
|
||||
_DSP28x_usDelay:
|
||||
SUB ACC,#1
|
||||
BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0
|
||||
LRETR
|
||||
|
||||
;There is a 9/10 cycle overhead and each loop
|
||||
;takes five cycles. The LoopCount is given by
|
||||
;the following formula:
|
||||
; DELAY_CPU_CYCLES = 9 + 5*LoopCount
|
||||
; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
|
||||
; The macro DELAY_US(A) performs this calculation for you
|
||||
;
|
||||
;//===========================================================================
|
||||
;// End of file.
|
||||
;//===========================================================================
|
||||
@ -0,0 +1,89 @@
|
||||
#include "DSP2833x_Device.h"
|
||||
#include "DSP28x_Project.h"
|
||||
#include "Protocol/CAN.h"
|
||||
#include "Protocol/CAN_data.h"
|
||||
#include "Protocol/DigitalIO.h"
|
||||
#include "Protocol/MemoryMap.h"
|
||||
#include "Periphery.h"
|
||||
|
||||
Periphery::Periphery() :
|
||||
_canb(canSpace::CANA),
|
||||
_digitalIO(),
|
||||
_zone6_ptr(reinterpret_cast<Uint16*>(0x100000)),
|
||||
_modbusSettingsMsg(),
|
||||
_modbusInit(false)
|
||||
{
|
||||
_softVersion.DSP = 202;
|
||||
_softVersion.CPLD = 0;
|
||||
}
|
||||
|
||||
|
||||
void Periphery::config(){
|
||||
|
||||
//--------------------------------------Init CAN interface----------------------------------------------------------
|
||||
_canb.initGpio();
|
||||
_canb.config();
|
||||
|
||||
// Data Frame MBOX
|
||||
_canb.configRxMBox(canSpace::MODBUS_SETTINGS_MBOX, canSpace::MsgID(0x0), canSpace::MsgCtrlReg(0x6)); // Modbus settings
|
||||
// _canb.configTxMBox(canSpace::MODBUS_DATA_COMM_TO_CPU_MBOX, canSpace::MsgID(0x29), canSpace::MsgCtrlReg(0x26)); // Send Modbus data to CPU
|
||||
// _canb.configRxMBox(canSpace::MODBUS_DATA_CPU_TO_COMM_MBOX, canSpace::MsgID(0x28), canSpace::MsgCtrlReg(0x6)); // Receive Modbus data from CPU
|
||||
_canb.configTxMBox(canSpace::DIGITAL_INPUT_MBOX, canSpace::MsgID(0x30), canSpace::MsgCtrlReg(0x2)); // Receive DI
|
||||
_canb.configRxMBox(canSpace::DIGITAL_OUTPUT_MBOX, canSpace::MsgID(0x31), canSpace::MsgCtrlReg(0x2)); // Send DO
|
||||
|
||||
// Remote frame MBOX
|
||||
_canb.configTxMBox(canSpace::COMM_VERSION_MBOX, canSpace::MsgID(0x1, false, true), canSpace::MsgCtrlReg(0));
|
||||
|
||||
// Interrupts
|
||||
_canb.configSystemIsr(canSpace::I0EN_ENABLE |
|
||||
canSpace::EPIM_ENABLE | canSpace::WLIM_ENABLE | canSpace::AAIM_ENABLE);
|
||||
|
||||
|
||||
//--------------------------------------Init XINTF interface----------------------------------------------------------
|
||||
InitXintf();
|
||||
|
||||
|
||||
//---------------------------------------Init DIO interface----------------------------------------------------------
|
||||
_digitalIO.setup(_zone6_ptr);
|
||||
_digitalIO.setMemoryOffset(interface::DISCRETE_DATA_OFFSET);
|
||||
|
||||
}
|
||||
|
||||
|
||||
Uint16 Periphery::getVersionFPGA(){
|
||||
Uint16 data;
|
||||
data = *_zone6_ptr + interface::SOFT_VERSION_OFFSET;
|
||||
return data;
|
||||
}
|
||||
|
||||
|
||||
void Periphery::updateVersionFPGA(){
|
||||
_softVersion.CPLD = getVersionFPGA() & 0x3FF; // no more than 1023 (9.9.9) should be limit
|
||||
_message.mdl.word.LOW_WORD = _softVersion.DSP;
|
||||
_message.mdl.word.HI_WORD = _softVersion.CPLD;
|
||||
_canb.updateTXMessage(canSpace::COMM_VERSION_MBOX, _message);
|
||||
}
|
||||
|
||||
|
||||
void Periphery::processDigitalInput(){
|
||||
Uint16 data = 0;
|
||||
_digitalIO.readDigitalIO(data);
|
||||
_canb.transmitMsg(canSpace::DIGITAL_INPUT_MBOX, (data));
|
||||
}
|
||||
|
||||
|
||||
void Periphery::processDigitalOutput(){
|
||||
if(_canb.isNewMessage(canSpace::DIGITAL_OUTPUT_MBOX)){
|
||||
_canb.receiveMsg(canSpace::DIGITAL_OUTPUT_MBOX, _message);
|
||||
Uint16 data = _message.mdl.word.LOW_WORD;
|
||||
_digitalIO.writeDigitalIO(data);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void Periphery::initExternalModbus(){
|
||||
if (!_modbusInit && (_canb.isNewMessage(canSpace::MODBUS_SETTINGS_MBOX))) {
|
||||
_canb.receiveMsg(canSpace::MODBUS_SETTINGS_MBOX, _modbusSettingsMsg);
|
||||
_modbusInit = true; // TODO modbus init function must be here
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,40 @@
|
||||
#pragma once
|
||||
|
||||
#include "DSP28x_Project.h"
|
||||
#include "DSP2833x_Device.h"
|
||||
#include "Protocol/CAN.h"
|
||||
#include "Protocol/CAN_data.h"
|
||||
#include "Protocol/DigitalIO.h"
|
||||
#include "Protocol/MemoryMap.h"
|
||||
|
||||
|
||||
struct SoftwareVersion{
|
||||
Uint16 DSP;
|
||||
Uint16 CPLD;
|
||||
};
|
||||
|
||||
class Periphery{
|
||||
public:
|
||||
Periphery();
|
||||
void config();
|
||||
Uint16 getVersionFPGA();
|
||||
void updateVersionFPGA();
|
||||
void processDigitalInput();
|
||||
void processDigitalOutput();
|
||||
void initExternalModbus();
|
||||
void processExternalModbus(); // TODO
|
||||
void processCPUModbus(); // TODO
|
||||
|
||||
private:
|
||||
canSpace::CAN _canb;
|
||||
interface::DigitalIO _digitalIO;
|
||||
Uint16* _zone6_ptr;
|
||||
|
||||
SoftwareVersion _softVersion;
|
||||
canSpace::CANMessage _modbusSettingsMsg;
|
||||
canSpace::CANMessage _message;
|
||||
bool _modbusInit;
|
||||
|
||||
Uint16 tempIn;
|
||||
Uint16 tempOut;
|
||||
};
|
||||
@ -0,0 +1,285 @@
|
||||
#include "CAN.h"
|
||||
#include "DSP2833x_Device.h"
|
||||
#include "DSP2833x_ECan.h"
|
||||
|
||||
namespace canSpace {
|
||||
|
||||
void CAN::transmitMsg(Uint16 boxNumber, const CANMessage& message){
|
||||
if (boxNumber > 31) return;
|
||||
|
||||
Uint32 mboxControl(0);
|
||||
mboxControl = 1ul << boxNumber;
|
||||
|
||||
volatile MBOX* p_MailBox(0);
|
||||
p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
|
||||
|
||||
p_MailBox->MDH.all = 0x0;
|
||||
p_MailBox->MDL.all = 0x0;
|
||||
|
||||
// p_MailBox->MSGCTRL.bit.DLC = message.dataLength;
|
||||
p_MailBox->MDH.all = message.mdh.all;
|
||||
p_MailBox->MDL.all = message.mdl.all;
|
||||
|
||||
// Set TRS for mailbox
|
||||
CanShadow_.CANTRS.all = 0;
|
||||
CanShadow_.CANTRS.all |= mboxControl;
|
||||
p_CanRegs_->CANTRS.all = CanShadow_.CANTRS.all;
|
||||
|
||||
// Wait for TA bit to be set
|
||||
// do { CanShadow_.CANTA.all = p_CanRegs_->CANTA.all; }
|
||||
// while((CanShadow_.CANTA.all & mboxControl) == 0 );
|
||||
|
||||
// // Clear TA (transmit acknowledge bit)
|
||||
// CanShadow_.CANTA.all = 0;
|
||||
// CanShadow_.CANTA.all |= mboxControl;
|
||||
// p_CanRegs_->CANTA.all = CanShadow_.CANTA.all;
|
||||
}
|
||||
|
||||
|
||||
void CAN::transmitMsg(Uint16 boxNumber, const Uint64& message){
|
||||
if (boxNumber > 31) return;
|
||||
|
||||
Uint32 mboxControl(0);
|
||||
mboxControl = 1ul << boxNumber;
|
||||
|
||||
volatile MBOX* p_MailBox(0);
|
||||
p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
|
||||
|
||||
p_MailBox->MDH.all = 0x0;
|
||||
p_MailBox->MDL.all = 0x0;
|
||||
|
||||
p_MailBox->MDH.all = message >> 32;
|
||||
p_MailBox->MDL.all = message;
|
||||
|
||||
// Set TRS for mailbox
|
||||
CanShadow_.CANTRS.all = 0;
|
||||
CanShadow_.CANTRS.all |= mboxControl;
|
||||
p_CanRegs_->CANTRS.all = CanShadow_.CANTRS.all;
|
||||
|
||||
// Wait for TA bit to be set
|
||||
// do { CanShadow_.CANTA.all = p_CanRegs_->CANTA.all; }
|
||||
// while((CanShadow_.CANTA.all & mboxControl) == 0 );
|
||||
|
||||
// Clear TA (transmit acknowledge bit)
|
||||
// CanShadow_.CANTA.all = 0;
|
||||
// CanShadow_.CANTA.all |= mboxControl;
|
||||
// p_CanRegs_->CANTA.all = CanShadow_.CANTA.all;
|
||||
}
|
||||
|
||||
|
||||
void CAN::transmitMsg(Uint16 boxNumber, const Uint64& message, const Uint16 dlc){
|
||||
if (boxNumber > 31) return;
|
||||
|
||||
Uint32 mboxControl(0);
|
||||
mboxControl = 1ul << boxNumber;
|
||||
|
||||
volatile MBOX* p_MailBox(0);
|
||||
p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
|
||||
|
||||
p_MailBox->MDH.all = 0x0;
|
||||
p_MailBox->MDL.all = 0x0;
|
||||
|
||||
p_MailBox->MSGCTRL.bit.DLC = dlc;
|
||||
p_MailBox->MDH.all = message >> 32;
|
||||
p_MailBox->MDL.all = message;
|
||||
|
||||
// Set TRS for mailbox
|
||||
CanShadow_.CANTRS.all = 0;
|
||||
CanShadow_.CANTRS.all |= mboxControl;
|
||||
p_CanRegs_->CANTRS.all = CanShadow_.CANTRS.all;
|
||||
|
||||
// Wait for TA bit to be set
|
||||
// do { CanShadow_.CANTA.all = p_CanRegs_->CANTA.all; }
|
||||
// while((CanShadow_.CANTA.all & mboxControl) == 0 );
|
||||
|
||||
// Clear TA (transmit acknowledge bit)
|
||||
// CanShadow_.CANTA.all = 0;
|
||||
// CanShadow_.CANTA.all |= mboxControl;
|
||||
// p_CanRegs_->CANTA.all = CanShadow_.CANTA.all;
|
||||
}
|
||||
|
||||
|
||||
void CAN::updateTXMessage(Uint16 boxNumber, const CANMessage& message){ // TODO check trs bit and set it at the end if it was here. Once the TRS bit is set for a mailbox and then data is changed in the mailbox using the CDR
|
||||
// bit, the CAN module fails to transmit the new data and transmits the old data instead. To avoid this,
|
||||
// reset transmission in that mailbox using the TRRn bit and set the TRSn bit again. The new data is
|
||||
// then transmitted.
|
||||
if (boxNumber > 31) return;
|
||||
|
||||
volatile MBOX* p_MailBox(0);
|
||||
p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
|
||||
|
||||
// Set change data request (CDR bit + MBOX number)
|
||||
p_CanRegs_->CANMC.all |= (128 + boxNumber);
|
||||
|
||||
// TODO Add lenght changing?
|
||||
p_MailBox->MDL.all = message.mdl.all;
|
||||
p_MailBox->MDH.all = message.mdh.all;
|
||||
|
||||
CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
|
||||
CanShadow_.CANMC.bit.CDR = 0;
|
||||
p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
|
||||
}
|
||||
|
||||
|
||||
void CAN::updateTXMessage(Uint16 boxNumber, const Uint64& message){ // TODO check trs bit and set it at the end if it was here. Once the TRS bit is set for a mailbox and then data is changed in the mailbox using the CDR
|
||||
// bit, the CAN module fails to transmit the new data and transmits the old data instead. To avoid this,
|
||||
// reset transmission in that mailbox using the TRRn bit and set the TRSn bit again. The new data is
|
||||
// then transmitted.
|
||||
if (boxNumber > 31) return;
|
||||
|
||||
volatile MBOX* p_MailBox(0);
|
||||
p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
|
||||
|
||||
// Set change data request (CDR bit + MBOX number)
|
||||
p_CanRegs_->CANMC.all |= (128 + boxNumber);
|
||||
|
||||
// TODO Add lenght changing?
|
||||
p_MailBox->MDL.all = message;
|
||||
p_MailBox->MDH.all = message >> 32;
|
||||
|
||||
CanShadow_.CANMC.all = p_CanRegs_->CANMC.all;
|
||||
CanShadow_.CANMC.bit.CDR = 0;
|
||||
p_CanRegs_->CANMC.all = CanShadow_.CANMC.all;
|
||||
}
|
||||
|
||||
|
||||
void CAN::sendRemoteRequest(Uint16 boxNumber){
|
||||
if (boxNumber > 31) return;
|
||||
|
||||
volatile MBOX* p_MailBox(0);
|
||||
p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
|
||||
|
||||
Uint32 mboxControl(0);
|
||||
mboxControl = 1ul << boxNumber;
|
||||
|
||||
// Mailbox disable
|
||||
CanShadow_.CANME.all = p_CanRegs_->CANME.all;
|
||||
CanShadow_.CANME.all &= ~(mboxControl);
|
||||
p_CanRegs_->CANME.all = CanShadow_.CANME.all;
|
||||
|
||||
p_MailBox->MSGCTRL.bit.RTR = 1;
|
||||
|
||||
// Mailbox enable
|
||||
CanShadow_.CANME.all = p_CanRegs_->CANME.all;
|
||||
CanShadow_.CANME.all |= mboxControl;
|
||||
p_CanRegs_->CANME.all = CanShadow_.CANME.all;
|
||||
|
||||
// Set TRS for mailbox
|
||||
CanShadow_.CANTRS.all = 0;
|
||||
CanShadow_.CANTRS.all |= mboxControl;
|
||||
p_CanRegs_->CANTRS.all = CanShadow_.CANTRS.all;
|
||||
}
|
||||
|
||||
|
||||
int16 CAN::receiveMsg(Uint16 boxNumber, CANMessage& rxMessage){ // TODO faults just return -1
|
||||
if (boxNumber > 31) { return -1; }
|
||||
|
||||
Uint32 mboxControl(0);
|
||||
mboxControl = 1ul << boxNumber;
|
||||
|
||||
volatile MBOX* p_MailBox(0);
|
||||
p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
|
||||
|
||||
bool isNewMessageInBox = p_CanRegs_->CANRMP.all & mboxControl;
|
||||
if(!isNewMessageInBox) return -2;
|
||||
|
||||
p_CanRegs_->CANRMP.all &= mboxControl;
|
||||
|
||||
rxMessage.dataLength = p_MailBox->MSGCTRL.all;
|
||||
rxMessage.mdl.all = p_MailBox->MDL.all;
|
||||
rxMessage.mdh.all = p_MailBox->MDH.all;
|
||||
|
||||
bool newMessage;
|
||||
bool lostMessage;
|
||||
|
||||
newMessage = p_CanRegs_->CANRMP.all & mboxControl;
|
||||
lostMessage = p_CanRegs_->CANRML.all & mboxControl;
|
||||
|
||||
if(newMessage || lostMessage) {
|
||||
return -3;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int16 CAN::receiveMsg(Uint16 boxNumber, Uint64& rxMessage){ // TODO faults just return -1
|
||||
if (boxNumber > 31) { return -1; }
|
||||
|
||||
Uint32 mboxControl(0);
|
||||
mboxControl = 1ul << boxNumber;
|
||||
|
||||
volatile MBOX* p_MailBox(0);
|
||||
p_MailBox = &(p_CanMBoxes_->MBOX0) + boxNumber;
|
||||
|
||||
bool isNewMessageInBox = p_CanRegs_->CANRMP.all & mboxControl;
|
||||
if(!isNewMessageInBox) return -2;
|
||||
|
||||
p_CanRegs_->CANRMP.all &= mboxControl;
|
||||
|
||||
rxMessage = p_MailBox->MDH.all;
|
||||
rxMessage = rxMessage << 32;
|
||||
rxMessage = p_MailBox->MDL.all;
|
||||
|
||||
bool newMessage;
|
||||
bool lostMessage;
|
||||
|
||||
newMessage = p_CanRegs_->CANRMP.all & mboxControl;
|
||||
lostMessage = p_CanRegs_->CANRML.all & mboxControl;
|
||||
|
||||
if(newMessage || lostMessage) {
|
||||
return -3;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
bool CAN::isNewMessage(){
|
||||
return static_cast<bool>(p_CanRegs_->CANRMP.all);
|
||||
}
|
||||
|
||||
|
||||
bool CAN::isNewMessage(Uint16 boxNumber){
|
||||
if (boxNumber > 31) { return 0; }
|
||||
|
||||
Uint32 mboxControl(0);
|
||||
mboxControl = 1ul << boxNumber;
|
||||
|
||||
bool isNewMessageInBox = p_CanRegs_->CANRMP.all & mboxControl;
|
||||
return isNewMessageInBox;
|
||||
}
|
||||
|
||||
|
||||
void CAN::resetTimeStampCounter(){
|
||||
EALLOW;
|
||||
ECanbRegs.CANTSC = 0;
|
||||
EDIS;
|
||||
}
|
||||
|
||||
|
||||
void CAN::setTimeOutValue(Uint16 boxNumber, Uint32 canBitsNumber){
|
||||
if (boxNumber > 31) { return; }
|
||||
|
||||
volatile Uint32* p_MailBox(0);
|
||||
p_MailBox = &(p_CanMotoRegs_->MOTO0) + boxNumber;
|
||||
|
||||
*p_MailBox = canBitsNumber;
|
||||
}
|
||||
|
||||
|
||||
bool CAN::isTimeOut(Uint16 boxNumber){
|
||||
bool mBOXTimeOut = false;
|
||||
mBOXTimeOut = p_CanRegs_->CANTOS.all & (1ul << boxNumber);
|
||||
return mBOXTimeOut;
|
||||
}
|
||||
|
||||
|
||||
void CAN::clearTimeOutFlag(Uint16 boxNumber){
|
||||
Uint32 clearFlag = 0;
|
||||
clearFlag = 1ul << boxNumber;
|
||||
p_CanRegs_->CANTOS.all = clearFlag;
|
||||
}
|
||||
|
||||
|
||||
} // canSpace
|
||||
@ -0,0 +1,142 @@
|
||||
#pragma once
|
||||
|
||||
#include "F28335/DSP28x_Project.h"
|
||||
#include "F28335/DSP2833x_Device.h"
|
||||
|
||||
namespace canSpace {
|
||||
|
||||
enum CAN_VARIANT{
|
||||
CANA,
|
||||
CANB
|
||||
};
|
||||
|
||||
enum configFlags{
|
||||
NONE = 0,
|
||||
MSB_ENABLE = 1u << 0,
|
||||
STM_ENABLE = 1u << 1
|
||||
};
|
||||
|
||||
|
||||
enum configSystemIsrFlags{
|
||||
I0EN_ENABLE = 1ul,
|
||||
I1EN_ENABLE = 1ul << 1,
|
||||
GIL_ENABLE = 1ul << 2,
|
||||
WLIM_ENABLE = 1ul << 8,
|
||||
EPIM_ENABLE = 1ul << 9,
|
||||
BOIM_ENABLE = 1ul << 10,
|
||||
RMLIM_ENABLE = 1ul << 11,
|
||||
WUIM_ENABLE = 1ul << 12,
|
||||
WDIM_ENABLE = 1ul << 13,
|
||||
AAIM_ENABLE = 1ul << 14,
|
||||
TCOM_ENABLE = 1ul << 16,
|
||||
MTOM_ENABLE = 1ul << 17
|
||||
};
|
||||
|
||||
|
||||
// eCAN Message Control Register (MSGCTRL) bit definitions
|
||||
struct MsgCtrlBits { // bits description
|
||||
Uint16 DLC:4; // 0:3
|
||||
Uint16 RTR:1; // 4
|
||||
Uint16 OPC:1; // 1
|
||||
Uint16 rsvd1:2; // 7:6 reserved
|
||||
Uint16 TPL:5; // 12:8
|
||||
Uint16 rsvd2:3; // 15:13 reserved
|
||||
};
|
||||
|
||||
|
||||
union MsgCtrlReg {
|
||||
Uint16 all;
|
||||
struct MsgCtrlBits bit;
|
||||
|
||||
MsgCtrlReg(Uint16 configData = 0){
|
||||
all = configData;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
struct MsgID_Bits { // bits description
|
||||
Uint16 EXTMSGID_L:16; // 0:15
|
||||
Uint16 EXTMSGID_H:2; // 16:17
|
||||
Uint16 STDMSGID:11; // 18:28
|
||||
Uint16 AAM:1; // 29
|
||||
Uint16 AME:1; // 30
|
||||
Uint16 IDE:1; // 31
|
||||
};
|
||||
|
||||
// Allow access to the bit fields or entire register
|
||||
union MsgID {
|
||||
Uint32 all;
|
||||
struct MsgID_Bits bit;
|
||||
|
||||
MsgID(Uint32 boxID = 0xAAA, bool isExtendedID = false, bool isAAM = false, bool isAME = false) {
|
||||
if(!isExtendedID){
|
||||
bit.STDMSGID = boxID;
|
||||
bit.EXTMSGID_H = 0;
|
||||
bit.EXTMSGID_L = 0;
|
||||
}
|
||||
else{ all = boxID; }
|
||||
|
||||
bit.IDE = isExtendedID;
|
||||
bit.AAM = isAAM;
|
||||
bit.AME = isAME;
|
||||
}
|
||||
|
||||
MsgID(const MsgID& init) {
|
||||
all = init.all;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
struct CANMessage {
|
||||
Uint16 dataLength;
|
||||
union CANMDL_REG mdl;
|
||||
union CANMDH_REG mdh;
|
||||
|
||||
CANMessage(){
|
||||
mdl.all = 0;
|
||||
mdh.all = 0;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
class CAN{
|
||||
public:
|
||||
CAN(CAN_VARIANT canVariant);
|
||||
|
||||
void initGpio();
|
||||
void config(Uint16 baudrate = 1000, Uint16 flags = 0);
|
||||
void configTxMBox(Uint16 boxNumber, const MsgID& configID, const MsgCtrlReg& configCtrlReg);
|
||||
void configRxMBox(Uint16 boxNumber, const MsgID& configID, const MsgCtrlReg& configCtrlReg);
|
||||
void configSystemIsr(Uint32 flags);
|
||||
void configMBoxIsr(Uint16 boxNumber);
|
||||
|
||||
bool isNewMessage();
|
||||
bool isNewMessage(Uint16 boxNumber);
|
||||
|
||||
void transmitMsg(Uint16 boxNumber, const CANMessage& message);
|
||||
void transmitMsg(Uint16 boxNumber, const Uint64& message);
|
||||
void transmitMsg(Uint16 boxNumber, const Uint64& message, const Uint16 dlc);
|
||||
void updateTXMessage(Uint16 boxNumber, const CANMessage& message);
|
||||
void updateTXMessage(Uint16 boxNumber, const Uint64& message);
|
||||
void sendRemoteRequest(Uint16 boxNumber);
|
||||
int16 receiveMsg(Uint16 boxNumber, CANMessage& rxMessage);
|
||||
int16 receiveMsg(Uint16 boxNumber, Uint64& rxMessage);
|
||||
|
||||
void enableTimeOutControl(Uint16 boxNumber);
|
||||
void disableTimeOutControl(Uint16 boxNumber);
|
||||
void resetTimeStampCounter();
|
||||
void setTimeOutValue(Uint16 boxNumber, Uint32 canBitsNumber);
|
||||
bool isTimeOut(Uint16 boxNumber);
|
||||
void clearTimeOutFlag(Uint16 boxNumber);
|
||||
|
||||
private:
|
||||
CAN_VARIANT canPort;
|
||||
volatile ECAN_REGS* p_CanRegs_;
|
||||
ECAN_REGS CanShadow_;
|
||||
volatile ECAN_MBOXES* p_CanMBoxes_;
|
||||
volatile MOTO_REGS* p_CanMotoRegs_;
|
||||
volatile MOTS_REGS* p_CanMotsRegs_;
|
||||
};
|
||||
|
||||
|
||||
} // canSpace
|
||||
@ -0,0 +1,17 @@
|
||||
#pragma once
|
||||
|
||||
namespace canSpace {
|
||||
|
||||
enum MBOX_NUMBERS {
|
||||
MODBUS_SETTINGS_MBOX = 0,
|
||||
COMM_VERSION_MBOX = 1,
|
||||
MODBUS_DATA_COMM_TO_CPU_RSV2_MBOX = 26,
|
||||
MODBUS_DATA_COMM_TO_CPU_RSV1_MBOX = 27,
|
||||
MODBUS_DATA_CPU_TO_COMM_MBOX = 28,
|
||||
MODBUS_DATA_COMM_TO_CPU_MBOX = 29,
|
||||
DIGITAL_INPUT_MBOX = 30,
|
||||
DIGITAL_OUTPUT_MBOX = 31
|
||||
};
|
||||
|
||||
|
||||
}
|
||||
@ -0,0 +1,41 @@
|
||||
#include "DigitalIO.h"
|
||||
|
||||
namespace interface{
|
||||
|
||||
DigitalIO::DigitalIO():
|
||||
m_pointer(0)
|
||||
{}
|
||||
|
||||
|
||||
void DigitalIO::setup(Uint16 *memzone){
|
||||
m_pointer = memzone;// + OFFSET_DATA_DISCRETE_IO;
|
||||
}
|
||||
|
||||
|
||||
void DigitalIO::setMemoryOffset(Uint16 offset){
|
||||
m_pointer += offset;
|
||||
}
|
||||
|
||||
|
||||
void DigitalIO::readDigitalIO(Uint16& data){
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
data = *m_pointer;
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
}
|
||||
|
||||
|
||||
void DigitalIO::writeDigitalIO(Uint16& data) const{
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
*m_pointer = data;
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
asm(" NOP");
|
||||
}
|
||||
|
||||
} // interface
|
||||
@ -0,0 +1,63 @@
|
||||
#pragma once
|
||||
|
||||
#include "DSP28x_Project.h"
|
||||
|
||||
namespace interface
|
||||
{
|
||||
|
||||
struct DigitalIODataBitField
|
||||
{
|
||||
Uint16 b00: 1;
|
||||
Uint16 b01: 1;
|
||||
Uint16 b02: 1;
|
||||
Uint16 b03: 1;
|
||||
Uint16 b04: 1;
|
||||
Uint16 b05: 1;
|
||||
Uint16 b06: 1;
|
||||
Uint16 b07: 1;
|
||||
Uint16 b08: 1;
|
||||
Uint16 b09: 1;
|
||||
Uint16 b10: 1;
|
||||
Uint16 b11: 1;
|
||||
Uint16 b12: 1;
|
||||
Uint16 b13: 1;
|
||||
Uint16 b14: 1;
|
||||
Uint16 b15: 1;
|
||||
};
|
||||
|
||||
|
||||
union DigitalIODataRegister
|
||||
{
|
||||
Uint16 all;
|
||||
DigitalIODataBitField bit;
|
||||
DigitalIODataRegister():
|
||||
all(0)
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
struct DigitalIOData
|
||||
{
|
||||
DigitalIODataRegister input;
|
||||
DigitalIODataRegister output;
|
||||
DigitalIOData():
|
||||
input(),
|
||||
output()
|
||||
{}
|
||||
};
|
||||
|
||||
|
||||
class DigitalIO {
|
||||
public:
|
||||
DigitalIO();
|
||||
void setup(Uint16 *memzone);
|
||||
void setMemoryOffset(Uint16 offset);
|
||||
|
||||
void readDigitalIO(Uint16& data);
|
||||
void writeDigitalIO(Uint16& data) const;
|
||||
|
||||
private:
|
||||
Uint16 *m_pointer;
|
||||
};
|
||||
|
||||
} // interface
|
||||
@ -0,0 +1,11 @@
|
||||
#pragma once
|
||||
|
||||
namespace interface {
|
||||
|
||||
enum MemoryOffset {
|
||||
SOFT_VERSION_OFFSET = static_cast<Uint16>(0x0),
|
||||
DISCRETE_DATA_OFFSET = static_cast<Uint16>(0xA),
|
||||
PROFIBUS_OFFSET = static_cast<Uint16>(0x14)
|
||||
};
|
||||
|
||||
}
|
||||
@ -0,0 +1,177 @@
|
||||
/*
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: 28335_RAM_lnk.cmd
|
||||
//
|
||||
// TITLE: Linker Command File For 28335 examples that run out of RAM
|
||||
//
|
||||
// This ONLY includes all SARAM blocks on the 28335 device.
|
||||
// This does not include flash or OTP.
|
||||
//
|
||||
// Keep in mind that L0 and L1 are protected by the code
|
||||
// security module.
|
||||
//
|
||||
// What this means is in most cases you will want to move to
|
||||
// another memory map file which has more memory defined.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
*/
|
||||
|
||||
/* ======================================================
|
||||
// For Code Composer Studio V2.2 and later
|
||||
// ---------------------------------------
|
||||
// In addition to this memory linker command file,
|
||||
// add the header linker command file directly to the project.
|
||||
// The header linker command file is required to link the
|
||||
// peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in <base>\DSP2833x_Headers\cmd
|
||||
//
|
||||
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
|
||||
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
|
||||
========================================================= */
|
||||
|
||||
/* ======================================================
|
||||
// For Code Composer Studio prior to V2.2
|
||||
// --------------------------------------
|
||||
// 1) Use one of the following -l statements to include the
|
||||
// header linker command file in the project. The header linker
|
||||
// file is required to link the peripheral structures to the proper
|
||||
// locations within the memory map */
|
||||
|
||||
/* Uncomment this line to include file only for non-BIOS applications */
|
||||
/* -l DSP2833x_Headers_nonBIOS.cmd */
|
||||
|
||||
/* Uncomment this line to include file only for BIOS applications */
|
||||
/* -l DSP2833x_Headers_BIOS.cmd */
|
||||
|
||||
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
|
||||
library search path under project->build options, linker tab,
|
||||
library search path (-i).
|
||||
/*========================================================= */
|
||||
|
||||
/* Define the memory block start/length for the F28335
|
||||
PAGE 0 will be used to organize program sections
|
||||
PAGE 1 will be used to organize data sections
|
||||
|
||||
Notes:
|
||||
Memory blocks on F28335 are uniform (ie same
|
||||
physical memory) in both PAGE 0 and PAGE 1.
|
||||
That is the same memory region should not be
|
||||
defined for both PAGE 0 and PAGE 1.
|
||||
Doing so will result in corruption of program
|
||||
and/or data.
|
||||
|
||||
L0/L1/L2 and L3 memory blocks are mirrored - that is
|
||||
they can be accessed in high memory or low memory.
|
||||
For simplicity only one instance is used in this
|
||||
linker file.
|
||||
|
||||
Contiguous SARAM memory blocks can be combined
|
||||
if required to create a larger memory block.
|
||||
*/
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0 :
|
||||
/* BEGIN is used for the "boot to SARAM" bootloader mode */
|
||||
|
||||
BEGIN : origin = 0x000000, length = 0x000002 /* Boot to M0 will go here */
|
||||
RAMM0 : origin = 0x000050, length = 0x0003B0
|
||||
RAML0 : origin = 0x008000, length = 0x001000
|
||||
RAML1 : origin = 0x009000, length = 0x001000
|
||||
RAML2 : origin = 0x00A000, length = 0x001000
|
||||
RAML3 : origin = 0x00B000, length = 0x001000
|
||||
ZONE7A : origin = 0x200000, length = 0x00FC00 /* XINTF zone 7 - program space */
|
||||
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
|
||||
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
|
||||
ADC_CAL : origin = 0x380080, length = 0x000009
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002
|
||||
IQTABLES : origin = 0x3FE000, length = 0x000b50
|
||||
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c
|
||||
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0
|
||||
BOOTROM : origin = 0x3FF27C, length = 0x000D44
|
||||
|
||||
|
||||
PAGE 1 :
|
||||
/* BOOT_RSVD is used by the boot ROM for stack. */
|
||||
/* This section is only reserved to keep the BOOT ROM from */
|
||||
/* corrupting this area during the debug process */
|
||||
|
||||
BOOT_RSVD : origin = 0x000002, length = 0x00004E /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
|
||||
RAML4 : origin = 0x00C000, length = 0x001000
|
||||
RAML5 : origin = 0x00D000, length = 0x001000
|
||||
RAML6 : origin = 0x00E000, length = 0x001000
|
||||
RAML7 : origin = 0x00F000, length = 0x001000
|
||||
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Setup for "boot to SARAM" mode:
|
||||
The codestart section (found in DSP28_CodeStartBranch.asm)
|
||||
re-directs execution to the start of user code. */
|
||||
codestart : > BEGIN, PAGE = 0
|
||||
ramfuncs : > RAML0, PAGE = 0
|
||||
.text : > RAML1, PAGE = 0
|
||||
.InitBoot : > RAML1, PAGE = 0
|
||||
.cinit : > RAML0, PAGE = 0
|
||||
.pinit : > RAML0, PAGE = 0
|
||||
.switch : > RAML0, PAGE = 0
|
||||
|
||||
.stack : > RAMM1, PAGE = 1
|
||||
.ebss : > RAML4, PAGE = 1
|
||||
.econst : > RAML5, PAGE = 1
|
||||
.esysmem : > RAMM1, PAGE = 1
|
||||
|
||||
IQmath : > RAML1, PAGE = 0
|
||||
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
|
||||
|
||||
/* Uncomment the section below if calling the IQNexp() or IQexp()
|
||||
functions from the IQMath.lib library in order to utilize the
|
||||
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
|
||||
is 1 wait-state). If this section is not uncommented, IQmathTables2
|
||||
will be loaded into other memory (SARAM, Flash, etc.) and will take
|
||||
up space, but 0 wait-state is possible.
|
||||
*/
|
||||
/*
|
||||
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
|
||||
{
|
||||
|
||||
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
|
||||
|
||||
}
|
||||
*/
|
||||
|
||||
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
|
||||
|
||||
DMARAML4 : > RAML4, PAGE = 1
|
||||
DMARAML5 : > RAML5, PAGE = 1
|
||||
DMARAML6 : > RAML6, PAGE = 1
|
||||
DMARAML7 : > RAML7, PAGE = 1
|
||||
|
||||
ZONE7DATA : > ZONE7B, PAGE = 1
|
||||
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used */
|
||||
csm_rsvd : > CSM_RSVD PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
|
||||
csmpasswds : > CSM_PWL PAGE = 0, TYPE = DSECT /* not used for SARAM examples */
|
||||
|
||||
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
|
||||
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@ -0,0 +1,183 @@
|
||||
/*
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: DSP2833x_Headers_nonBIOS.cmd
|
||||
//
|
||||
// TITLE: DSP2833x Peripheral registers linker command file
|
||||
//
|
||||
// DESCRIPTION:
|
||||
//
|
||||
// This file is for use in Non-BIOS applications.
|
||||
//
|
||||
// Linker command file to place the peripheral structures
|
||||
// used within the DSP2833x headerfiles into the correct memory
|
||||
// mapped locations.
|
||||
//
|
||||
// This version of the file includes the PieVectorTable structure.
|
||||
// For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file
|
||||
// which does not include the PieVectorTable structure.
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0: /* Program Memory */
|
||||
|
||||
PAGE 1: /* Data Memory */
|
||||
|
||||
DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */
|
||||
FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */
|
||||
CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */
|
||||
|
||||
ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */
|
||||
|
||||
XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */
|
||||
|
||||
CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */
|
||||
CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
|
||||
CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
|
||||
|
||||
PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */
|
||||
PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */
|
||||
|
||||
DMA : origin = 0x001000, length = 0x000200 /* DMA registers */
|
||||
|
||||
MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */
|
||||
MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */
|
||||
|
||||
ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */
|
||||
ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */
|
||||
ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */
|
||||
ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */
|
||||
ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */
|
||||
|
||||
ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */
|
||||
ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */
|
||||
ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */
|
||||
ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */
|
||||
ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */
|
||||
|
||||
EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */
|
||||
EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */
|
||||
EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */
|
||||
EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */
|
||||
EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */
|
||||
EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */
|
||||
|
||||
ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */
|
||||
ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */
|
||||
ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */
|
||||
ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */
|
||||
ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */
|
||||
ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */
|
||||
|
||||
EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */
|
||||
EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */
|
||||
|
||||
GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */
|
||||
GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */
|
||||
GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */
|
||||
|
||||
SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */
|
||||
SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */
|
||||
SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */
|
||||
XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */
|
||||
|
||||
ADC : origin = 0x007100, length = 0x000020 /* ADC registers */
|
||||
|
||||
SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */
|
||||
|
||||
SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */
|
||||
|
||||
I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */
|
||||
|
||||
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */
|
||||
|
||||
PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */
|
||||
}
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
PieVectTableFile : > PIE_VECT, PAGE = 1
|
||||
|
||||
/*** Peripheral Frame 0 Register Structures ***/
|
||||
DevEmuRegsFile : > DEV_EMU, PAGE = 1
|
||||
FlashRegsFile : > FLASH_REGS, PAGE = 1
|
||||
CsmRegsFile : > CSM, PAGE = 1
|
||||
AdcMirrorFile : > ADC_MIRROR, PAGE = 1
|
||||
XintfRegsFile : > XINTF, PAGE = 1
|
||||
CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1
|
||||
CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1
|
||||
CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
|
||||
PieCtrlRegsFile : > PIE_CTRL, PAGE = 1
|
||||
DmaRegsFile : > DMA, PAGE = 1
|
||||
|
||||
/*** Peripheral Frame 3 Register Structures ***/
|
||||
McbspaRegsFile : > MCBSPA, PAGE = 1
|
||||
McbspbRegsFile : > MCBSPB, PAGE = 1
|
||||
|
||||
/*** Peripheral Frame 1 Register Structures ***/
|
||||
ECanaRegsFile : > ECANA, PAGE = 1
|
||||
ECanaLAMRegsFile : > ECANA_LAM PAGE = 1
|
||||
ECanaMboxesFile : > ECANA_MBOX PAGE = 1
|
||||
ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1
|
||||
ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1
|
||||
|
||||
ECanbRegsFile : > ECANB, PAGE = 1
|
||||
ECanbLAMRegsFile : > ECANB_LAM PAGE = 1
|
||||
ECanbMboxesFile : > ECANB_MBOX PAGE = 1
|
||||
ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1
|
||||
ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1
|
||||
|
||||
EPwm1RegsFile : > EPWM1 PAGE = 1
|
||||
EPwm2RegsFile : > EPWM2 PAGE = 1
|
||||
EPwm3RegsFile : > EPWM3 PAGE = 1
|
||||
EPwm4RegsFile : > EPWM4 PAGE = 1
|
||||
EPwm5RegsFile : > EPWM5 PAGE = 1
|
||||
EPwm6RegsFile : > EPWM6 PAGE = 1
|
||||
|
||||
ECap1RegsFile : > ECAP1 PAGE = 1
|
||||
ECap2RegsFile : > ECAP2 PAGE = 1
|
||||
ECap3RegsFile : > ECAP3 PAGE = 1
|
||||
ECap4RegsFile : > ECAP4 PAGE = 1
|
||||
ECap5RegsFile : > ECAP5 PAGE = 1
|
||||
ECap6RegsFile : > ECAP6 PAGE = 1
|
||||
|
||||
EQep1RegsFile : > EQEP1 PAGE = 1
|
||||
EQep2RegsFile : > EQEP2 PAGE = 1
|
||||
|
||||
GpioCtrlRegsFile : > GPIOCTRL PAGE = 1
|
||||
GpioDataRegsFile : > GPIODAT PAGE = 1
|
||||
GpioIntRegsFile : > GPIOINT PAGE = 1
|
||||
|
||||
/*** Peripheral Frame 2 Register Structures ***/
|
||||
SysCtrlRegsFile : > SYSTEM, PAGE = 1
|
||||
SpiaRegsFile : > SPIA, PAGE = 1
|
||||
SciaRegsFile : > SCIA, PAGE = 1
|
||||
XIntruptRegsFile : > XINTRUPT, PAGE = 1
|
||||
AdcRegsFile : > ADC, PAGE = 1
|
||||
ScibRegsFile : > SCIB, PAGE = 1
|
||||
ScicRegsFile : > SCIC, PAGE = 1
|
||||
I2caRegsFile : > I2CA, PAGE = 1
|
||||
|
||||
/*** Code Security Module Register Structures ***/
|
||||
CsmPwlFile : > CSM_PWL, PAGE = 1
|
||||
|
||||
/*** Device Part ID Register Structures ***/
|
||||
PartIdRegsFile : > PARTID, PAGE = 1
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
@ -0,0 +1,204 @@
|
||||
/*
|
||||
//###########################################################################
|
||||
//
|
||||
// FILE: F28335.cmd
|
||||
//
|
||||
// TITLE: Linker Command File For F28335 Device
|
||||
//
|
||||
//###########################################################################
|
||||
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
|
||||
// $Release Date: November 1, 2016 $
|
||||
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
|
||||
// http://www.ti.com/ ALL RIGHTS RESERVED $
|
||||
//###########################################################################
|
||||
*/
|
||||
|
||||
/* ======================================================
|
||||
// For Code Composer Studio V2.2 and later
|
||||
// ---------------------------------------
|
||||
// In addition to this memory linker command file,
|
||||
// add the header linker command file directly to the project.
|
||||
// The header linker command file is required to link the
|
||||
// peripheral structures to the proper locations within
|
||||
// the memory map.
|
||||
//
|
||||
// The header linker files are found in <base>\DSP2833x_Headers\cmd
|
||||
//
|
||||
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
|
||||
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
|
||||
========================================================= */
|
||||
|
||||
/* ======================================================
|
||||
// For Code Composer Studio prior to V2.2
|
||||
// --------------------------------------
|
||||
// 1) Use one of the following -l statements to include the
|
||||
// header linker command file in the project. The header linker
|
||||
// file is required to link the peripheral structures to the proper
|
||||
// locations within the memory map */
|
||||
|
||||
/* Uncomment this line to include file only for non-BIOS applications */
|
||||
/* -l DSP2833x_Headers_nonBIOS.cmd */
|
||||
|
||||
/* Uncomment this line to include file only for BIOS applications */
|
||||
/* -l DSP2833x_Headers_BIOS.cmd */
|
||||
|
||||
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
|
||||
library search path under project->build options, linker tab,
|
||||
library search path (-i).
|
||||
/*========================================================= */
|
||||
|
||||
/* Define the memory block start/length for the F28335
|
||||
PAGE 0 will be used to organize program sections
|
||||
PAGE 1 will be used to organize data sections
|
||||
|
||||
Notes:
|
||||
Memory blocks on F28335 are uniform (ie same
|
||||
physical memory) in both PAGE 0 and PAGE 1.
|
||||
That is the same memory region should not be
|
||||
defined for both PAGE 0 and PAGE 1.
|
||||
Doing so will result in corruption of program
|
||||
and/or data.
|
||||
|
||||
L0/L1/L2 and L3 memory blocks are mirrored - that is
|
||||
they can be accessed in high memory or low memory.
|
||||
For simplicity only one instance is used in this
|
||||
linker file.
|
||||
|
||||
Contiguous SARAM memory blocks can be combined
|
||||
if required to create a larger memory block.
|
||||
*/
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
PAGE 0: /* Program Memory */
|
||||
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
|
||||
|
||||
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
|
||||
RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */
|
||||
RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */
|
||||
RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */
|
||||
RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */
|
||||
ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
|
||||
ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */
|
||||
FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
|
||||
FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
|
||||
FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
|
||||
FLASHE : origin = 0x318000, length = 0x008000 /* on-chip FLASH */
|
||||
FLASHD : origin = 0x320000, length = 0x008000 /* on-chip FLASH */
|
||||
FLASHC : origin = 0x328000, length = 0x008000 /* on-chip FLASH */
|
||||
FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
|
||||
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
|
||||
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
|
||||
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
|
||||
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
|
||||
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
|
||||
|
||||
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
|
||||
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
|
||||
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
|
||||
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
|
||||
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
|
||||
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
|
||||
|
||||
PAGE 1 : /* Data Memory */
|
||||
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
|
||||
/* Registers remain on PAGE1 */
|
||||
|
||||
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
|
||||
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
|
||||
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
|
||||
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
|
||||
RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */
|
||||
RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */
|
||||
RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */
|
||||
ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
|
||||
FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */
|
||||
}
|
||||
|
||||
/* Allocate sections to memory blocks.
|
||||
Note:
|
||||
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
|
||||
execution when booting to flash
|
||||
ramfuncs user defined section to store functions that will be copied from Flash into RAM
|
||||
*/
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* Allocate program areas: */
|
||||
.cinit : > FLASHA PAGE = 0
|
||||
.pinit : > FLASHA, PAGE = 0
|
||||
.text : > FLASHA PAGE = 0
|
||||
codestart : > BEGIN PAGE = 0
|
||||
ramfuncs : LOAD = FLASHD,
|
||||
RUN = RAML0,
|
||||
LOAD_START(_RamfuncsLoadStart),
|
||||
LOAD_END(_RamfuncsLoadEnd),
|
||||
RUN_START(_RamfuncsRunStart),
|
||||
LOAD_SIZE(_RamfuncsLoadSize),
|
||||
PAGE = 0
|
||||
|
||||
csmpasswds : > CSM_PWL PAGE = 0
|
||||
csm_rsvd : > CSM_RSVD PAGE = 0
|
||||
|
||||
/* Allocate uninitalized data sections: */
|
||||
.stack : > RAML7 PAGE = 1 // CHANGES RAMM1 was here. Also 0x400 was added in linker general options (in -heap) and 0x300 at stack was changed to 0x400
|
||||
.ebss : > RAML4 PAGE = 1
|
||||
.esysmem : > RAMM1 PAGE = 1
|
||||
|
||||
/* Initalized sections go in Flash */
|
||||
/* For SDFlash to program these, they must be allocated to page 0 */
|
||||
.econst : > FLASHA PAGE = 0
|
||||
.switch : > FLASHA PAGE = 0
|
||||
|
||||
/* Allocate IQ math areas: */
|
||||
IQmath : > FLASHC PAGE = 0 /* Math Code */
|
||||
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
|
||||
|
||||
/* Uncomment the section below if calling the IQNexp() or IQexp()
|
||||
functions from the IQMath.lib library in order to utilize the
|
||||
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
|
||||
is 1 wait-state). If this section is not uncommented, IQmathTables2
|
||||
will be loaded into other memory (SARAM, Flash, etc.) and will take
|
||||
up space, but 0 wait-state is possible.
|
||||
*/
|
||||
/*
|
||||
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
|
||||
{
|
||||
|
||||
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
|
||||
|
||||
}
|
||||
*/
|
||||
|
||||
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
|
||||
|
||||
/* Allocate DMA-accessible RAM sections: */
|
||||
DMARAML4 : > RAML4, PAGE = 1
|
||||
DMARAML5 : > RAML5, PAGE = 1
|
||||
DMARAML6 : > RAML6, PAGE = 1
|
||||
DMARAML7 : > RAML7, PAGE = 1
|
||||
|
||||
/* Allocate 0x400 of XINTF Zone 7 to storing data */
|
||||
ZONE7DATA : > ZONE7B, PAGE = 1
|
||||
|
||||
/* .reset is a standard section used by the compiler. It contains the */
|
||||
/* the address of the start of _c_int00 for C Code. /*
|
||||
/* When using the boot ROM this section and the CPU vector */
|
||||
/* table is not needed. Thus the default type is set here to */
|
||||
/* DSECT */
|
||||
.reset : > RESET, PAGE = 0, TYPE = DSECT
|
||||
vectors : > VECTORS PAGE = 0, TYPE = DSECT
|
||||
|
||||
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
|
||||
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
//===========================================================================
|
||||
// End of file.
|
||||
//===========================================================================
|
||||
*/
|
||||
|
||||
@ -0,0 +1,229 @@
|
||||
// Some comments about author
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "DSP2833x_Device.h"
|
||||
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
|
||||
#include "DSP2833x_Examples.h"
|
||||
#include "Protocol/CAN.h"
|
||||
#include "Protocol/CAN_data.h"
|
||||
#include "Protocol/DigitalIO.h"
|
||||
|
||||
|
||||
//Functions declarations
|
||||
void idle_loop(void);
|
||||
|
||||
interrupt void cpu_timer0_isr(void);
|
||||
interrupt void cpu_timer1_isr(void);
|
||||
interrupt void canb_isr(void);
|
||||
interrupt void canb_box_isr(void);
|
||||
|
||||
canSpace::CAN canTest(canSpace::CANB);
|
||||
|
||||
interface::DigitalIO digitalIO;
|
||||
interface::DigitalIODataRegister digitalInputReg;
|
||||
interface::DigitalIODataRegister digitalOutputReg;
|
||||
|
||||
// RX
|
||||
canSpace::CANMessage DOMessage;
|
||||
canSpace::CANMessage messageSettings;
|
||||
canSpace::CANMessage MODBUS_CPU_COMM_Message;
|
||||
|
||||
// TX
|
||||
canSpace::CANMessage DIMessage;
|
||||
canSpace::CANMessage MODBUS_COMM_CPU_Message;
|
||||
canSpace::CANMessage SoftVersionMessage;
|
||||
Uint32 array[25] = {0};
|
||||
|
||||
struct SoftwareVersion{
|
||||
Uint16 DSP;
|
||||
Uint16 CPLD;
|
||||
};
|
||||
|
||||
SoftwareVersion softVersion = { .DSP = 101, .CPLD = 202 };
|
||||
|
||||
volatile Uint16 infCounter = 0;
|
||||
volatile Uint16 canISRcounter = 0;
|
||||
volatile Uint16 canBoxISRcounter = 0;
|
||||
volatile Uint16 testCounter = 0;
|
||||
|
||||
volatile bool init = true;
|
||||
volatile bool startTX = false;
|
||||
volatile bool update = false;
|
||||
volatile bool sendRemote = false;
|
||||
|
||||
Uint16 modbusInit = 0;
|
||||
int32 testVar = 0;
|
||||
|
||||
|
||||
void main()
|
||||
{
|
||||
ServiceDog();
|
||||
DisableDog();
|
||||
|
||||
InitSysCtrl();
|
||||
|
||||
DINT;
|
||||
|
||||
InitPieCtrl();
|
||||
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
InitPieVectTable();
|
||||
|
||||
EALLOW;
|
||||
PieVectTable.TINT0 = &cpu_timer0_isr;
|
||||
PieVectTable.XINT13 = &cpu_timer1_isr;
|
||||
PieVectTable.ECAN0INTB = &canb_isr;
|
||||
PieVectTable.ECAN1INTB = &canb_box_isr;
|
||||
EDIS;
|
||||
|
||||
InitCpuTimers();
|
||||
ConfigCpuTimer(&CpuTimer0, 150, 1000); // 1ms
|
||||
ConfigCpuTimer(&CpuTimer1, 150, 5000); // 5ms
|
||||
|
||||
IER |= M_INT1; // Enable CPU Interrupt 1
|
||||
IER |= M_INT9; // Enable CPU Interrupt 9
|
||||
IER |= M_INT13; // Enable CPU Interrupt 13
|
||||
|
||||
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
|
||||
PieCtrlRegs.PIEIER9.bit.INTx7 = 1; // from 5 to 8
|
||||
PieCtrlRegs.PIEIER9.bit.INTx8 = 1;
|
||||
|
||||
canTest.initGpio();
|
||||
canTest.config();
|
||||
canTest.configTxMBox(canSpace::DIGITAL_INPUT_MBOX, canSpace::MsgID(0x30), canSpace::MsgCtrlReg(0x3));
|
||||
|
||||
DIMessage.dataLength = 3;
|
||||
DIMessage.mdl.byte.BYTE0 = 0x11;
|
||||
DIMessage.mdl.byte.BYTE1 = 0x22;
|
||||
DIMessage.mdl.byte.BYTE2 = 0x33;
|
||||
|
||||
MODBUS_COMM_CPU_Message.dataLength = 6;
|
||||
MODBUS_COMM_CPU_Message.mdl.byte.BYTE0 = 0xA;
|
||||
MODBUS_COMM_CPU_Message.mdl.byte.BYTE1 = 0xB;
|
||||
MODBUS_COMM_CPU_Message.mdl.byte.BYTE2 = 0xC;
|
||||
MODBUS_COMM_CPU_Message.mdl.byte.BYTE3 = 0xD;
|
||||
MODBUS_COMM_CPU_Message.mdh.byte.BYTE4 = 0xE;
|
||||
MODBUS_COMM_CPU_Message.mdh.byte.BYTE5 = 0xF;
|
||||
|
||||
SoftVersionMessage.dataLength = 2;
|
||||
SoftVersionMessage.mdl.byte.BYTE0 = softVersion.DSP;
|
||||
SoftVersionMessage.mdl.byte.BYTE0 = softVersion.CPLD;
|
||||
|
||||
digitalIO.setup((Uint16*)0x4000);
|
||||
|
||||
// Enable global Interrupts and higher priority real-time debug events:
|
||||
EINT; // Enable Global interrupt INTM
|
||||
ERTM; // Enable Global realtime interrupt DBGM
|
||||
|
||||
CpuTimer0.RegsAddr->TCR.bit.TSS = 0;
|
||||
CpuTimer1.RegsAddr->TCR.bit.TSS = 0;
|
||||
|
||||
idle_loop();
|
||||
//
|
||||
}//end main()
|
||||
//
|
||||
//
|
||||
|
||||
void idle_loop()
|
||||
{
|
||||
while (true)
|
||||
{
|
||||
infCounter++;
|
||||
|
||||
// ожидать получения данных при remote frame
|
||||
// get cpld version with xintf here
|
||||
// if (init){
|
||||
// init = false;
|
||||
// // в main положить
|
||||
// canTest.updateTXMessage(canSpace::COMM_VERSION_MBOX, SoftVersionMessage);
|
||||
// }
|
||||
|
||||
// if (canTest.isNewMessage(canSpace::MODBUS_SETTINGS_MBOX)){
|
||||
// canTest.receiveMsg(canSpace::MODBUS_SETTINGS_MBOX, messageSettings);
|
||||
// modbusInit++;
|
||||
// }
|
||||
|
||||
}//end while
|
||||
|
||||
}//end idle_loop()
|
||||
|
||||
|
||||
interrupt void cpu_timer0_isr(void)
|
||||
{
|
||||
CpuTimer0.InterruptCount++;
|
||||
// if(canTest.isNewMessage()){
|
||||
// canTest.receiveMsg(canSpace::DIGITAL_OUTPUT_MBOX, DOMessage);
|
||||
// canTest.receiveMsg(canSpace::MODBUS_DATA_CPU_TO_COMM_MBOX, MODBUS_CPU_COMM_Message);
|
||||
// testCounter++;
|
||||
// }
|
||||
|
||||
// digitalOutputReg.all = digitalOutputReg.all;
|
||||
// digitalIO.writeDigitalIO(digitalOutputReg.all);
|
||||
|
||||
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
|
||||
}//end
|
||||
|
||||
|
||||
interrupt void cpu_timer1_isr(){
|
||||
CpuTimer1.InterruptCount++;
|
||||
|
||||
// digitalIO.readDigitalIO(DIMessage.mdl.all);
|
||||
// digitalIO.readDigitalIO(digitalInputReg.all);
|
||||
// DIMessage.mdl.all = digitalInputReg.all;
|
||||
canTest.transmitMsg(canSpace::DIGITAL_INPUT_MBOX, DIMessage);
|
||||
}
|
||||
|
||||
|
||||
interrupt void canb_isr(void){
|
||||
canISRcounter++;
|
||||
|
||||
CANGIF0_REG CANGIF0_SHADOW;
|
||||
volatile Uint32 resetBit;
|
||||
|
||||
CANGIF0_SHADOW.all = ECanbRegs.CANGIF0.all;
|
||||
|
||||
if (CANGIF0_SHADOW.bit.WLIF0){
|
||||
resetBit = 256;
|
||||
ECanbRegs.CANGIF0.all = 256ul;
|
||||
}
|
||||
|
||||
if (CANGIF0_SHADOW.bit.EPIF0){
|
||||
ECanbRegs.CANGIF0.all = 528ul;
|
||||
}
|
||||
|
||||
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9;
|
||||
}
|
||||
|
||||
interrupt void canb_box_isr(void){
|
||||
canBoxISRcounter++;
|
||||
|
||||
// Just example
|
||||
//
|
||||
// volatile Uint32 boxNumberIsr;
|
||||
// boxNumberIsr = ECanbRegs.CANGIF1.bit.MIV1;
|
||||
|
||||
// CANRMP_REG temp;
|
||||
// temp.all = 0;
|
||||
// temp.all = 1ul << 27;
|
||||
|
||||
// ECanbRegs.CANRMP.all = temp.all;
|
||||
|
||||
// MODBUS_COMM_CPU_Message27.mdh.all = ECanbMboxes.MBOX27.MDH.all;
|
||||
// MODBUS_COMM_CPU_Message27.mdl.all = ECanbMboxes.MBOX27.MDL.all;
|
||||
|
||||
// temp.all = ECanbRegs.CANRMP.all;
|
||||
// if (temp.bit.RMP25){
|
||||
// temp.all = 1ul << 25;
|
||||
// ECanbRegs.CANRMP.all = temp.all;
|
||||
|
||||
// MODBUS_COMM_CPU_Message25.mdh.all = ECanbMboxes.MBOX25.MDH.all;
|
||||
// MODBUS_COMM_CPU_Message25.mdl.all = ECanbMboxes.MBOX25.MDL.all;
|
||||
// }
|
||||
|
||||
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9;
|
||||
}
|
||||
@ -0,0 +1,166 @@
|
||||
// Some comments about author
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "DSP2833x_Device.h"
|
||||
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
|
||||
#include "DSP2833x_Examples.h"
|
||||
#include "Protocol/CAN.h"
|
||||
#include "Protocol/CAN_data.h"
|
||||
#include "Protocol/DigitalIO.h"
|
||||
#include "Periphery.h"
|
||||
|
||||
|
||||
//Functions declarations
|
||||
void idle_loop(void);
|
||||
|
||||
interrupt void cpu_timer0_isr(void);
|
||||
interrupt void cpu_timer1_isr(void);
|
||||
interrupt void canb_isr(void);
|
||||
interrupt void canb_box_isr(void);
|
||||
|
||||
Periphery periphery;
|
||||
|
||||
volatile Uint16 infCounter = 0;
|
||||
volatile Uint16 canISRcounter = 0;
|
||||
volatile Uint16 canBoxISRcounter = 0;
|
||||
volatile Uint16 testCounter = 0;
|
||||
|
||||
volatile bool init = true;
|
||||
volatile bool startTX = false;
|
||||
volatile bool update = false;
|
||||
volatile bool sendRemote = false;
|
||||
|
||||
Uint16 modbusInit = 0;
|
||||
int32 testVar = 0;
|
||||
|
||||
void main()
|
||||
{
|
||||
ServiceDog();
|
||||
DisableDog();
|
||||
|
||||
InitSysCtrl();
|
||||
|
||||
DINT;
|
||||
|
||||
InitPieCtrl();
|
||||
|
||||
IER = 0x0000;
|
||||
IFR = 0x0000;
|
||||
|
||||
InitPieVectTable();
|
||||
|
||||
EALLOW;
|
||||
PieVectTable.TINT0 = &cpu_timer0_isr;
|
||||
PieVectTable.XINT13 = &cpu_timer1_isr;
|
||||
PieVectTable.ECAN0INTB = &canb_isr;
|
||||
PieVectTable.ECAN1INTB = &canb_box_isr;
|
||||
EDIS;
|
||||
|
||||
InitCpuTimers();
|
||||
ConfigCpuTimer(&CpuTimer0, 150, 1000); // 1ms
|
||||
ConfigCpuTimer(&CpuTimer1, 150, 5000); // 5ms
|
||||
|
||||
IER |= M_INT1; // Enable CPU Interrupt 1
|
||||
IER |= M_INT9; // Enable CPU Interrupt 9
|
||||
IER |= M_INT13; // Enable CPU Interrupt 13
|
||||
|
||||
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
|
||||
PieCtrlRegs.PIEIER9.bit.INTx7 = 1; // from 5 to 8
|
||||
PieCtrlRegs.PIEIER9.bit.INTx8 = 1;
|
||||
|
||||
periphery.config();
|
||||
|
||||
// Enable global Interrupts and higher priority real-time debug events:
|
||||
EINT; // Enable Global interrupt INTM
|
||||
ERTM; // Enable Global realtime interrupt DBGM
|
||||
|
||||
periphery.updateVersionFPGA();
|
||||
|
||||
CpuTimer0.RegsAddr->TCR.bit.TSS = 0;
|
||||
CpuTimer1.RegsAddr->TCR.bit.TSS = 0;
|
||||
|
||||
idle_loop();
|
||||
//
|
||||
}//end main()
|
||||
//
|
||||
//
|
||||
|
||||
void idle_loop()
|
||||
{
|
||||
while (true)
|
||||
{
|
||||
infCounter++;
|
||||
|
||||
periphery.initExternalModbus();
|
||||
|
||||
}//end while
|
||||
|
||||
}//end idle_loop()
|
||||
|
||||
|
||||
interrupt void cpu_timer0_isr(void)
|
||||
{
|
||||
periphery.processDigitalOutput();
|
||||
|
||||
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
|
||||
}//end
|
||||
|
||||
|
||||
interrupt void cpu_timer1_isr(){
|
||||
CpuTimer1.InterruptCount++;
|
||||
|
||||
periphery.processDigitalInput();
|
||||
}
|
||||
|
||||
|
||||
interrupt void canb_isr(void){
|
||||
canISRcounter++;
|
||||
|
||||
CANGIF0_REG CANGIF0_SHADOW;
|
||||
volatile Uint32 resetBit;
|
||||
|
||||
CANGIF0_SHADOW.all = ECanbRegs.CANGIF0.all;
|
||||
|
||||
if (CANGIF0_SHADOW.bit.WLIF0){
|
||||
resetBit = 256;
|
||||
ECanbRegs.CANGIF0.all = 256ul;
|
||||
}
|
||||
|
||||
if (CANGIF0_SHADOW.bit.EPIF0){
|
||||
ECanbRegs.CANGIF0.all = 528ul;
|
||||
}
|
||||
|
||||
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9;
|
||||
}
|
||||
|
||||
interrupt void canb_box_isr(void){
|
||||
canBoxISRcounter++;
|
||||
|
||||
// Just example
|
||||
//
|
||||
// volatile Uint32 boxNumberIsr;
|
||||
// boxNumberIsr = ECanbRegs.CANGIF1.bit.MIV1;
|
||||
|
||||
// CANRMP_REG temp;
|
||||
// temp.all = 0;
|
||||
// temp.all = 1ul << 27;
|
||||
|
||||
// ECanbRegs.CANRMP.all = temp.all;
|
||||
|
||||
// MODBUS_COMM_CPU_Message27.mdh.all = ECanbMboxes.MBOX27.MDH.all;
|
||||
// MODBUS_COMM_CPU_Message27.mdl.all = ECanbMboxes.MBOX27.MDL.all;
|
||||
|
||||
// temp.all = ECanbRegs.CANRMP.all;
|
||||
// if (temp.bit.RMP25){
|
||||
// temp.all = 1ul << 25;
|
||||
// ECanbRegs.CANRMP.all = temp.all;
|
||||
|
||||
// MODBUS_COMM_CPU_Message25.mdh.all = ECanbMboxes.MBOX25.MDH.all;
|
||||
// MODBUS_COMM_CPU_Message25.mdl.all = ECanbMboxes.MBOX25.MDL.all;
|
||||
// }
|
||||
|
||||
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP9;
|
||||
}
|
||||
@ -0,0 +1,28 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<configurations XML_version="1.2" id="configurations_0">
|
||||
|
||||
|
||||
<configuration XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
|
||||
|
||||
<instance XML_version="1.2" desc="Texas Instruments XDS100v3 USB Debug Probe_0" href="connections/TIXDS100v3_Dot7_Connection.xml" id="Texas Instruments XDS100v3 USB Debug Probe_0" xml="TIXDS100v3_Dot7_Connection.xml" xmlpath="connections"/>
|
||||
|
||||
<connection XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
|
||||
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2c28x.xml" id="drivers" xml="tixds100v2c28x.xml" xmlpath="drivers"/>
|
||||
|
||||
<property Type="choicelist" Value="1" id="Emulator Selection">
|
||||
<choice Name="Select by serial number" value="0">
|
||||
<property Type="stringfield" Value="FT57N1L8" id="-- Enter the serial number"/>
|
||||
</choice>
|
||||
</property>
|
||||
<platform XML_version="1.2" id="platform_0">
|
||||
|
||||
<instance XML_version="1.2" desc="TMS320F28335_0" href="devices/f28335.xml" id="TMS320F28335_0" xml="f28335.xml" xmlpath="devices"/>
|
||||
|
||||
</platform>
|
||||
|
||||
</connection>
|
||||
|
||||
</configuration>
|
||||
|
||||
</configurations>
|
||||
@ -0,0 +1,28 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<configurations XML_version="1.2" id="configurations_0">
|
||||
|
||||
|
||||
<configuration XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
|
||||
|
||||
<instance XML_version="1.2" desc="Texas Instruments XDS100v3 USB Debug Probe_0" href="connections/TIXDS100v3_Dot7_Connection.xml" id="Texas Instruments XDS100v3 USB Debug Probe_0" xml="TIXDS100v3_Dot7_Connection.xml" xmlpath="connections"/>
|
||||
|
||||
<connection XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe_0">
|
||||
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2c28x.xml" id="drivers" xml="tixds100v2c28x.xml" xmlpath="drivers"/>
|
||||
|
||||
<property Type="choicelist" Value="1" id="Emulator Selection">
|
||||
<choice Name="Select by serial number" value="0">
|
||||
<property Type="stringfield" Value="TI7EZCHI" id="-- Enter the serial number"/>
|
||||
</choice>
|
||||
</property>
|
||||
<platform XML_version="1.2" id="platform_0">
|
||||
|
||||
<instance XML_version="1.2" desc="TMS320F28335_0" href="devices/f28335.xml" id="TMS320F28335_0" xml="f28335.xml" xmlpath="devices"/>
|
||||
|
||||
</platform>
|
||||
|
||||
</connection>
|
||||
|
||||
</configuration>
|
||||
|
||||
</configurations>
|
||||
@ -0,0 +1,42 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<configurations XML_version="1.2" id="configurations_0">
|
||||
|
||||
|
||||
|
||||
<configuration XML_version="1.2" id="configuration_0">
|
||||
|
||||
|
||||
|
||||
<instance XML_version="1.2" desc="Texas Instruments XDS100v3 USB Debug Probe" href="connections/TIXDS100v3_Dot7_Connection.xml" id="Texas Instruments XDS100v3 USB Debug Probe" xml="TIXDS100v3_Dot7_Connection.xml" xmlpath="connections"/>
|
||||
|
||||
|
||||
|
||||
<connection XML_version="1.2" id="Texas Instruments XDS100v3 USB Debug Probe">
|
||||
|
||||
|
||||
|
||||
<instance XML_version="1.2" href="drivers/tixds100v2c28x.xml" id="drivers" xml="tixds100v2c28x.xml" xmlpath="drivers"/>
|
||||
|
||||
|
||||
|
||||
<platform XML_version="1.2" id="platform_0">
|
||||
|
||||
|
||||
|
||||
<instance XML_version="1.2" desc="TMS320F28335" href="devices/f28335.xml" id="TMS320F28335" xml="f28335.xml" xmlpath="devices"/>
|
||||
|
||||
|
||||
|
||||
</platform>
|
||||
|
||||
|
||||
|
||||
</connection>
|
||||
|
||||
|
||||
|
||||
</configuration>
|
||||
|
||||
|
||||
|
||||
</configurations>
|
||||
@ -0,0 +1,9 @@
|
||||
The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based
|
||||
on the device and connection settings specified in your project on the Properties > General page.
|
||||
|
||||
Please note that in automatic target-configuration management, changes to the project's device and/or
|
||||
connection settings will either modify an existing or generate a new target-configuration file. Thus,
|
||||
if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively,
|
||||
you may create your own target-configuration file for this project and manage it manually. You can
|
||||
always switch back to automatic target-configuration management by checking the "Manage the project's
|
||||
target-configuration automatically" checkbox on the project's Properties > General page.
|
||||
Loading…
Reference in New Issue