/*
 * ADC.cpp
 *
 *      Author: Aleksey Gerasimenko
 *      gerasimenko.aleksey.n@gmail.com
 */

#include "DSP28335/ADC.h"

namespace DSP28335
{

//CONSTRUCTOR
ADC::ADC():
        DSP28335::CPUBase(),
        m_status(false)
//
{}//end CONSTRUCTOR
//

void DSP28335::ADC::setup()
{
    if(m_mode == DSP28335::ADC::UNDEFINED)
    {
        //--- Configure the other ADC registers
        AdcRegs.ADCREFSEL.bit.REF_SEL = 0;  // ADC reference, 0=internal, 1=external

        //--- Power-up the ADC
        //AdcRegs.ADCTRL3.all = 0x00EC;     // Power-up reference and main ADC
        //AdcRegs.ADCTRL3.all = 0x00F4;     // Power-up reference and main ADC /20
        //AdcRegs.ADCTRL3.all = 0x00EE;     // Power-up reference and main ADC /14
        //AdcRegs.ADCTRL3.all = 0x00EA;     // Power-up reference and main ADC /10
        //AdcRegs.ADCTRL3.all = 0x00E8;     // Power-up reference and main ADC /8
        //AdcRegs.ADCTRL3.all = 0x00E4;     // Power-up reference and main ADC /4
        // bit 15-8      0's:    reserved
        // bit 7-6       11:     ADCBGRFDN, reference power, 00=off, 11=on
        // bit 5         1:      ADCPWDN, main ADC power, 0=off, 1=on
        // bit 4-1       0110:   ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
        // bit 0         0:      SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling

        AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0008;      // bit 4-1       0110:   ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
        AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0000;     // bit 0         0:      SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling
        AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x0003;     // bit 7-6       11:     ADCBGRFDN, reference power, 00=off, 11=on
        AdcRegs.ADCTRL3.bit.ADCPWDN = 0x0001;       // bit 5         1:      ADCPWDN, main ADC power, 0=off, 1=on

        DELAY_US(5000);                      // Wait 5 ms before using the ADC

        //AdcRegs.ADCTRL1.all = 0x0710;
        // bit 15        0:      reserved
        // bit 14        0:      RESET, 0=no action, 1=reset ADC
        // bit 13-12     00:     SUSMOD, 00=ignore emulation suspend
        // bit 11-8      0111:   ACQ_PS (Acquisition), 0111 = 8 x ADCCLK
        // bit 7         0:      CPS (Core clock), 0: ADCCLK=FCLK/1, 1: ADCCLK=FCLK/2
        // bit 6         0:      CONT_RUN, 0=start/stop mode, 1=continuous run
        // bit 5         0:      SEQ_OVRD, 0=disabled, 1=enabled
        // bit 4         1:      SEQ_CASC, 0=dual sequencer, 1=cascaded sequencer
        // bit 3-0       0000:   reserved
        AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascaded mode
        AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // Disable Sequencer override
        AdcRegs.ADCTRL1.bit.CONT_RUN = 0x0; // Start-stop mode
        AdcRegs.ADCTRL1.bit.CPS = 0x0;      // Core Clock Prescaler = 1 (ADCCLK=Fclk/1)
        AdcRegs.ADCTRL1.bit.ACQ_PS = 0x2;   // Acqusition window size
        AdcRegs.ADCTRL1.bit.SUSMOD = 0x0;   // Emulation-suspend mode

        //AdcRegs.ADCTRL2.all = 0x0900;
        // bit 15        0:      ePWM_SOCB_SEQ, 0=no action
        // bit 14        0:      RST_SEQ1, 0=no action
        // bit 13        0:      SOC_SEQ1, 0=clear any pending SOCs
        // bit 12        0:      reserved
        // bit 11        1:      INT_ENA_SEQ1, 1=enable interrupt
        // bit 10        0:      INT_MOD_SEQ1, 0=int on every SEQ1 conv
        // bit 9         0:      reserved
        // bit 8         1:      ePWM_SOCA_SEQ1, 1=SEQ1 start from ePWM_SOCA trigger
        // bit 7         0:      EXT_SOC_SEQ1, 1=SEQ1 start from ADCSOC pin
        // bit 6         0:      RST_SEQ2, 0=no action
        // bit 5         0:      SOC_SEQ2, no effect in cascaded mode
        // bit 4         0:      reserved
        // bit 3         0:      INT_ENA_SEQ2, 0=int disabled
        // bit 2         0:      INT_MOD_SEQ2, 0=int on every other SEQ2 conv
        // bit 1         0:      reserved
        // bit 0         0:      ePWM_SOCB_SEQ2, 0=no action
        AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ2 = 0x0;   // ePWM SOCB enable bit for SEQ2
        AdcRegs.ADCTRL2.bit.INT_MOD_SEQ2 = 0x0;     // SEQ2 interrupt mode
        AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2 = 0x0;     // SEQ2 interrupt enable
        AdcRegs.ADCTRL2.bit.SOC_SEQ2 = 0x0;         // SOC SEQ2
        AdcRegs.ADCTRL2.bit.RST_SEQ2 = 0x0;         // Reset SEQ2

        AdcRegs.ADCTRL2.bit.EXT_SOC_SEQ1 = 0x0;     // external SOC SEQ1
        AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 0x0;   // ePWM SOCB enable bit for SEQ1
        AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0;     // SEQ1 interrupt mode
        AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;     // SEQ1 interrupt enable
        AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x0;         // SOC SEQ1
        AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;         // Reset SEQ1
        AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ = 0x0;        // ePWM SOCB enable for cascaded sequencer


        AdcRegs.ADCMAXCONV.all = 15;
        // bit 15-7      0's:    reserved
        // bit 6-4       000:    MAX_CONV2 value
        // bit 3-0       0000:   MAX_CONV1 value (0 means 1 conversion)

        // Since we are only doing 1 conversion in the sequence, we only need to
        // configure the ADCCHSELSEQ1 register, and only the CONV00 field.  All
        // other channel selection fields are don't cares in this example.
        //AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0;  // Convert Channel 0
        AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA3 as 1st SEQ conv.
        AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup ADCINA2 as 2nd SEQ conv.
        AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup ADCINA2 as 3nd SEQ conv.
        AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup ADCINA2 as 4nd SEQ conv.

        AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Setup ADCINA3 as 5st SEQ conv.
        AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Setup ADCINA2 as 6nd SEQ conv.
        AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Setup ADCINA2 as 7nd SEQ conv.
        AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; // Setup ADCINA2 as 8nd SEQ conv.

        AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8; // Setup ADCINA3 as 9st SEQ conv.
        AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9; // Setup ADCINA2 as 10nd SEQ conv.
        AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xA; // Setup ADCINA2 as 11nd SEQ conv.
        AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xB; // Setup ADCINA2 as 12nd SEQ conv.

        AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xC; // Setup ADCINA3 as 13st SEQ conv.
        AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xD; // Setup ADCINA2 as 14nd SEQ conv.
        AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0xE; // Setup ADCINA2 as 15nd SEQ conv.
        AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0xF; // Setup ADCINA2 as 16nd SEQ conv.
        //
        //
        //
        m_mode = DSP28335::ADC::OPERATIONAL;
    //
    }//end if
    //
}//end
//.TI.ramfunc
// #pragma CODE_SECTION("ramfuncs");
bool DSP28335::ADC::is_ready()
{
    return m_status;
    //
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::clear_status()
{
    m_status = false;
    //
}//end

// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::sw_soc_seq1()
{
    if(m_mode == DSP28335::ADC::OPERATIONAL)
    {
        AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;
        //
    }//if
    //
}//end
//

// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::sw_soc_seq2()
{
    if(m_mode == DSP28335::ADC::OPERATIONAL)
    {
        AdcRegs.ADCTRL2.bit.SOC_SEQ2 = 1;
        //
    }//if
    //
}//end

// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::interrupt_ack()
{
    m_status = true;

    //AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
    //PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;

    // Reinitialize for next ADC sequence
    AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;         // Reset SEQ1
    AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;       // Clear INT SEQ1 bit
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;   // Acknowledge interrupt to PIE
    //
}//end
//

} /* namespace DSP28335 */