/*
 * XINTF.cpp
 *
 *      Author: Aleksey Gerasimenko
 *      gerasimenko.aleksey.n@gmail.com
 */

#include "DSP28335/XINTF.h"

namespace DSP28335
{
//CONSTRUCTOR
XINTF::XINTF():
        CPUBase(),
        _gpio_setup(&DSP28335::GPIO::gpio_xintf_16bit_setup)
{}//CONSTRUCTOR


void XINTF::setup(DSP28335::XINTFSetup& setup)
{

    if(m_mode == DSP28335::XINTF::UNDEFINED)
    {
        //
        // This shows how to write to the XINTF registers.  The
        // values used here are the default state after reset.
        // Different hardware will require a different configuration.
        //


        //
        // Any changes to XINTF timing should only be made by code
        // running outside of the XINTF.
        //

        //
        //                       All Zones
        // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
        //


        //struct XINTCNF2_BITS {     // bits  description
        //    Uint16 WRBUFF:2;       // 1:0   Write buffer depth
        //    Uint16 CLKMODE:1;      // 2     Ratio for XCLKOUT with respect to XTIMCLK
        //    Uint16 CLKOFF:1;       // 3     Disable XCLKOUT
        //    Uint16 rsvd1:2;        // 5:4   reserved
        //    Uint16 WLEVEL:2;       // 7:6   Current level of the write buffer
        //    Uint16 rsvd2:1;        // 8     reserved
        //    Uint16 HOLD:1;         // 9     Hold enable/disable
        //    Uint16 HOLDS:1;        // 10    Current state of HOLDn input
        //    Uint16 HOLDAS:1;       // 11    Current state of HOLDAn output
        //    Uint16 rsvd3:4;        // 15:12 reserved
        //    Uint16 XTIMCLK:3;      // 18:16 Ratio for XTIMCLK
        //    Uint16 rsvd4:13;       // 31:19 reserved
        //};

        EALLOW;
        XintfRegs.XINTCNF2.bit.XTIMCLK = 1;

        //
        // No write buffering
        //
        XintfRegs.XINTCNF2.bit.WRBUFF = 0;

        //
        // XCLKOUT is enabled
        //
        XintfRegs.XINTCNF2.bit.CLKOFF = 0;

        //
        // XCLKOUT = XTIMCLK/2
        //
        XintfRegs.XINTCNF2.bit.CLKMODE = 1;

        //
        // WLEVEL
        //
        XintfRegs.XINTCNF2.bit.WLEVEL = 0;

        //
        // HOLD
        //
        XintfRegs.XINTCNF2.bit.HOLD = 0;

        //
        // HOLDS
        //
        XintfRegs.XINTCNF2.bit.HOLDS = 1;

        //
        // HOLDAS
        //
        XintfRegs.XINTCNF2.bit.HOLDAS = 1;

        //
        //                       Zone 0
        // When using ready, ACTIVE must be 1 or greater
        // Lead must always be 1 or greater
        // Zone write timing
        //
        XintfRegs.XTIMING0.bit.XWRLEAD = 3;
        XintfRegs.XTIMING0.bit.XWRACTIVE = 5; // default 7;
        XintfRegs.XTIMING0.bit.XWRTRAIL = 1;  // default 3;

        //
        // Zone read timing
        //
        XintfRegs.XTIMING0.bit.XRDLEAD = 3;
        XintfRegs.XTIMING0.bit.XRDACTIVE = 5; // default 7;
        XintfRegs.XTIMING0.bit.XRDTRAIL = 1;  // default 3;

        //
        // double all Zone read/write lead/active/trail timing
        //
        XintfRegs.XTIMING0.bit.X2TIMING = 1;

        //
        // Zone will sample XREADY signal
        //
        XintfRegs.XTIMING0.bit.USEREADY = 1;
        XintfRegs.XTIMING0.bit.READYMODE = 1;  // sample asynchronous

        //
        // Size must be either:
        // 0,1 = x32 or
        // 1,1 = x16 other values are reserved
        //
        XintfRegs.XTIMING0.bit.XSIZE = 3;

        //
        //                  Zone 6
        // When using ready, ACTIVE must be 1 or greater
        // Lead must always be 1 or greater
        // Zone write timing
        //
        XintfRegs.XTIMING6.bit.XWRLEAD = 3;
        XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
        XintfRegs.XTIMING6.bit.XWRTRAIL = 3;

        //
        // Zone read timing
        //
        XintfRegs.XTIMING6.bit.XRDLEAD = 3;
        XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
        XintfRegs.XTIMING6.bit.XRDTRAIL = 3;

        //
        // double all Zone read/write lead/active/trail timing
        //
        XintfRegs.XTIMING6.bit.X2TIMING = 1;

        //
        // Zone will sample XREADY signal
        //
        XintfRegs.XTIMING6.bit.USEREADY = 1;
        XintfRegs.XTIMING6.bit.READYMODE = 1;  // sample asynchronous

        //
        // Size must be either:
        // 0,1 = x32 or
        // 1,1 = x16 other values are reserved
        //
        XintfRegs.XTIMING6.bit.XSIZE = 3;

        //
        //                 Zone 7
        // When using ready, ACTIVE must be 1 or greater
        // Lead must always be 1 or greater
        // Zone write timing
        //
        XintfRegs.XTIMING7.bit.XWRLEAD = 3;
        XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
        XintfRegs.XTIMING7.bit.XWRTRAIL = 3;

        //
        // Zone read timing
        //
        XintfRegs.XTIMING7.bit.XRDLEAD = 3;
        XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
        XintfRegs.XTIMING7.bit.XRDTRAIL = 3;

        //
        // double all Zone read/write lead/active/trail timing
        //
        XintfRegs.XTIMING7.bit.X2TIMING = 1;

        //
        // Zone will sample XREADY signal
        //
        XintfRegs.XTIMING7.bit.USEREADY = 1;
        XintfRegs.XTIMING7.bit.READYMODE = 1;  // sample asynchronous

        //
        // Size must be either:
        // 0,1 = x32 or
        // 1,1 = x16 other values are reserved
        //
        XintfRegs.XTIMING7.bit.XSIZE = 3;

        //
        // Bank switching
        // Assume Zone 7 is slow, so add additional BCYC cycles
        // when ever switching from Zone 7 to another Zone.
        // This will help avoid bus contention.
        //
        XintfRegs.XBANK.bit.BANK = 7;
        XintfRegs.XBANK.bit.BCYC = 7;
        EDIS;

        //
        // Force a pipeline flush to ensure that the write to the last register
        // configured occurs before returning.
        //
        asm(" RPT #7 || NOP");

        if(setup.gpio_setup != 0)
        {
            _gpio_setup = setup.gpio_setup;
            //
            (*_gpio_setup)();
            //
            m_mode = DSP28335::XINTF::OPERATIONAL;
            m_status = true;
            //
        }//if
        //
    }//if
    //
}//
//

} /* namespace DSP28335 */