/* * ADCCTRL.cpp * * Author: Aleksey Gerasimenko * gerasimenko.aleksey.n@gmail.com */ #include "SYSCTRL/ADCCTRL.h" namespace SYSCTRL { //CONSTRUCTOR ADCCTRL::ADCCTRL(): m_time_sample(-1.0), m_result_00(0), m_result_01(0), m_result_02(0), m_result_03(0), m_result_04(0), m_result_05(0), m_result_06(0), m_result_07(0), m_result_08(0), m_result_09(0), m_result_10(0), m_result_11(0), m_result_12(0), m_result_13(0), m_result_14(0), m_result_15(0), // m_channel_00(0), m_channel_01(0), m_channel_02(0), m_channel_03(0), m_channel_04(0), m_channel_05(0), m_channel_06(0), m_channel_07(0), m_channel_08(0), m_channel_09(0), m_channel_10(0), m_channel_11(0), m_channel_12(0), m_channel_13(0), m_channel_14(0), m_channel_15(0), // m_offset_00(0), m_offset_01(0), m_offset_02(0), m_offset_03(0), m_offset_04(0), m_offset_05(0), m_offset_06(0), m_offset_07(0), m_offset_08(0), m_offset_09(0), m_offset_10(0), m_offset_11(0), m_offset_12(0), m_offset_13(0), m_offset_14(0), m_offset_15(0), // m_scale_channel_00(-1.0), m_scale_channel_01(-1.0), m_scale_channel_02(-1.0), m_scale_channel_03(-1.0), m_scale_channel_04(-1.0), m_scale_channel_05(-1.0), m_scale_channel_06(-1.0), m_scale_channel_07(-1.0), m_scale_channel_08(-1.0), m_scale_channel_09(-1.0), m_scale_channel_10(-1.0), m_scale_channel_11(-1.0), m_scale_channel_12(-1.0), // _read_adc_result(&SYSCTRL::ADCCTRL::_read_adc_result_undef) // {}//end CONSTRUCTOR void ADCCTRL::setup(const ADCCTRLSetup& setup) { // if(setup.time_sample > FP_ZERO) { m_time_sample = setup.time_sample; } else { m_time_sample = -1.0; } // }//end // void ADCCTRL::configure(const ADCCTRLConfiguration& config) { static bool _state_config = true; if(m_time_sample > FP_ZERO) { m_offset_00 = config.offset_00; m_offset_01 = config.offset_01; m_offset_02 = config.offset_02; m_offset_03 = config.offset_03; m_offset_04 = config.offset_04; m_offset_05 = config.offset_05; m_offset_06 = config.offset_06; m_offset_07 = config.offset_07; m_offset_08 = config.offset_08; m_offset_09 = config.offset_09; m_offset_10 = config.offset_10; m_offset_11 = config.offset_11; m_offset_12 = config.offset_12; m_offset_13 = config.offset_13; m_offset_14 = config.offset_14; m_offset_15 = config.offset_15; m_scale_channel_00 = config.scale_current_net_a; m_scale_channel_01 = config.scale_current_net_b; m_scale_channel_02 = config.scale_current_net_c; m_scale_channel_03 = config.scale_current_load_a; m_scale_channel_04 = config.scale_current_load_b; m_scale_channel_05 = config.scale_current_load_c; m_scale_channel_06 = config.scale_voltage_net_a; m_scale_channel_07 = config.scale_voltage_net_b; m_scale_channel_08 = config.scale_voltage_net_c; m_scale_channel_09 = config.scale_voltage_load_a; m_scale_channel_10 = config.scale_voltage_load_b; m_scale_channel_11 = config.scale_voltage_load_c; m_scale_channel_12 = config.scale_voltage_dc; _state_config &= m_offset_00 >= 0 ? true : false; _state_config &= m_offset_01 >= 0 ? true : false; _state_config &= m_offset_02 >= 0 ? true : false; _state_config &= m_offset_03 >= 0 ? true : false; _state_config &= m_offset_04 >= 0 ? true : false; _state_config &= m_offset_05 >= 0 ? true : false; _state_config &= m_offset_06 >= 0 ? true : false; _state_config &= m_offset_07 >= 0 ? true : false; _state_config &= m_offset_08 >= 0 ? true : false; _state_config &= m_offset_09 >= 0 ? true : false; _state_config &= m_offset_10 >= 0 ? true : false; _state_config &= m_offset_11 >= 0 ? true : false; _state_config &= m_offset_12 >= 0 ? true : false; _state_config &= m_offset_13 >= 0 ? true : false; _state_config &= m_offset_14 >= 0 ? true : false; _state_config &= m_offset_15 >= 0 ? true : false; _state_config &= m_scale_channel_00 > FP_ZERO ? true : false; _state_config &= m_scale_channel_01 > FP_ZERO ? true : false; _state_config &= m_scale_channel_02 > FP_ZERO ? true : false; _state_config &= m_scale_channel_03 > FP_ZERO ? true : false; _state_config &= m_scale_channel_04 > FP_ZERO ? true : false; _state_config &= m_scale_channel_05 > FP_ZERO ? true : false; _state_config &= m_scale_channel_06 > FP_ZERO ? true : false; _state_config &= m_scale_channel_07 > FP_ZERO ? true : false; _state_config &= m_scale_channel_08 > FP_ZERO ? true : false; _state_config &= m_scale_channel_09 > FP_ZERO ? true : false; _state_config &= m_scale_channel_10 > FP_ZERO ? true : false; _state_config &= m_scale_channel_11 > FP_ZERO ? true : false; _state_config &= m_scale_channel_12 > FP_ZERO ? true : false; if(_state_config) { _read_adc_result = &SYSCTRL::ADCCTRL::_read_adc_result_operational; // }//end if // }//end if // }//end // #pragma CODE_SECTION("ramfuncs"); void ADCCTRL::read_adc_result() { (this->*_read_adc_result)(); // }//end // #pragma CODE_SECTION("ramfuncs"); void ADCCTRL::_read_adc_result_undef() {}//end // #pragma CODE_SECTION("ramfuncs"); void ADCCTRL::_read_adc_result_operational() { m_result_00 = (Uint16)(AdcRegs.ADCRESULT0>>4); //INA m_result_01 = (Uint16)(AdcRegs.ADCRESULT1>>4); //INB m_result_02 = (Uint16)(AdcRegs.ADCRESULT2>>4); //INC m_result_03 = (Uint16)(AdcRegs.ADCRESULT3>>4); //ILA m_result_04 = (Uint16)(AdcRegs.ADCRESULT4>>4); //ILB m_result_05 = (Uint16)(AdcRegs.ADCRESULT5>>4); //ILC m_result_06 = (Uint16)(AdcRegs.ADCRESULT6>>4); //UNA m_result_07 = (Uint16)(AdcRegs.ADCRESULT7>>4); //UNB m_result_08 = (Uint16)(AdcRegs.ADCRESULT8>>4); //UNC m_result_09 = (Uint16)(AdcRegs.ADCRESULT9>>4); //ULA m_result_10 = (Uint16)(AdcRegs.ADCRESULT10>>4); //ULB m_result_11 = (Uint16)(AdcRegs.ADCRESULT11>>4); //ULC m_result_12 = (Uint16)(AdcRegs.ADCRESULT12>>4); //UDC m_result_13 = (Uint16)(AdcRegs.ADCRESULT13>>4); // m_result_14 = (Uint16)(AdcRegs.ADCRESULT14>>4); // m_result_15 = (Uint16)(AdcRegs.ADCRESULT15>>4); // // m_channel_00 = (int16)((int16)m_result_00 - (int16)m_offset_00); m_channel_01 = (int16)((int16)m_result_01 - (int16)m_offset_01); m_channel_02 = (int16)((int16)m_result_02 - (int16)m_offset_02); m_channel_03 = (int16)((int16)m_result_03 - (int16)m_offset_03); m_channel_04 = (int16)((int16)m_result_04 - (int16)m_offset_04); m_channel_05 = (int16)((int16)m_result_05 - (int16)m_offset_05); m_channel_06 = (int16)((int16)m_result_06 - (int16)m_offset_06); m_channel_07 = (int16)((int16)m_result_07 - (int16)m_offset_07); m_channel_08 = (int16)((int16)m_result_08 - (int16)m_offset_08); m_channel_09 = (int16)((int16)m_result_09 - (int16)m_offset_09); m_channel_10 = (int16)((int16)m_result_10 - (int16)m_offset_10); m_channel_11 = (int16)((int16)m_result_11 - (int16)m_offset_11); m_channel_12 = (int16)((int16)m_result_12 - (int16)m_offset_12); m_channel_13 = (int16)((int16)m_result_13 - (int16)m_offset_13); m_channel_14 = (int16)((int16)m_result_14 - (int16)m_offset_14); m_channel_15 = (int16)((int16)m_result_15 - (int16)m_offset_15); // }//end // #pragma CODE_SECTION("ramfuncs"); void ADCCTRL::get_current_net(float& current_net_a, float& current_net_b, float& current_net_c) { current_net_a = m_scale_channel_00 * (float)m_channel_00; current_net_b = m_scale_channel_01 * (float)m_channel_01; current_net_c = m_scale_channel_02 * (float)m_channel_02; // }//end // #pragma CODE_SECTION("ramfuncs"); void ADCCTRL::get_current_load(float& current_load_a, float& current_load_b, float& current_load_c) { current_load_a = m_scale_channel_03 * (float)m_channel_03; current_load_b = m_scale_channel_04 * (float)m_channel_04; current_load_c = m_scale_channel_05 * (float)m_channel_05; // }//end // #pragma CODE_SECTION("ramfuncs"); void ADCCTRL::get_voltage_net(float& voltage_net_a, float& voltage_net_b, float& voltage_net_c) { voltage_net_a = m_scale_channel_06 * (float)m_channel_06; voltage_net_b = m_scale_channel_07 * (float)m_channel_07; voltage_net_c = m_scale_channel_08 * (float)m_channel_08; // }//end // #pragma CODE_SECTION("ramfuncs"); void ADCCTRL::get_voltage_load(float& voltage_load_a, float& voltage_load_b, float& voltage_load_c) { voltage_load_a = m_scale_channel_09 * (float)m_channel_09; voltage_load_b = m_scale_channel_10 * (float)m_channel_10; voltage_load_c = m_scale_channel_11 * (float)m_channel_11; // }//end // #pragma CODE_SECTION("ramfuncs"); void ADCCTRL::get_voltage_dc(float& voltage_dc) { voltage_dc = m_scale_channel_12 * (float)m_channel_12; // }//end // } /* namespace HAL */