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#include "CAN.h"
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#include "DSP2833x_ECan.h"
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namespace can_space {
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CAN::CAN(CAN_VARIANT canVariant) :
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_canPort(canVariant),
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_p_CanRegs(0),
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_p_CanMBoxes(0),
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_p_CanMotoRegs(0),
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_p_CanMotsRegs(0)
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{}
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void CAN::initGpio(){
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if(_canPort == CANA) InitECanaGpio();
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else if (_canPort == CANB) InitECanbGpio();
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}
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void CAN::config(uint16_t baudrate, uint16_t flags){
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if (_canPort == CANA){
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 1;
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EDIS;
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_p_CanRegs = &ECanaRegs;
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_p_CanMBoxes = &ECanaMboxes;
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_p_CanMotoRegs = &ECanaMOTORegs;
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_p_CanMotsRegs = &ECanaMOTSRegs;
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}
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else if (_canPort == CANB){
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EALLOW;
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SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 1;
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EDIS;
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_p_CanRegs = &ECanbRegs;
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_p_CanMBoxes = &ECanbMboxes;
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_p_CanMotoRegs = &ECanbMOTORegs;
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_p_CanMotsRegs = &ECanbMOTSRegs;
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}
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else { return; }
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// Create a shadow register structure for the CAN control registers. This // TODO add this into description
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// is needed, since only 32-bit access is allowed to these registers.
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// 16-bit access to these registers could potentially corrupt the register
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// contents or return false data. This is especially true while writing
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// to/reading from a bit (or group of bits) among bits 16 - 31
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EALLOW;
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// Configure eCAN RX and TX pins for CAN operation using eCAN regs
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_CanShadow.CANTIOC.all = _p_CanRegs->CANTIOC.all;
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_CanShadow.CANTIOC.bit.TXFUNC = 1;
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_p_CanRegs->CANTIOC.all = _CanShadow.CANTIOC.all;
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_CanShadow.CANRIOC.all = _p_CanRegs->CANRIOC.all;
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_CanShadow.CANRIOC.bit.RXFUNC = 1;
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_p_CanRegs->CANRIOC.all = _CanShadow.CANRIOC.all;
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// Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31)
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// HECC mode also enables time-stamping feature
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_CanShadow.CANMC.all = _p_CanRegs->CANMC.all;
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_CanShadow.CANMC.bit.SCB = 1;
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_p_CanRegs->CANMC.all = _CanShadow.CANMC.all;
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// Initialize all bits of 'Master Control Field' to zero
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// Some bits of MSGCTRL register come up in an unknown state. For proper
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// operation, all bits (including reserved bits) of MSGCTRL must be
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// initialized to zero
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_p_CanMBoxes->MBOX0.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX1.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX2.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX3.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX4.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX5.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX6.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX7.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX8.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX9.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX10.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX11.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX12.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX13.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX14.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX15.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX16.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX17.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX18.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX19.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX20.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX21.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX22.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX23.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX24.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX25.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX26.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX27.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX28.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX29.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX30.MSGCTRL.all = 0x00000000;
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_p_CanMBoxes->MBOX31.MSGCTRL.all = 0x00000000;
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// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
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// as a matter of precaution.
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_p_CanRegs->CANTA.all = 0xFFFFFFFF;
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_p_CanRegs->CANRMP.all = 0xFFFFFFFF;
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_p_CanRegs->CANGIF0.all = 0xFFFFFFFF;
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_p_CanRegs->CANGIF1.all = 0xFFFFFFFF;
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// Configure bit timing parameters for eCANA
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_CanShadow.CANMC.all = _p_CanRegs->CANMC.all;
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_CanShadow.CANMC.bit.CCR = 1 ;
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_p_CanRegs->CANMC.all = _CanShadow.CANMC.all;
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do { _CanShadow.CANES.all = _p_CanRegs->CANES.all; }
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while(_CanShadow.CANES.bit.CCE != 1 );
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// MSB - 0; LSB - 1
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_CanShadow.CANMC.all = _p_CanRegs->CANMC.all;
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if (flags & MSB_ENABLE){
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_CanShadow.CANMC.bit.DBO = 0;
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}
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else
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{ _CanShadow.CANMC.bit.DBO = 1; }
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_p_CanRegs->CANMC.all = _CanShadow.CANMC.all;
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_CanShadow.CANBTC.all = 0;
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// The following block for all 150 MHz SYSCLKOUT
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// (75 MHz CAN clock) - default. Bit rate = 1 Mbps / 500 kbps / 250 kbps / 100 kbps
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switch (baudrate) {
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case 1000:
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_CanShadow.CANBTC.bit.BRPREG = 4;
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_CanShadow.CANBTC.bit.TSEG2REG = 3;
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_CanShadow.CANBTC.bit.TSEG1REG = 9;
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break;
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case 500:
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_CanShadow.CANBTC.bit.BRPREG = 9;
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_CanShadow.CANBTC.bit.TSEG2REG = 3;
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_CanShadow.CANBTC.bit.TSEG1REG = 9;
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break;
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case 250:
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_CanShadow.CANBTC.bit.BRPREG = 19;
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_CanShadow.CANBTC.bit.TSEG2REG = 3;
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_CanShadow.CANBTC.bit.TSEG1REG = 9;
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break;
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case 100:
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_CanShadow.CANBTC.bit.BRPREG = 49;
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_CanShadow.CANBTC.bit.TSEG2REG = 3;
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_CanShadow.CANBTC.bit.TSEG1REG = 9;
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break;
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default: return;
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}
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_CanShadow.CANBTC.bit.SAM = 1;
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_p_CanRegs->CANBTC.all = _CanShadow.CANBTC.all;
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_CanShadow.CANMC.all = _p_CanRegs->CANMC.all;
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_CanShadow.CANMC.bit.CCR = 0 ;
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_p_CanRegs->CANMC.all = _CanShadow.CANMC.all;
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do { _CanShadow.CANES.all = _p_CanRegs->CANES.all; }
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while(_CanShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared
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_CanShadow.CANMC.all = _p_CanRegs->CANMC.all;
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_CanShadow.CANMC.bit.ABO = 1;
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_p_CanRegs->CANMC.all = _CanShadow.CANMC.all;
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// Disable all Mailboxes
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_p_CanRegs->CANME.all = 0;
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// Disable all interrupts
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_p_CanRegs->CANGIM.all = 0;
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_p_CanRegs->CANMIM.all = 0;
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//
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// Debug feature
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// Configure the eCAN for self test mode.
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_CanShadow.CANMC.all = _p_CanRegs->CANMC.all;
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if (flags & STM_ENABLE){
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_CanShadow.CANMC.bit.STM = 1;
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}
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else
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{ _CanShadow.CANMC.bit.STM = 0; }
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_p_CanRegs->CANMC.all = _CanShadow.CANMC.all;
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EDIS;
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}
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void CAN::configTxMBox(uint16_t boxNumber, const MsgID& configID, const MsgCtrlReg& configCtrlReg){
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if (boxNumber > 31) return;
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volatile MBOX* p_MailBox(0);
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p_MailBox = &(_p_CanMBoxes->MBOX0) + boxNumber;
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uint32_t mboxControl(0);
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mboxControl = 1ul << boxNumber;
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// Reset transmittion
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if (_CanShadow.CANTRS.all &= mboxControl)
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{
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_CanShadow.CANTRR.all = _p_CanRegs->CANTRR.all;
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_CanShadow.CANTRR.all |= mboxControl;
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_p_CanRegs->CANTRR.all = _CanShadow.CANTRR.all;
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do {_CanShadow.CANTRS.all = _p_CanRegs->CANTRS.all;}
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while((_CanShadow.CANTRS.all & mboxControl) != 0); // Wait for TRS bit to be cleared
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}
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// Mailbox disable
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_CanShadow.CANME.all = _p_CanRegs->CANME.all;
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_CanShadow.CANME.all &= ~(mboxControl);
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_p_CanRegs->CANME.all = _CanShadow.CANME.all;
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// Write to the MSGID field
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p_MailBox->MSGID.all = configID.all;
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// Mailbox direction - transmit
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_CanShadow.CANMD.all = _p_CanRegs->CANMD.all;
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_CanShadow.CANMD.all &= ~(mboxControl);
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_p_CanRegs->CANMD.all = _CanShadow.CANMD.all;
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// Config MBOX control reg
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p_MailBox->MSGCTRL.all = configCtrlReg.all;
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// Mailbox enable
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_CanShadow.CANME.all = _p_CanRegs->CANME.all;
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_CanShadow.CANME.all |= mboxControl;
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_p_CanRegs->CANME.all = _CanShadow.CANME.all;
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}
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void CAN::configRxMBox(uint16_t boxNumber, const MsgID& configID, const MsgCtrlReg& configCtrlReg){
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if (boxNumber > 31) return;
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volatile MBOX* p_MailBox(0);
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p_MailBox = &(_p_CanMBoxes->MBOX0) + boxNumber;
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uint32_t mboxControl(0);
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mboxControl = 1ul << boxNumber;
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// Mailbox disable
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_CanShadow.CANME.all = _p_CanRegs->CANME.all;
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_CanShadow.CANME.all &= ~(mboxControl);
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_p_CanRegs->CANME.all = _CanShadow.CANME.all;
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// Write to the MSGID field
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p_MailBox->MSGID.all = 0x0;
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p_MailBox->MSGID.all = configID.all;
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// Write to DLC and RTR field in control reg
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p_MailBox->MSGCTRL.bit.DLC = configCtrlReg.bit.DLC;
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p_MailBox->MSGCTRL.bit.RTR = configCtrlReg.bit.RTR;
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// Configure Mailbox under test as a Receive mailbox
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_CanShadow.CANMD.all = _p_CanRegs->CANMD.all;
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_CanShadow.CANMD.all |= mboxControl;
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_p_CanRegs->CANMD.all = _CanShadow.CANMD.all;
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// Overwrite protection
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// If "ON" make sure that an additional mailbox is configured to store ’overflow’ messages.
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if(configCtrlReg.bit.OPC){
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_CanShadow.CANOPC.all = _p_CanRegs->CANOPC.all;
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_CanShadow.CANOPC.all |= mboxControl;
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_p_CanRegs->CANOPC.all = _CanShadow.CANOPC.all;
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}
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// Enable Mailbox
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_CanShadow.CANME.all = _p_CanRegs->CANME.all;
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_CanShadow.CANME.all |= mboxControl;
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_p_CanRegs->CANME.all = _CanShadow.CANME.all;
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}
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void CAN::configSystemIsr(uint32_t flags){
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EALLOW;
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_p_CanRegs->CANGIM.all = flags;
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EDIS;
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}
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void CAN::configMBoxIsr(uint16_t boxNumber){
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if (boxNumber > 31) return;
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uint32_t mboxControl(0);
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mboxControl = 1ul << boxNumber;
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EALLOW;
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_p_CanRegs->CANMIL.all |= mboxControl;
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_p_CanRegs->CANMIM.all |= mboxControl;
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EDIS;
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}
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void CAN::enableTimeOutControl(uint16_t boxNumber){
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if (boxNumber > 31) return;
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uint32_t mboxControl(0);
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mboxControl = _p_CanRegs->CANTOC.all;
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mboxControl |= 1ul << boxNumber;
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_p_CanRegs->CANTOC.all = mboxControl;
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}
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void CAN::disableTimeOutControl(uint16_t boxNumber){
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if (boxNumber > 31) return;
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uint32_t mboxControl(0);
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mboxControl = _p_CanRegs->CANTOC.all;
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mboxControl &= ~(1ul << boxNumber);
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_p_CanRegs->CANTOC.all = mboxControl;
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}
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} //can_space
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