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394 lines
13 KiB
C++
394 lines
13 KiB
C++
4 weeks ago
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/*
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* PWMSingleInterace.cpp
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*
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* Author: Aleksey Gerasimenko
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* gerasimenko.aleksey.n@gmail.com
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*/
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#include "PERIPHERY/PWMSInterace.h"
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namespace PERIPHERY
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{
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//CONSTRUCTOR
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PWMSInterace::PWMSInterace():
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PWMInterface(),
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m_phase(),
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//
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_telemetry_execute(&PWMSInterace::_telemetry_sequence_one)
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//
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{}//CONSTRUCTOR
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//
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void PWMSInterace::setup(uint16_t *memzone)
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{
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_setup_phase(m_phase, memzone + OFFSET_PWM_PHASE);
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m_broadcast.p_order = memzone + OFFSET_BROADCAST_ORDER;
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m_broadcast.p_cell_quantity_in_phase = memzone + OFFSET_BROADCAST_CELLNUMBER;
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m_broadcast.p_freq = memzone + OFFSET_BROADCAST_FREQ;
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//
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_gpio_hard_fault_setup = &DSP28335::GPIO::gpio_hard_fault_setup;
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_hard_fault_read = &DSP28335::GPIO::gpio_hard_fault_read;
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(*_gpio_hard_fault_setup)();
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//
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set_telemetry_sequence_one();
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//
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}//
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//
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//
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void PWMSInterace::setup(const PWMStructureSetup& setup)
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{
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_gpio_hard_fault_setup = setup.p_gpio_hard_fault_setup;
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_hard_fault_read = setup.p_hard_fault_read;
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(*_gpio_hard_fault_setup)();
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set_telemetry_sequence_one();
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//
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}//
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//
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void PWMSInterace::setup(uint16_t *memzone, const PWMStructureSetup& setup)
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{
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_setup_phase(m_phase, memzone + OFFSET_PWM_PHASE);
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m_broadcast.p_order = memzone + OFFSET_BROADCAST_ORDER;
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m_broadcast.p_cell_quantity_in_phase = memzone + OFFSET_BROADCAST_CELLNUMBER;
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m_broadcast.p_freq = memzone + OFFSET_BROADCAST_FREQ;
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//
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_gpio_hard_fault_setup = setup.p_gpio_hard_fault_setup;
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_hard_fault_read = setup.p_hard_fault_read;
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(*_gpio_hard_fault_setup)();
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set_telemetry_sequence_one();
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//
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}//
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//
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void PWMSInterace::_setup_phase(PWMPhaseStructure& phase, uint16_t *base)
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{
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phase.p_pwm_frequency = base + OFFSET_FREQ_PWM;
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phase.p_cell_quantity_in_phase = base + OFFSET_CQ_IN_PHASE;
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phase.p_compare = base + OFFSET_CMP;
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phase.p_order = base + OFFSET_ORDER;
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phase.p_pwm_state = base + OFFSET_PWM_STATE;
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phase.p_pwm_version = base + OFFSET_PWM_VERSION;
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phase.a_cell_quantity_in_cascade[0] = base + OFFSET_CQ_IN_CASC_00;
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phase.a_cell_quantity_in_cascade[1] = base + OFFSET_CQ_IN_CASC_01;
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phase.a_cell_quantity_in_cascade[2] = base + OFFSET_CQ_IN_CASC_02;
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phase.a_cell_quantity_in_cascade[3] = base + OFFSET_CQ_IN_CASC_03;
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phase.a_cell_quantity_in_cascade[4] = base + OFFSET_CQ_IN_CASC_04;
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phase.a_cell_quantity_in_cascade[5] = base + OFFSET_CQ_IN_CASC_05;
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phase.a_cell_quantity_in_cascade[6] = base + OFFSET_CQ_IN_CASC_06;
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phase.a_cell_quantity_in_cascade[7] = base + OFFSET_CQ_IN_CASC_07;
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phase.a_cell_quantity_in_cascade[8] = base + OFFSET_CQ_IN_CASC_08;
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phase.a_cell_quantity_in_cascade[9] = base + OFFSET_CQ_IN_CASC_09;
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phase.a_cell_quantity_in_cascade[10] = base + OFFSET_CQ_IN_CASC_10;
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phase.a_cell_quantity_in_cascade[11] = base + OFFSET_CQ_IN_CASC_11;
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phase.a_cell_quantity_in_cascade[12] = base + OFFSET_CQ_IN_CASC_12;
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phase.a_cell_quantity_in_cascade[13] = base + OFFSET_CQ_IN_CASC_13;
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phase.a_cell_quantity_in_cascade[14] = base + OFFSET_CQ_IN_CASC_14;
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phase.a_cell_quantity_in_cascade[15] = base + OFFSET_CQ_IN_CASC_15;
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phase.a_cell_quantity_in_cascade[16] = base + OFFSET_CQ_IN_CASC_16;
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phase.a_cell_quantity_in_cascade[17] = base + OFFSET_CQ_IN_CASC_17;
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phase.p_telemetry_box = base + OFFSET_TELEMETRY;
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phase.p_breakdown_cell_state = base + OFFSET_CELL_BREAKDOWN;
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phase.p_breakdown_cell_address = base + OFFSET_CELL_BREAKDOWN_ADR;
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phase.a_cascade_pointers[0] = base + OFFSET_CASCADE_00;
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phase.a_cascade_pointers[1] = base + OFFSET_CASCADE_01;
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phase.a_cascade_pointers[2] = base + OFFSET_CASCADE_02;
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phase.a_cascade_pointers[3] = base + OFFSET_CASCADE_03;
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phase.a_cascade_pointers[4] = base + OFFSET_CASCADE_04;
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phase.a_cascade_pointers[5] = base + OFFSET_CASCADE_05;
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phase.a_cascade_pointers[6] = base + OFFSET_CASCADE_06;
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phase.a_cascade_pointers[7] = base + OFFSET_CASCADE_07;
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phase.a_cascade_pointers[8] = base + OFFSET_CASCADE_08;
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phase.a_cascade_pointers[9] = base + OFFSET_CASCADE_09;
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phase.a_cascade_pointers[10] = base + OFFSET_CASCADE_10;
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phase.a_cascade_pointers[11] = base + OFFSET_CASCADE_11;
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phase.a_cascade_pointers[12] = base + OFFSET_CASCADE_12;
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phase.a_cascade_pointers[13] = base + OFFSET_CASCADE_13;
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phase.a_cascade_pointers[14] = base + OFFSET_CASCADE_14;
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phase.a_cascade_pointers[15] = base + OFFSET_CASCADE_15;
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phase.a_cascade_pointers[16] = base + OFFSET_CASCADE_16;
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phase.a_cascade_pointers[17] = base + OFFSET_CASCADE_17;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::set_frequency(uint16_t freq)
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{
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NOP;
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NOP;
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NOP;
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*m_phase.p_pwm_frequency = freq;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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//void PWMSInterace::set_cascade_quantity(uint16_t quant)
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//{
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//m_config.cascade_quantity = quant;
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//
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//}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::set_cell_quantity_phase(uint16_t quant)
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{
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NOP;
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NOP;
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NOP;
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*m_phase.p_cell_quantity_in_phase = quant;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::set_cmp(uint16_t cmpr)
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{
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NOP;
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NOP;
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NOP;
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*m_phase.p_compare = cmpr;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::set_order(uint16_t order)
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{
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NOP;
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NOP;
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NOP;
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*m_phase.p_order = order;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::get_board_state(uint16_t& state)
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{
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NOP;
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NOP;
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NOP;
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state = *m_phase.p_pwm_state;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::get_sw_version(uint16_t& version)
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{
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NOP;
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NOP;
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NOP;
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version = *m_phase.p_pwm_version;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::get_breakdown_cell_state(uint16_t& cellstate)
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{
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NOP;
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NOP;
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NOP;
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cellstate = *m_phase.p_breakdown_cell_state;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::get_breakdown_cell_index(uint16_t& cellindex)
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{
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NOP;
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NOP;
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NOP;
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cellindex = *m_phase.p_breakdown_cell_address;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::set_cell_quantity_cascade(uint16_t cascadenum, uint16_t quant)
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{
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NOP;
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NOP;
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NOP;
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*m_phase.a_cell_quantity_in_cascade[cascadenum] = quant;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::broadcast_order(uint16_t order)
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{
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NOP;
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NOP;
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NOP;
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*m_broadcast.p_order = order;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::broadcast_cell_quantity_phase(uint16_t quant)
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{
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NOP;
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NOP;
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NOP;
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*m_broadcast.p_cell_quantity_in_phase = quant;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::broadcast_freq(uint16_t freq)
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{
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NOP;
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NOP;
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NOP;
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*m_broadcast.p_freq = freq;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::get_hard_fault(uint16_t& hard_fault)
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{
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(*_hard_fault_read)(m_hard_fault.all);
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hard_fault = m_hard_fault.all;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::get_indirect_access(uint16_t cascade, uint16_t cell, uint16_t offset, uint16_t& telemetry)
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{
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//
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m_aux_pointer = m_phase.a_cascade_pointers[cascade] + m_offset_cells.cell_offset[cell];
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//
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NOP;
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NOP;
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NOP;
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*m_phase.p_telemetry_box = offset;
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telemetry = *m_aux_pointer;
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NOP;
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NOP;
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NOP;
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//
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}//
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//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::telemetry_execute(PWMSInterfaceConfiguration& config, PWMPhaseTelemetryValue& telemetry_phase)
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{
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(this->*_telemetry_execute)(config, telemetry_phase);
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::reset_telemetry()
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{
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m_telemetry_function_counter = 0;
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m_telemetry_cascade_counter = 0;
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m_telemetry_cell_counter = 0;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::set_telemetry_sequence_one()
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{
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m_telemetry_function_counter = 0;
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m_telemetry_cascade_counter = 0;
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m_telemetry_cell_counter = 0;
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//
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_telemetry_execute = &PWMSInterace::_telemetry_sequence_one;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::set_telemetry_sequence_two()
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{
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m_telemetry_function_counter = 0;
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m_telemetry_cascade_counter = 0;
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m_telemetry_cell_counter = 0;
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//
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_telemetry_execute = &PWMSInterace::_telemetry_sequence_two;
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//
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}//
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//
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//#pragma CODE_SECTION("ramfuncs");
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void PWMSInterace::_telemetry_sequence_one(PWMSInterfaceConfiguration& config, PWMPhaseTelemetryValue& telemetry_phase)
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{
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//
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m_telemetry_function_quantity = 11;
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m_telemetry_cascade_quantity = config.cascade_quantity;
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m_telemetry_cell_quantity = config.cell_quantity_in_cascade[m_telemetry_cascade_counter];
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//
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switch(m_telemetry_function_counter)
|
||
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|
{
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||
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|
case 0:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.state, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].state); break;}
|
||
|
|
case 1:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.saw_init_val, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].saw_init_val); break;}
|
||
|
|
case 2:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.version, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].version); break;}
|
||
|
|
case 3:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.t_pcb, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].t_pcb); break;}
|
||
|
|
case 4:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.ctrl_faults, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].ctrl_faults); break;}
|
||
|
|
case 5:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.int_bd_l, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].int_bd_l); break;}
|
||
|
|
case 6:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.voltage, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].voltage); break;}
|
||
|
|
case 7:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.freq_pwm, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].freq_pwm); break;}
|
||
|
|
case 8:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.time_cntr, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].time_cntr); break;}
|
||
|
|
case 9:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.t_rad, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].t_rad); break;}
|
||
|
|
case 10:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.sync_faults, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].sync_faults); break;}
|
||
|
|
case 11:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.int_bd_h, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].int_bd_h); break;}
|
||
|
|
default:{}
|
||
|
|
}//switch
|
||
|
|
//
|
||
|
|
m_telemetry_cell_counter++;
|
||
|
|
if(m_telemetry_cell_counter >= m_telemetry_cell_quantity)
|
||
|
|
{
|
||
|
|
m_telemetry_cell_counter = 0;
|
||
|
|
m_telemetry_cascade_counter++;
|
||
|
|
if(m_telemetry_cascade_counter >= m_telemetry_cascade_quantity)
|
||
|
|
{
|
||
|
|
m_telemetry_cascade_counter = 0;
|
||
|
|
m_telemetry_function_counter++;
|
||
|
|
if(m_telemetry_function_counter > m_telemetry_function_quantity)
|
||
|
|
{
|
||
|
|
m_telemetry_function_counter = 0;
|
||
|
|
}//if
|
||
|
|
//
|
||
|
|
}//if
|
||
|
|
//
|
||
|
|
}//if
|
||
|
|
//
|
||
|
|
}//
|
||
|
|
//
|
||
|
|
//#pragma CODE_SECTION("ramfuncs");
|
||
|
|
void PWMSInterace::_telemetry_sequence_two(PWMSInterfaceConfiguration& config, PWMPhaseTelemetryValue& telemetry_phase)
|
||
|
|
{
|
||
|
|
//
|
||
|
|
}//
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
} /* namespace PERIPHERY */
|