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Clean project. Modbus still working

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feature/Modbus
Oleg 4 weeks ago
parent 9feba6b8c9
commit 5db1783db5
60 changed files with 14 additions and 7823 deletions
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187
DSP28335/ADC.cpp
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/*
* ADC.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/ADC.h"
namespace DSP28335
{
//CONSTRUCTOR
ADC::ADC():
DSP28335::CPUBase(),
m_status(false)
//
{}//end CONSTRUCTOR
//
void DSP28335::ADC::setup()
{
if(m_mode == DSP28335::ADC::UNDEFINED)
{
//--- Configure the other ADC registers
AdcRegs.ADCREFSEL.bit.REF_SEL = 0; // ADC reference, 0=internal, 1=external
//--- Power-up the ADC
//AdcRegs.ADCTRL3.all = 0x00EC; // Power-up reference and main ADC
//AdcRegs.ADCTRL3.all = 0x00F4; // Power-up reference and main ADC /20
//AdcRegs.ADCTRL3.all = 0x00EE; // Power-up reference and main ADC /14
//AdcRegs.ADCTRL3.all = 0x00EA; // Power-up reference and main ADC /10
//AdcRegs.ADCTRL3.all = 0x00E8; // Power-up reference and main ADC /8
//AdcRegs.ADCTRL3.all = 0x00E4; // Power-up reference and main ADC /4
// bit 15-8 0's: reserved
// bit 7-6 11: ADCBGRFDN, reference power, 00=off, 11=on
// bit 5 1: ADCPWDN, main ADC power, 0=off, 1=on
// bit 4-1 0110: ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
// bit 0 0: SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling
AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0008; // bit 4-1 0110: ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0000; // bit 0 0: SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling
AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x0003; // bit 7-6 11: ADCBGRFDN, reference power, 00=off, 11=on
AdcRegs.ADCTRL3.bit.ADCPWDN = 0x0001; // bit 5 1: ADCPWDN, main ADC power, 0=off, 1=on
DELAY_US(5000); // Wait 5 ms before using the ADC
//AdcRegs.ADCTRL1.all = 0x0710;
// bit 15 0: reserved
// bit 14 0: RESET, 0=no action, 1=reset ADC
// bit 13-12 00: SUSMOD, 00=ignore emulation suspend
// bit 11-8 0111: ACQ_PS (Acquisition), 0111 = 8 x ADCCLK
// bit 7 0: CPS (Core clock), 0: ADCCLK=FCLK/1, 1: ADCCLK=FCLK/2
// bit 6 0: CONT_RUN, 0=start/stop mode, 1=continuous run
// bit 5 0: SEQ_OVRD, 0=disabled, 1=enabled
// bit 4 1: SEQ_CASC, 0=dual sequencer, 1=cascaded sequencer
// bit 3-0 0000: reserved
AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascaded mode
AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // Disable Sequencer override
AdcRegs.ADCTRL1.bit.CONT_RUN = 0x0; // Start-stop mode
AdcRegs.ADCTRL1.bit.CPS = 0x0; // Core Clock Prescaler = 1 (ADCCLK=Fclk/1)
AdcRegs.ADCTRL1.bit.ACQ_PS = 0x2; // Acqusition window size
AdcRegs.ADCTRL1.bit.SUSMOD = 0x0; // Emulation-suspend mode
//AdcRegs.ADCTRL2.all = 0x0900;
// bit 15 0: ePWM_SOCB_SEQ, 0=no action
// bit 14 0: RST_SEQ1, 0=no action
// bit 13 0: SOC_SEQ1, 0=clear any pending SOCs
// bit 12 0: reserved
// bit 11 1: INT_ENA_SEQ1, 1=enable interrupt
// bit 10 0: INT_MOD_SEQ1, 0=int on every SEQ1 conv
// bit 9 0: reserved
// bit 8 1: ePWM_SOCA_SEQ1, 1=SEQ1 start from ePWM_SOCA trigger
// bit 7 0: EXT_SOC_SEQ1, 1=SEQ1 start from ADCSOC pin
// bit 6 0: RST_SEQ2, 0=no action
// bit 5 0: SOC_SEQ2, no effect in cascaded mode
// bit 4 0: reserved
// bit 3 0: INT_ENA_SEQ2, 0=int disabled
// bit 2 0: INT_MOD_SEQ2, 0=int on every other SEQ2 conv
// bit 1 0: reserved
// bit 0 0: ePWM_SOCB_SEQ2, 0=no action
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ2 = 0x0; // ePWM SOCB enable bit for SEQ2
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ2 = 0x0; // SEQ2 interrupt mode
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2 = 0x0; // SEQ2 interrupt enable
AdcRegs.ADCTRL2.bit.SOC_SEQ2 = 0x0; // SOC SEQ2
AdcRegs.ADCTRL2.bit.RST_SEQ2 = 0x0; // Reset SEQ2
AdcRegs.ADCTRL2.bit.EXT_SOC_SEQ1 = 0x0; // external SOC SEQ1
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 0x0; // ePWM SOCB enable bit for SEQ1
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; // SEQ1 interrupt mode
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // SEQ1 interrupt enable
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x0; // SOC SEQ1
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1; // Reset SEQ1
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ = 0x0; // ePWM SOCB enable for cascaded sequencer
AdcRegs.ADCMAXCONV.all = 15;
// bit 15-7 0's: reserved
// bit 6-4 000: MAX_CONV2 value
// bit 3-0 0000: MAX_CONV1 value (0 means 1 conversion)
// Since we are only doing 1 conversion in the sequence, we only need to
// configure the ADCCHSELSEQ1 register, and only the CONV00 field. All
// other channel selection fields are don't cares in this example.
//AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0; // Convert Channel 0
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA3 as 1st SEQ conv.
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup ADCINA2 as 2nd SEQ conv.
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup ADCINA2 as 3nd SEQ conv.
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup ADCINA2 as 4nd SEQ conv.
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Setup ADCINA3 as 5st SEQ conv.
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Setup ADCINA2 as 6nd SEQ conv.
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Setup ADCINA2 as 7nd SEQ conv.
AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; // Setup ADCINA2 as 8nd SEQ conv.
AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8; // Setup ADCINA3 as 9st SEQ conv.
AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9; // Setup ADCINA2 as 10nd SEQ conv.
AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xA; // Setup ADCINA2 as 11nd SEQ conv.
AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xB; // Setup ADCINA2 as 12nd SEQ conv.
AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xC; // Setup ADCINA3 as 13st SEQ conv.
AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xD; // Setup ADCINA2 as 14nd SEQ conv.
AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0xE; // Setup ADCINA2 as 15nd SEQ conv.
AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0xF; // Setup ADCINA2 as 16nd SEQ conv.
//
//
//
m_mode = DSP28335::ADC::OPERATIONAL;
//
}//end if
//
}//end
//.TI.ramfunc
// #pragma CODE_SECTION("ramfuncs");
bool DSP28335::ADC::is_ready()
{
return m_status;
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::clear_status()
{
m_status = false;
//
}//end
// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::sw_soc_seq1()
{
if(m_mode == DSP28335::ADC::OPERATIONAL)
{
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;
//
}//if
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::sw_soc_seq2()
{
if(m_mode == DSP28335::ADC::OPERATIONAL)
{
AdcRegs.ADCTRL2.bit.SOC_SEQ2 = 1;
//
}//if
//
}//end
// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::interrupt_ack()
{
m_status = true;
//AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
//PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
// Reinitialize for next ADC sequence
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
//
}//end
//
} /* namespace DSP28335 */

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DSP28335/ADC.h
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/*
* ADC.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#ifndef DSP28335_ADC_H_
#define DSP28335_ADC_H_
namespace DSP28335
{
class ADC: public DSP28335::CPUBase
{
private:
bool m_status;
public:
ADC();
void setup();
public:
bool is_ready();
void clear_status();
public:
void sw_soc_seq1();
void sw_soc_seq2();
public:
void interrupt_ack();
//
};
} /* namespace DSP28335 */
#endif /* DSP28335_ADC_H_ */

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DSP28335/CPU.cpp
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/*
* CPUCore.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/CPU.h"
namespace DSP28335
{
//CONSTRUCTOR
CPU::CPU():
DSP28335::CPUBase(),
scib(ScibRegs),
// scic(ScicRegs),
// cpu_timers(CpuTimer0),
// epwm(),
// ecana(),
// ecanb(),
// eqep1(),
// period_measure(DSP28335::MeasureTimePeriod(CpuTimer2)),
interval_measure(DSP28335::MeasureTimeInterval(CpuTimer1)),
// xintf(),
// dout(),
// m_counter_startup(0),
// m_counter_sync(0),
_execute(&CPU::_execute_undef)
//
{}//end CONSTRUCTOR
void CPU::setup(DSP28335::CPUSetup& setup)
{
// adc.setup();
//
scib.setup(setup.scib);
//
// scic.setup(setup.scic);
InitCpuTimers();
// cpu_timers.setup(setup.timers);
// epwm.setup(setup.epwm);
// xintf.setup(setup.xintf);
// period_measure.set_magic((Uint32)0);
// period_measure.reset();
//
interval_measure.set_magic((Uint32)0);
interval_measure.reset();
//
// ecana.setup(setup.ecana);
// //
// ecanb.setup(setup.ecanb);
// eqep1.setup(setup.eqep1);
// dout.setup(setup.dout);
// m_counter_startup = setup.startup_period;
// m_counter_sync = setup.period_sync;
if(//adc.compare(DSP28335::ADC::OPERATIONAL) &&
//scib.compare(DSP28335::SCIB::OPERATIONAL) &&
//scic.compare(DSP28335::SCIC::OPERATIONAL) &&
// cpu_timers.compare(DSP28335::CPUTimers::OPERATIONAL) // &&
// epwm.compare(DSP28335::EPWM::OPERATIONAL) &&
// xintf.compare(DSP28335::XINTF::OPERATIONAL) &&
// ecana.compare(DSP28335::ECANA::OPERATIONAL) &&
// ecanb.compare(DSP28335::ECANB::OPERATIONAL) &&
// eqep1.compare(DSP28335::EQEP1::OPERATIONAL) &&
// dout.compare(DSP28335::DiscreteOutputs::OPERATIONAL)
true)
{
m_mode = DSP28335::CPUBase::OPERATIONAL;
//_execute = &CPUCore::_execute_mode_i;
//_execute = &CPUCore::_execute_mode_500HZ;
_execute = &CPU::_execute_undef;
// epwm.set_actions();
//
}//if
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void CPU::execute()
{
(this->*_execute)();
//
}//
//
void CPU::_execute_undef()
{}//
//
// #pragma CODE_SECTION("ramfuncs");
void CPU::_execute_mode_i()
{
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void CPU::_execute_mode_ii()
{
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void CPU::_execute_mode_iii()
{}//
//
//
} /* namespace DSP28335 */

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DSP28335/CPU.h
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/*
* SYSCore.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/ADC.h"
#include "DSP28335/CPUTimers.h"
#include "DSP28335/DiscreteOutputs.h"
#include "DSP28335/ECANA.h"
#include "DSP28335/ECANB.h"
#include "DSP28335/EPWM.h"
#include "DSP28335/EQEP1.h"
#include "DSP28335/GPIO.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/MeasureTimeInterval.h"
#include "DSP28335/MeasureTimePeriod.h"
#include "DSP28335/MemoryZone.h"
#include "DSP28335/MemoryZone0.h"
#include "DSP28335/MemoryZone7.h"
#include "DSP28335/SCIA.h"
#include "DSP28335/SCIB.h"
#include "DSP28335/SCIBase.h"
#include "DSP28335/SCIC.h"
#include "DSP28335/SPIBase.h"
#include "DSP28335/SPIA.h"
#include "DSP28335/XINTF.h"
#ifndef DSP28335_CPUCORE_H_
#define DSP28335_CPUCORE_H_
namespace DSP28335
{
struct CPUSetup
{
DSP28335::SCISetup scib;
DSP28335::SCISetup scic;
DSP28335::CPUTimersSetup timers;
DSP28335::EPWMSetup epwm;
DSP28335::XINTFSetup xintf;
DSP28335::ECANASetup ecana;
DSP28335::ECANBSetup ecanb;
DSP28335::EQEP1Setup eqep1;
DSP28335::DiscreteOutputsSetup dout;
Uint16 period_sync;
Uint16 startup_period;
CPUSetup():
scib(),
scic(),
timers(),
epwm(),
xintf(),
ecana(),
ecanb(),
eqep1(),
dout(),
period_sync(0),
startup_period(0)
{}
};//end SYSCoreSetup
struct CPUConfiguration
{
DSP28335::SCIConfiguration scib;
DSP28335::SCIConfiguration scic;
DSP28335::EPWMConfiguration epwm;
CPUConfiguration():
scib(),
scic(),
epwm()
{}
};//CPUConfiguration
class CPU: public DSP28335::CPUBase
{
public:
// DSP28335::GPIO gpio;
DSP28335::SCIB scib;
// DSP28335::SCIC scic;
// DSP28335::CPUTimers cpu_timers;
// DSP28335::EPWM epwm;
// DSP28335::MeasureTimePeriod period_measure;
DSP28335::MeasureTimeInterval interval_measure;
// DSP28335::XINTF xintf;
// DSP28335::ECANA ecana;
// DSP28335::ECANB ecanb;
// DSP28335::EQEP1 eqep1;
// DSP28335::DiscreteOutputs dout;
private:
// Uint16 m_counter_startup;
// Uint16 m_counter_sync;
public:
CPU();
public:
void setup(DSP28335::CPUSetup& setup);
void get_hard_code_setup(DSP28335::CPUSetup& hsetup);
public:
void execute();
private:
void (CPU::*_execute)();
void _execute_undef();
void _execute_mode_i();
void _execute_mode_ii();
void _execute_mode_iii();
//
};// CPU
} /* namespace DSP28335 */
#endif /* DSP28335_CPUCORE_H_ */

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DSP28335/CPUCoreHardCodeSetup.cpp
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/*
* SYSCoreHardCodeSetup.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/CPU.h"
namespace DSP28335
{
void DSP28335::CPU::get_hard_code_setup(DSP28335::CPUSetup& hsetup)
{
// At startup number synchronization pwm's periods
hsetup.startup_period = 20;
// synchronization every pwm's cycle
hsetup.period_sync = 5;
//
// SCIB - interface with monitor? RS485, MODBUS RTU
//
hsetup.scib.config.baudrate = SCIB_BAUDRATE_DEFAULT;
hsetup.scib.config.parity = SCIB_PARITY_DEFAULT;
hsetup.scib.config.stopbits = SCIB_STOPBITS_DEFAULT;
hsetup.scib.config.lenght = SCIB_LENGHT_DEFAULT;
hsetup.scib.gpio_setup = SCIB_GPIO_SETUP_DEFAULT;
//
// SCIC - internal interface
//
hsetup.scic.config.baudrate = SCIC_BAUDRATE_DEFAULT;
hsetup.scic.config.parity = SCIC_PARITY_DEFAULT;
hsetup.scic.config.stopbits = SCIC_STOPBITS_DEFAULT;
hsetup.scic.config.lenght = SCIC_LENGHT_DEFAULT;
hsetup.scic.gpio_setup = SCIC_GPIO_SETUP_DEFAULT;
//
// CPU Timers
//
hsetup.timers.frequency = 150.0; //150MHz
hsetup.timers.period = 1000.0; //1000us
//
// EPWM
//
hsetup.epwm.parameters.fpwm = 500; //Hz
hsetup.epwm.parameters.pulse_sync = 1.0e-6; //s
hsetup.epwm.parameters.pulse_adc_soc = 32.0e-6; //s
hsetup.epwm.parameters.adc_soc_offset = FP_ZERO; //relative
hsetup.epwm.parameters.adc_soc_quantity = 2;
hsetup.epwm.gpio_setup = &DSP28335::GPIO::gpio_epwm_setup;
//
// XINTF
//
hsetup.xintf.gpio_setup = &DSP28335::GPIO::gpio_xintf_16bit_setup;
//
// ECANA
//
hsetup.ecana.gpio_setup = &DSP28335::GPIO::gpio_cana_setup;
//
// ECANB
//
hsetup.ecanb.gpio_setup = &DSP28335::GPIO::gpio_canb_setup;
//
// EQEP
//
hsetup.eqep1.gpio_setup = &DSP28335::GPIO::gpio_eqep_setup;
//
// Discrete Outputs
//
hsetup.dout.gpio_setup = &DSP28335::GPIO::gpio_dicrete_outputs_setup;
//
}//end
} /* namespace DSP28335 */

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DSP28335/DiscreteOutputs.cpp
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/*
* DiscreteOutputs.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/DiscreteOutputs.h"
namespace DSP28335
{
//CONSTRUCTOR
DiscreteOutputs::DiscreteOutputs():
DSP28335::CPUBase(),
_gpio_setup(&DSP28335::GPIO::gpio_dicrete_outputs_setup)
{}//CONSTRUCTOR
void DiscreteOutputs::setup(const DiscreteOutputsSetup& setup)
{
if(m_mode == DSP28335::DiscreteOutputs::UNDEFINED)
{
if(setup.gpio_setup != 0)
{
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
m_mode = DSP28335::DiscreteOutputs::OPERATIONAL;
//
}//if
//
}//if
//
//
}//
} /* namespace DSP28335 */

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DSP28335/DiscreteOutputs.h
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/*
* DiscreteOutputs.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/GPIO.h"
#ifndef DSP28335_DISCRETEOUTPUTS_H_
#define DSP28335_DISCRETEOUTPUTS_H_
namespace DSP28335
{
struct DiscreteOutputsSetup: public DSP28335::CPUBaseSetup
{
DiscreteOutputsSetup():
DSP28335::CPUBaseSetup()
{}
};//
class DiscreteOutputs: public DSP28335::CPUBase
{
public:
DiscreteOutputs();
void setup(const DiscreteOutputsSetup& setup);
private:
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_DISCRETEOUTPUTS_H_ */

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DSP28335/ECANA.cpp
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/*
* ECANA.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/ECANA.h"
namespace DSP28335
{
//CONSTRUCTOR
ECANA::ECANA():
CPUBase(),
_gpio_setup(&DSP28335::GPIO::gpio_cana_setup)
{}//CONSTRUCTOR
void ECANA::setup(const ECANASetup& setup)
{
if(m_mode == DSP28335::ECANA::UNDEFINED)
{
InitECana();
if(setup.gpio_setup != 0)
{
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
m_mode = DSP28335::ECANA::OPERATIONAL;
//
}//if
//
}//if
//
}//
} /* namespace DSP28335 */

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DSP28335/ECANA.h
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/*
* ECANA.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/GPIO.h"
#ifndef DSP28335_ECANA_H_
#define DSP28335_ECANA_H_
namespace DSP28335
{
struct ECANASetup: public DSP28335::CPUBaseSetup
{
ECANASetup():
DSP28335::CPUBaseSetup()
{}
};//ECANASetup
class ECANA: public DSP28335::CPUBase
{
public:
ECANA();
void setup(const ECANASetup& setup);
private:
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_ECANA_H_ */

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DSP28335/ECANB.cpp
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/*
* ECANB.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/ECANB.h"
namespace DSP28335
{
//CONSTRUCTOR
ECANB::ECANB():
CPUBase(),
_gpio_setup(&DSP28335::GPIO::gpio_canb_setup)
{}//CONSTRUCTOR
void ECANB::setup(const ECANBSetup& setup)
{
if(m_mode == DSP28335::ECANB::UNDEFINED)
{
InitECanb();
if(setup.gpio_setup != 0)
{
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
m_mode = DSP28335::ECANB::OPERATIONAL;
//
}//if
//
}//if
//
}//
} /* namespace DSP28335 */

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DSP28335/ECANB.h
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/*
* ECANB.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/GPIO.h"
#ifndef CPU_ECANB_H_
#define CPU_ECANB_H_
namespace DSP28335
{
struct ECANBSetup: public DSP28335::CPUBaseSetup
{
ECANBSetup():
DSP28335::CPUBaseSetup()
{}
};//ECANBSetup
class ECANB: public CPUBase
{
public:
ECANB();
void setup(const ECANBSetup& setup);
private:
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* CPU_ECANB_H_ */

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DSP28335/EPWM.cpp
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/*
* EPWM.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/EPWM.h"
namespace DSP28335
{
//CONSTRUCTOR
EPWMConfigModificator::EPWMConfigModificator():
m_config(),
modify(true)
{}//CONSTRUCTOR
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_config(EPWMConfiguration& refconfig)
{
if(m_config.fpwm != refconfig.fpwm)
{
m_config.fpwm = refconfig.fpwm;
modify = true;
}//
if(m_config.pulse_sync != refconfig.pulse_sync)
{
m_config.pulse_sync = refconfig.pulse_sync;
modify = true;
}//
if(m_config.pulse_adc_soc != refconfig.pulse_adc_soc)
{
m_config.pulse_adc_soc = refconfig.pulse_adc_soc;
modify = true;
}//
//
if(m_config.adc_soc_offset != refconfig.adc_soc_offset)
{
m_config.adc_soc_offset = refconfig.adc_soc_offset;
modify = true;
}//
//
if(m_config.adc_soc_quantity != refconfig.adc_soc_quantity)
{
m_config.adc_soc_quantity = refconfig.adc_soc_quantity;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
EPWMConfiguration EPWMConfigModificator::get_config()
{
return m_config;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::reset()
{
modify = false;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_pwm_frquency(float fpwm)
{
if(m_config.fpwm != fpwm)
{
m_config.fpwm = fpwm;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_pulse_sync(float pulse_sync)
{
if(m_config.pulse_sync != pulse_sync)
{
m_config.pulse_sync = pulse_sync;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_pulse_adc_soc(float pulse_adc_soc)
{
if(m_config.pulse_adc_soc != pulse_adc_soc)
{
m_config.pulse_adc_soc = pulse_adc_soc;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_adc_soc_offset(float adc_soc_offset)
{
if(m_config.adc_soc_offset != adc_soc_offset)
{
m_config.adc_soc_offset = adc_soc_offset;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_adc_soc_quantity(Uint16 adc_soc_quantity)
{
if(m_config.adc_soc_quantity != adc_soc_quantity)
{
m_config.adc_soc_quantity = adc_soc_quantity;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_pwm_frquency()
{
return m_config.fpwm;
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_pulse_sync()
{
return m_config.pulse_sync;
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_pulse_adc_soc()
{
return m_config.pulse_adc_soc;
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_adc_soc_offset()
{
return m_config.adc_soc_offset;
}//
//
// #pragma CODE_SECTION("ramfuncs");
Uint16 EPWMConfigModificator::get_adc_soc_quantity()
{
return m_config.adc_soc_quantity;
}//
//
//CONSTRUCTOR
EPWM::EPWM():
DSP28335::CPUBase(),
m_configuration_current(),
m_configuration_new(),
m_fcpu(150.0e6),
m_timer_period(FP_ZERO),
m_timer_step(FP_ZERO),
m_time_sample_adc(FP_ZERO),
m_clock_prescale_list(),
m_high_speed_clock_prescale(),
m_tbprd(FP_ZERO),
m_clkdiv(0),
m_hspclkdiv(0),
m_cmpr_sync(0),
m_cmpr_adc_offset(0),
m_cmpr_adc_start(0),
m_cmpr_adc_stop(0),
m_cmpr_adc_width(0),
m_cmpr_adc_step(0),
m_adc_soc_quantity(0),
m_adc_soc_counter(0),
_epwm2_adc_drive(0),
status(),
_gpio_setup(0)
//
{
m_clock_prescale_list[0] = 1.0;
m_clock_prescale_list[1] = 2.0;
m_clock_prescale_list[2] = 4.0;
m_clock_prescale_list[3] = 8.0;
m_clock_prescale_list[4] = 16.0;
m_clock_prescale_list[5] = 32.0;
m_clock_prescale_list[6] = 64.0;
m_clock_prescale_list[7] = 128.0;
//
m_high_speed_clock_prescale[0] = 1.0;
m_high_speed_clock_prescale[1] = 2.0;
m_high_speed_clock_prescale[2] = 4.0;
m_high_speed_clock_prescale[3] = 6.0;
m_high_speed_clock_prescale[4] = 8.0;
m_high_speed_clock_prescale[5] = 10.0;
m_high_speed_clock_prescale[6] = 12.0;
m_high_speed_clock_prescale[7] = 14.0;
//
}//end CONSTRUCTOR
void EPWM::setup(const EPWMSetup& setup)
{
m_status = true;
//m_status &= m_mode == DSP28335::EPWM::UNDEFINED ? true : false;
m_status &= setup.parameters.fpwm > (float)(5.0) ? true : false;
m_status &= setup.parameters.pulse_sync != FP_ZERO ? true : false;
m_status &= setup.parameters.pulse_adc_soc != FP_ZERO ? true : false;
m_status &= setup.parameters.adc_soc_offset >= FP_ZERO ? true : false;
m_status &= setup.parameters.adc_soc_quantity >= 1 ? true : false;
m_status &= setup.gpio_setup != 0 ? true : false;
//
if(m_status)
{
m_configuration_current = setup.parameters;
m_tbprd = 0;
m_clkdiv = 0;
m_hspclkdiv = 0;
m_cmpr_sync = 0;
//
m_cmpr_adc_start = 0;
m_cmpr_adc_stop = 0;
m_cmpr_adc_width = 0;
m_cmpr_adc_step = 0;
//
m_adc_soc_quantity = setup.parameters.adc_soc_quantity;
m_adc_soc_counter = 0;
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/setup.parameters.fpwm;
//
while(m_timer_period>(float)(32767.0))
{
m_clkdiv++;
if(m_clkdiv >= 8)
{
m_clkdiv = 0;
m_hspclkdiv++;
//
}//if
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/setup.parameters.fpwm;
//
}//while
//
m_timer_step = (m_clock_prescale_list[m_clkdiv] * m_high_speed_clock_prescale[m_hspclkdiv])/m_fcpu;
m_tbprd = (Uint16)m_timer_period;
m_cmpr_sync = m_tbprd - (Uint16)(setup.parameters.pulse_sync/m_timer_step);
m_cmpr_adc_width = (Uint16)((float)(setup.parameters.pulse_adc_soc/m_timer_step));
m_cmpr_adc_step = (Uint16)((float)((float)m_timer_period/((float)setup.parameters.adc_soc_quantity)));
m_cmpr_adc_offset = (Uint16)((float)(m_timer_period * setup.parameters.adc_soc_offset));
m_time_sample_adc = m_timer_step * ((float)m_cmpr_adc_step);
status.all = 0;
//
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
// Setup TBCLK
EPwm1Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //
EPwm1Regs.TBCTL.bit.PHSEN = 0x0; //
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm1Regs.TBCTL.bit.CLKDIV = m_clkdiv;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm1Regs.AQCTLB.all = 0;
EPwm1Regs.AQSFRC.bit.ACTSFA = 0;
EPwm1Regs.AQSFRC.bit.ACTSFB = 0;
EPwm1Regs.AQSFRC.bit.OTSFA = 0;
EPwm1Regs.AQSFRC.bit.OTSFB = 0;
EPwm1Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm1Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm1Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm1Regs.DBCTL.bit.POLSEL = 0; // Active High complementary
EPwm1Regs.DBCTL.bit.IN_MODE = 0; //
EPwm1Regs.DBFED = 0;
EPwm1Regs.DBRED = 0;
// Set Compare values
EPwm1Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm1Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
//EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA; // Select INT on equal to CMPA
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
//EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // SOCA equal to zero: 1-zero; 2-period
//EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Disable INT EPWMxSOCA
//EPwm1Regs.ETSEL.bit.SOCBSEL = 2 // SOCB equal to period
//EPwm1Regs.ETSEL.bit.SOCBEN = 0; // Disable INT EPWMxSOCB
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; //
EPwm1Regs.ETPS.bit.INTCNT = 0;
// PWM-Chopper
EPwm1Regs.PCCTL.all = 0; // PWM-Chopper Control Register
// Trip-Zone Submodule
EPwm1Regs.TZSEL.all = 0; // Trip-Zone Select Register
EPwm1Regs.TZCTL.all = 0; // Trip-Zone Control Register
EPwm1Regs.TZEINT.all = 0; // Trip-Zone Enable Interrupt Register
//EPwm1Regs.TZFLG.all = 0; // Trip-Zone Flag Register
//EPwm1Regs.TZCLR.all = 0; // Trip-Zone Clear Register
//EPwm1Regs.TZFRC.all = 0; // Trip-Zone Force Register
// Setup TBCLK
EPwm2Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //
EPwm2Regs.TBCTL.bit.PHSEN = 0x0; //
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm2Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm2Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm2Regs.AQCTLB.all = 0;
EPwm2Regs.AQSFRC.bit.ACTSFA = 0;
EPwm2Regs.AQSFRC.bit.ACTSFB = 0;
EPwm2Regs.AQSFRC.bit.OTSFA = 0;
EPwm2Regs.AQSFRC.bit.OTSFB = 0;
EPwm2Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm2Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm2Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm2Regs.DBCTL.bit.POLSEL = 0; // Active High complementary
EPwm2Regs.DBCTL.bit.IN_MODE = 0; //
EPwm2Regs.DBFED = 0;
EPwm2Regs.DBRED = 0;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_offset; // Set compare A value
EPwm2Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA; //
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
//EPwm2Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // SOCA equal to zero: 1-zero; 2-period
//EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Disable INT EPWMxSOCA
//EPwm2Regs.ETSEL.bit.SOCBSEL = 2 // SOCB equal to period
//EPwm2Regs.ETSEL.bit.SOCBEN = 0; // Disable INT EPWMxSOCB
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; //
EPwm2Regs.ETPS.bit.INTCNT = 0;
// Setup TBCLK
EPwm5Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm5Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;// Count up/down
EPwm5Regs.TBCTL.bit.PHSEN = 0x0; // Disable phase loading
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm5Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm5Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm5Regs.CMPCTL.bit.LOADAMODE = 0; // Load on Zero
EPwm5Regs.CMPCTL.bit.LOADBMODE = 0;
// Set actions
EPwm5Regs.AQCTLA.all = 0;
EPwm5Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm5Regs.AQCTLB.bit.PRD = AQ_CLEAR;
EPwm5Regs.AQSFRC.bit.ACTSFA = 0;
EPwm5Regs.AQSFRC.bit.ACTSFB = 0;
EPwm5Regs.AQSFRC.bit.OTSFA = 0;
EPwm5Regs.AQSFRC.bit.OTSFB = 0;
EPwm5Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm5Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm5Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm5Regs.DBCTL.bit.POLSEL = 0; // Active Hi complementary
EPwm5Regs.DBCTL.bit.IN_MODE = 0; //
EPwm5Regs.DBFED = 0;
EPwm5Regs.DBRED = 0;
// Set Compare values
EPwm5Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm5Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
EPwm5Regs.ETSEL.all = 0;
EPwm5Regs.ETPS.all = 0;
// PWM-Chopper
EPwm5Regs.PCCTL.all = 0; // PWM-Chopper Control Register
// Trip-Zone Submodule
EPwm5Regs.TZSEL.all = 0; // Trip-Zone Select Register
EPwm5Regs.TZCTL.all = 0; // Trip-Zone Control Register
EPwm5Regs.TZEINT.all = 0; // Trip-Zone Enable Interrupt Register
// Setup TBCLK
EPwm6Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm6Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;// Count up/down
EPwm6Regs.TBCTL.bit.PHSEN = 0x0; // Disable phase loading
EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm6Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm6Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm6Regs.CMPCTL.bit.LOADAMODE = 0; // Load on Zero
EPwm6Regs.CMPCTL.bit.LOADBMODE = 0;
// Set actions
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count
EPwm6Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm6Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm6Regs.AQCTLB.bit.PRD = AQ_CLEAR;
EPwm6Regs.AQSFRC.bit.ACTSFA = 0;
EPwm6Regs.AQSFRC.bit.ACTSFB = 0;
EPwm6Regs.AQSFRC.bit.OTSFA = 0;
EPwm6Regs.AQSFRC.bit.OTSFB = 0;
EPwm6Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm6Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm6Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm6Regs.DBCTL.bit.POLSEL = 0; // Active Hi complementary
EPwm6Regs.DBCTL.bit.IN_MODE = 0; //
EPwm6Regs.DBFED = 0;
EPwm6Regs.DBRED = 0;
// Set Compare values
EPwm6Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm6Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
EPwm6Regs.ETSEL.all = 0;
//EPwm6Regs.ETPS.bit.INTPRD = 0; //
EPwm6Regs.ETPS.all = 0;
// PWM-Chopper
EPwm6Regs.PCCTL.all = 0; // PWM-Chopper Control Register
// Trip-Zone Submodule
EPwm6Regs.TZSEL.all = 0; // Trip-Zone Select Register
EPwm6Regs.TZCTL.all = 0; // Trip-Zone Control Register
EPwm6Regs.TZEINT.all = 0; // Trip-Zone Enable Interrupt Register
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_start;
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
m_mode = DSP28335::EPWM::OPERATIONAL;
//
}
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::configure(const EPWMConfiguration& config)
{
m_status = true;
m_status &= config.fpwm > (float)(5.0) ? true : false;
m_status &= config.pulse_sync != FP_ZERO ? true : false;
m_status &= config.pulse_adc_soc != FP_ZERO ? true : false;
m_status &= config.adc_soc_offset >= FP_ZERO ? true : false;
m_status &= config.adc_soc_quantity >= 1 ? true : false;
//
if(m_status)
{
m_configuration_current = config;
m_tbprd = 0;
m_clkdiv = 0;
m_hspclkdiv = 0;
m_cmpr_sync = 0;
//
m_cmpr_adc_start = 0;
m_cmpr_adc_stop = 0;
m_cmpr_adc_width = 0;
m_cmpr_adc_step = 0;
//
m_adc_soc_quantity = config.adc_soc_quantity;
m_adc_soc_counter = 0;
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/config.fpwm;
//
while(m_timer_period>(float)(32767.0))
{
m_clkdiv++;
if(m_clkdiv >= 8)
{
m_clkdiv = 0;
m_hspclkdiv++;
//
}//if
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/config.fpwm;
//
}//while
//
m_timer_step = (m_clock_prescale_list[m_clkdiv] * m_high_speed_clock_prescale[m_hspclkdiv])/m_fcpu;
m_tbprd = (Uint16)m_timer_period;
m_cmpr_sync = m_tbprd - (Uint16)(config.pulse_sync/m_timer_step);
m_cmpr_adc_width = (Uint16)((float)(config.pulse_adc_soc/m_timer_step));
//m_cmpr_adc_step = (Uint16)(m_tbprd/config.adc_soc_quantity);
m_cmpr_adc_step = (Uint16)((float)((float)m_timer_period/((float)config.adc_soc_quantity)));
m_cmpr_adc_offset = (Uint16)((float)(m_timer_period * config.adc_soc_offset));
m_time_sample_adc = m_timer_step * ((float)m_cmpr_adc_step);
status.all = 0x0001;
//
//
EPwm1Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm1Regs.TBCTL.bit.CLKDIV = m_clkdiv;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
EPwm1Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm2Regs.TBPRD = m_tbprd;
EPwm2Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
// EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_offset; // Set compare A value
EPwm5Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm5Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
EPwm5Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
// Setup TBCLK
EPwm6Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm6Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
EPwm6Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
//
}
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::set_actions()
{
// Set EPWM1 actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;
//EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on event A, up count
//EPwm1Regs.AQCTLA.bit.PRD = AQ_SET;
//
// Set EPWM5 actions
EPwm5Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm5Regs.AQCTLB.bit.PRD = AQ_CLEAR;
//EPwm5Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2B on event B, up count
//EPwm5Regs.AQCTLB.bit.PRD = AQ_SET;
//
// Set EPWM6 actions
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count
EPwm6Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm6Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm6Regs.AQCTLB.bit.PRD = AQ_CLEAR;
//EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on event A, up count
//EPwm6Regs.AQCTLA.bit.PRD = AQ_SET;
//EPwm6Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2B on event B, up count
//EPwm6Regs.AQCTLB.bit.PRD = AQ_SET;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::clear_actions()
{
// Clear actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
EPwm1Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
//
// Set EPWM5 actions
EPwm5Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
EPwm5Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
//
// Set EPWM6 actions
EPwm6Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
EPwm6Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
EPwm6Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
EPwm6Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWM::get_time_sample_adc()
{
return m_time_sample_adc;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm1_adc_drive()
{
m_adc_soc_counter = 0;
m_cmpr_adc_start = m_cmpr_adc_offset;
m_cmpr_adc_stop = m_cmpr_adc_offset + m_cmpr_adc_width;
//
//new_cycle = 1;
//adc_soc = 0;
//adc_ready = 0;
status.all = 0x001;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_start; // Set compare A value
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_start;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm2_adc_drive()
{
(this->*_epwm2_adc_drive)();
//
}//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::_epwm2_adc_drive_mode_start()
{
//new_cycle = 0;
//adc_soc = 1;
//adc_ready = 0;
status.all = 0x002;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_stop; // Set compare A value
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_stop;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::_epwm2_adc_drive_mode_stop()
{
m_adc_soc_counter++;
m_cmpr_adc_start += m_cmpr_adc_step;
m_cmpr_adc_stop += m_cmpr_adc_step;
//new_cycle = 0;
//adc_soc = 0;
//adc_ready = 1;
status.all = 0x004;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_start; // Set compare A value
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_start;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm1_interrupt_ack()
{
EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm2_interrupt_ack()
{
EPwm2Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//
}//
//
} /* namespace DSP28335 */

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DSP28335/EPWM.h
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/*
* EPWM.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#ifndef DSP28335_EPWM_H_
#define DSP28335_EPWM_H_
namespace DSP28335
{
enum CLOCKPRESCALE {DIV01, DIV02, DIV04, DIV08, DIV16, DIV32, DIV64, DIV128};
enum HIGHSPEEDCLOCKPRESCALE {HSDIV01, HSDIV02, HSDIV04, HSDIV06, HSDIV08, HSDIV10, HSDIV12, HSDIV14};
struct EPWMStatusBitField
{
Uint16 new_cycle:1;
Uint16 adc_soc:1;
Uint16 adc_ready:1;
};//EPWMStatusBitField
union EPWMStatusRegister
{
Uint16 all;
EPWMStatusBitField bit;
EPWMStatusRegister():
all(0)
{}
};//EPWMStatusRegister
struct EPWMConfiguration
{
float fpwm;
float pulse_sync;
float pulse_adc_soc;
float adc_soc_offset;
Uint16 adc_soc_quantity;
EPWMConfiguration():
fpwm(500.0),
pulse_sync(1.0e-6),
pulse_adc_soc(10.0e-6),
adc_soc_offset(FP_ZERO),
adc_soc_quantity(1)
{}
};//EPWMConfiguration
class EPWMConfigModificator
{
private:
EPWMConfiguration m_config;
public:
bool modify;
public:
EPWMConfigModificator();
void set_config(EPWMConfiguration& refconfig);
EPWMConfiguration get_config();
public:
void reset();
public:
void set_pwm_frquency(float fpwm);
void set_pulse_sync(float pulse_sync);
void set_pulse_adc_soc(float pulse_adc_soc);
void set_adc_soc_offset(float adc_soc_offset);
void set_adc_soc_quantity(Uint16 adc_soc_quantity);
public:
float get_pwm_frquency();
float get_pulse_sync();
float get_pulse_adc_soc();
float get_adc_soc_offset();
Uint16 get_adc_soc_quantity();
//
};//EPWMConfigModificator
struct EPWMSetup: public DSP28335::CPUBaseSetup
{
EPWMConfiguration parameters;
EPWMSetup():
DSP28335::CPUBaseSetup(),
parameters()
{}
};//EPWMSetup
class EPWM: public DSP28335::CPUBase
{
private:
EPWMConfiguration m_configuration_current;
EPWMConfiguration m_configuration_new;
private:
float m_fcpu;
float m_timer_period;
float m_timer_step;
float m_time_sample_adc;
float m_clock_prescale_list[8];
float m_high_speed_clock_prescale[8];
Uint16 m_tbprd; //TBPRD
Uint16 m_clkdiv;
Uint16 m_hspclkdiv;
Uint16 m_cmpr_sync;
Uint16 m_cmpr_adc_offset;
Uint16 m_cmpr_adc_start;
Uint16 m_cmpr_adc_stop;
Uint16 m_cmpr_adc_width;
Uint16 m_cmpr_adc_step;
Uint16 m_adc_soc_quantity;
Uint16 m_adc_soc_counter;
public:
EPWMStatusRegister status;
public:
EPWM();
void setup(const EPWMSetup& setup);
void configure(const EPWMConfiguration& config);
public:
void set_actions();
void clear_actions();
public:
float get_time_sample_adc();
public:
void epwm1_adc_drive();
public:
void epwm2_adc_drive();
private:
void (EPWM::*_epwm2_adc_drive)();
void _epwm2_adc_drive_mode_start();
void _epwm2_adc_drive_mode_stop();
public:
void epwm1_interrupt_ack();
void epwm2_interrupt_ack();
private:
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_EPWM_H_ */

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DSP28335/EQEP1.cpp
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/*
* EQEP1.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/EQEP1.h"
namespace DSP28335
{
//CONSTRUCTOR
EQEP1::EQEP1():
DSP28335::CPUBase(),
_gpio_setup(&DSP28335::GPIO::gpio_eqep_setup)
//
{}//CONSTRUCTOR
void EQEP1::setup(const EQEP1Setup& setup)
{
m_status = m_mode == DSP28335::EQEP1::UNDEFINED ? true : false;
m_status &= setup.gpio_setup != 0 ? true : false;
if(m_status)
{
//
EQep1Regs.QDECCTL.bit.QSRC = 00;
EQep1Regs.QDECCTL.bit.XCR = 0;
EQep1Regs.QEPCTL.bit.FREE_SOFT = 2;
EQep1Regs.QPOSMAX = 0xffffffff;
EQep1Regs.QEPCTL.bit.QPEN = 1;
EQep1Regs.QPOSCNT = 0x00000000;
//
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
//
m_mode = DSP28335::EQEP1::OPERATIONAL;
//
}//if
//
//
}//
//
} /* namespace DSP28335 */

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DSP28335/EQEP1.h
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/*
* EQEP1.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/GPIO.h"
#ifndef DSP28335_EQEP1_H_
#define DSP28335_EQEP1_H_
namespace DSP28335
{
struct EQEP1Setup: public DSP28335::CPUBaseSetup
{
EQEP1Setup():
DSP28335::CPUBaseSetup()
{}
};//
class EQEP1: public DSP28335::CPUBase
{
public:
EQEP1();
void setup(const EQEP1Setup& setup);
private:
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_EQEP1_H_ */

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DSP28335/FLASH.cpp
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/*
* Flash.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/FLASH.h"
namespace DSP28335
{
//CONSTRUCTOR
FLASH::FLASH():
DSP28335::CPUBase(),
m_mask_sector(0),
//
m_operation_status_erase(0),
m_operation_status_program(0),
m_operation_status_verify(0),
//
m_version_hex_default(API_VERSION_DEFAULT),
m_version_hex(0)
{
m_sector.StartAddr = 0;
m_sector.EndAddr = 0;
//
m_status_erase.FirstFailAddr = 0;
m_status_erase.ExpectedData = 0;
m_status_erase.ActualData = 0;
//
m_status_program.FirstFailAddr = 0;
m_status_program.ExpectedData = 0;
m_status_program.ActualData = 0;
//
m_status_verify.FirstFailAddr = 0;
m_status_verify.ExpectedData = 0;
m_status_verify.ActualData = 0;
//
}//end CONSTRUCTOR
void FLASH::setup(Uint16 mask_sector, Uint16 *StartAddr, Uint16 *EndAddr)
{
m_mask_sector = mask_sector;
m_sector.StartAddr = StartAddr;
m_sector.EndAddr = EndAddr;
//SCALE_FACTOR is defined in Flash2833x_API_Config.h
//EALLOW;
Flash_CPUScaleFactor = SCALE_FACTOR;
//EDIS;
//
m_mode = DSP28335::FLASH::OPERATIONAL;
//
}//end
Uint16 FLASH::erase()
{
//Uint16 status = 0;
//Flash_Erase(Uint16 SectorMask, FLASH_ST *FEraseStat);
//status = Flash_Erase(m_mask_sector, &m_status_erase);
//return status;
return Flash_Erase(m_mask_sector, &m_status_erase);
//
}//end
Uint16 FLASH::read(Uint16 *Dest, Uint32 Length)
{
Uint16 *Source = m_sector.StartAddr;
Uint16 status = 0;
if(Length <= 0x4000)
{
for(Uint32 i=0; i<Length; i++)
{
(*Dest++) = (*Source++);
//
}//end for
status = 1;
//
}//end if
//
return status;
//
}//end
Uint16 FLASH::program(Uint16 *BufAddr, Uint32 Length)
{
Uint16 status = STATUS_SUCCESS;
m_status_erase.FirstFailAddr = 0;
m_status_erase.ExpectedData = 0;
m_status_erase.ActualData = 0;
m_status_program.FirstFailAddr = 0;
m_status_program.ExpectedData = 0;
m_status_program.ActualData = 0;
m_status_verify.FirstFailAddr = 0;
m_status_verify.ExpectedData = 0;
m_status_verify.ActualData = 0;
status = Flash_Erase(m_mask_sector, &m_status_erase);
if(status != STATUS_SUCCESS) return status;
//Flash_Program(Uint16 *FlashAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FProgStatus);
status = Flash_Program(m_sector.StartAddr, BufAddr, Length, &m_status_program);
if(status != STATUS_SUCCESS) return status;
//Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FVerifyStat);
status = Flash_Verify(m_sector.StartAddr, BufAddr, Length, &m_status_verify);
return status;
//
}//end
Uint16 FLASH::verify(Uint16 *BufAddr, Uint32 Length)
{
Uint16 status = STATUS_SUCCESS;
m_status_verify.FirstFailAddr = 0;
m_status_verify.ExpectedData = 0;
m_status_verify.ActualData = 0;
//Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FVerifyStat);
status = Flash_Verify(m_sector.StartAddr, BufAddr, Length, &m_status_verify);
return status;
//
}//end
Uint16 FLASH::APIVersionHex()
{
Uint16 version = 0;
version = Flash_APIVersionHex();
return version;
//
}//end
} /* namespace DSP28335 */

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DSP28335/FLASH.h
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/*
* Flash.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "F28335/Flash2833x_API_Config.h"
#include "F28335/Flash2833x_API_Library.h"
#include "DSP28335/CPUBase.h"
#ifndef DSP28335_FLASH_H_
#define DSP28335_FLASH_H_
#define API_VERSION_DEFAULT 0x0100
namespace DSP28335
{
typedef struct
{
Uint16 *StartAddr;
Uint16 *EndAddr;
}SECTOR;
class FLASH: public DSP28335::CPUBase
{
private:
Uint16 m_mask_sector;
SECTOR m_sector;
//
FLASH_ST m_status_erase;
FLASH_ST m_status_program;
FLASH_ST m_status_verify;
Uint16 m_operation_status_erase;
Uint16 m_operation_status_program;
Uint16 m_operation_status_verify;
//
Uint16 m_version_hex_default;
Uint16 m_version_hex;
//
public:
FLASH();
void setup(Uint16 mask_sector, Uint16 *StartAddr, Uint16 *EndAddr);
Uint16 erase();
Uint16 read(Uint16 *Dest, Uint32 Length);
Uint16 program(Uint16 *BufAddr, Uint32 Length);
Uint16 verify(Uint16 *BufAddr, Uint32 Length);
Uint16 APIVersionHex();
//
};//end class FLASH
} /* namespace DSP28335 */
#endif /* DSP28335_FLASH_H_ */

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DSP28335/MeasureTimePeriod.cpp
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/*
* MeasureTimePeriod.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/MeasureTimePeriod.h"
namespace DSP28335
{
//Constructor
MeasureTimePeriod::MeasureTimePeriod(CPUTIMER_VARS& CPUTimer):
m_CPUTimer(CPUTimer),
m_timer_result((Uint32)0),
m_timer_result_previous((Uint32)0),
m_magic_number((Uint32)0),
_execute(&DSP28335::MeasureTimePeriod::_execute_start)
//
{}//end Constructor
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::execute(void)
{
(this->*_execute)();
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::reset(void)
{
m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer
m_CPUTimer.RegsAddr->PRD.all = 0xFFFFFFFF;
m_CPUTimer.RegsAddr->TCR.bit.TRB = 1; // Reload CPU Timer
//
_execute = &DSP28335::MeasureTimePeriod::_execute_start;
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::inc_counter()
{
m_CPUTimer.InterruptCount++;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::reset_counter()
{
m_CPUTimer.InterruptCount = (Uint32)0;
//
}//
//
void MeasureTimePeriod::set_magic(const Uint32 magic)
{
m_magic_number = (Uint32)magic;
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::_execute_start(void)
{
_execute = &DSP28335::MeasureTimePeriod::_execute_scan;
//
m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer
m_CPUTimer.RegsAddr->TCR.bit.TRB = 1; // Reload CPU Timer
m_CPUTimer.RegsAddr->TCR.bit.TSS = 0; // Start CPU Timer
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::_execute_scan(void)
{
m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer
//
m_timer_result_previous = m_timer_result;
m_timer_result = m_CPUTimer.RegsAddr->PRD.all - m_CPUTimer.RegsAddr->TIM.all - m_magic_number;
//
m_CPUTimer.RegsAddr->TCR.bit.TRB = 1; // Reload CPU Timer
m_CPUTimer.RegsAddr->TCR.bit.TSS = 0; // Start CPU Timer
//
}//end
//
} /* namespace DSP28335 */

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DSP28335/MeasureTimePeriod.h
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/*
* MeasureTimePeriod.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#ifndef DSP28335_MEASURETIMEPERIOD_H_
#define DSP28335_MEASURETIMEPERIOD_H_
namespace DSP28335
{
class MeasureTimePeriod
{
private:
CPUTIMER_VARS& m_CPUTimer;
Uint32 m_timer_result;
Uint32 m_timer_result_previous;
Uint32 m_magic_number;
public:
MeasureTimePeriod(CPUTIMER_VARS& pCPUTimer);
void execute(void);
void reset(void);
void inc_counter();
void reset_counter();
void set_magic(const Uint32 magic);
private:
void (MeasureTimePeriod::*_execute)(void);
void _execute_start(void);
void _execute_scan(void);
//
};//end class MeasureTimePeriod
} /* namespace DSP28335 */
#endif /* DSP28335_MEASURETIMEPERIOD_H_ */

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DSP28335/MemoryZone.h
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/*
* MemoryZone.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include <stdint.h>
#ifndef SYSCTRL_MEMORYZONE_H_
#define SYSCTRL_MEMORYZONE_H_
struct ZONE_REGISTER_16_BIT_FIELD
{
uint16_t b0: 1;
uint16_t b1: 1;
uint16_t b2: 1;
uint16_t b3: 1;
uint16_t b4: 1;
uint16_t b5: 1;
uint16_t b6: 1;
uint16_t b7: 1;
uint16_t b8: 1;
uint16_t b9: 1;
uint16_t bA: 1;
uint16_t bB: 1;
uint16_t bC: 1;
uint16_t bD: 1;
uint16_t bE: 1;
uint16_t bF: 1;
};//ZONE_REGISTER_16_BIT_FIELD
struct ZONE_REGISTER_16_BYTE_FIELD
{
uint16_t bt0 :8;
uint16_t bt1 :8;
};//ZONE_REGISTER_16_BYTE_FIELD
union ZONE_REGISTER_16
{
uint16_t u16;
int16_t i16;
ZONE_REGISTER_16_BIT_FIELD bit;
ZONE_REGISTER_16_BYTE_FIELD byte;
};//REGISTER_16
#endif /* SYSCTRL_MEMORYZONE_H_ */

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DSP28335/MemoryZone0.h
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/*
* MemoryZone0.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/MemoryZone.h"
#include <stdint.h>
#ifndef SYSCTRL_MEMORYZONE0_H_
#define SYSCTRL_MEMORYZONE0_H_
struct ZONE0_Bank_H
{
ZONE_REGISTER_16 h0;
ZONE_REGISTER_16 h1;
ZONE_REGISTER_16 h2;
ZONE_REGISTER_16 h3;
ZONE_REGISTER_16 h4;
ZONE_REGISTER_16 h5;
ZONE_REGISTER_16 h6;
ZONE_REGISTER_16 h7;
ZONE_REGISTER_16 h8;
ZONE_REGISTER_16 h9;
ZONE_REGISTER_16 hA;
ZONE_REGISTER_16 hB;
ZONE_REGISTER_16 hC;
ZONE_REGISTER_16 hD;
ZONE_REGISTER_16 hE;
ZONE_REGISTER_16 hF;
};//
struct ZONE0_Bank_HH
{
ZONE0_Bank_H hh0;
ZONE0_Bank_H hh1;
ZONE0_Bank_H hh2;
ZONE0_Bank_H hh3;
ZONE0_Bank_H hh4;
ZONE0_Bank_H hh5;
ZONE0_Bank_H hh6;
ZONE0_Bank_H hh7;
ZONE0_Bank_H hh8;
ZONE0_Bank_H hh9;
ZONE0_Bank_H hhA;
ZONE0_Bank_H hhB;
ZONE0_Bank_H hhC;
ZONE0_Bank_H hhD;
ZONE0_Bank_H hhE;
ZONE0_Bank_H hhF;
};//
struct ZONE0_Bank_HHH
{
ZONE0_Bank_HH hhh0;
ZONE0_Bank_HH hhh1;
ZONE0_Bank_HH hhh2;
ZONE0_Bank_HH hhh3;
ZONE0_Bank_HH hhh4;
ZONE0_Bank_HH hhh5;
ZONE0_Bank_HH hhh6;
ZONE0_Bank_HH hhh7;
ZONE0_Bank_HH hhh8;
ZONE0_Bank_HH hhh9;
ZONE0_Bank_HH hhhA;
ZONE0_Bank_HH hhhB;
ZONE0_Bank_HH hhhC;
ZONE0_Bank_HH hhhD;
ZONE0_Bank_HH hhhE;
ZONE0_Bank_HH hhhF;
};//
struct DATA_ZONE0_STRUCTURE
{
int16_t &cmpr_a;
int16_t &cmpr_b;
int16_t &cmpr_c;
DATA_ZONE0_STRUCTURE(int16_t &cmpa, int16_t &cmpb, int16_t &cmpc):
cmpr_a(cmpa),
cmpr_b(cmpb),
cmpr_c(cmpc)
{}
};//
struct ADC_ACCESS_STRUCTURE
{
int16_t *read_channel_a0;
int16_t *read_channel_a1;
int16_t *read_channel_b0;
int16_t *read_channel_b1;
int16_t *read_channel_c0;
int16_t *read_channel_c1;
};//
#endif /* SYSCTRL_MEMORYZONE0_H_ */

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DSP28335/MemoryZone7.h
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/*
* MemoryZone7.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/MemoryZone.h"
#include <stdint.h>
#ifndef SYSCTRL_MEMORYZONE7_H_
#define SYSCTRL_MEMORYZONE7_H_
struct ZONE7_Bank_H
{
ZONE_REGISTER_16 h0;
ZONE_REGISTER_16 h1;
ZONE_REGISTER_16 h2;
ZONE_REGISTER_16 h3;
ZONE_REGISTER_16 h4;
ZONE_REGISTER_16 h5;
ZONE_REGISTER_16 h6;
ZONE_REGISTER_16 h7;
ZONE_REGISTER_16 h8;
ZONE_REGISTER_16 h9;
ZONE_REGISTER_16 hA;
ZONE_REGISTER_16 hB;
ZONE_REGISTER_16 hC;
ZONE_REGISTER_16 hD;
ZONE_REGISTER_16 hE;
ZONE_REGISTER_16 hF;
};//
struct ZONE7_Bank_HH
{
ZONE7_Bank_H hh0;
ZONE7_Bank_H hh1;
ZONE7_Bank_H hh2;
ZONE7_Bank_H hh3;
ZONE7_Bank_H hh4;
ZONE7_Bank_H hh5;
ZONE7_Bank_H hh6;
ZONE7_Bank_H hh7;
ZONE7_Bank_H hh8;
ZONE7_Bank_H hh9;
ZONE7_Bank_H hhA;
ZONE7_Bank_H hhB;
ZONE7_Bank_H hhC;
ZONE7_Bank_H hhD;
ZONE7_Bank_H hhE;
ZONE7_Bank_H hhF;
};//
struct ZONE7_Bank_HHH
{
ZONE7_Bank_HH hhh0;
ZONE7_Bank_HH hhh1;
ZONE7_Bank_HH hhh2;
ZONE7_Bank_HH hhh3;
};//
#endif /* SYSCTRL_MEMORYZONE7_H_ */

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DSP28335/SPIA.cpp
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/*
* SPIA.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/SPIA.h"
namespace DSP28335
{
//CONSTRUCTOR
SPIA::SPIA():
SPIBase(),
m_fifo_tx_status(0),
m_data_tx_len(0),
m_data_tx_counter(0),
m_fifo_tx(),
m_fifo_rx(),
_gpio_setup(SPIA_GPIO_SETUP_DEFAULT)
{}//CONSTRUCTOR
void SPIA::setup()
{
SpiaRegs.SPICCR.bit.SPISWRESET = 0; // Software Reset SPI
SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // Master
// FRAM MODE 0 - CLKPOLARITY = 0, CLK_PHASE = 0
//SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // Normal Clock Phase
//SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; // Shift Clock Polarity
// FRAM MODE 3 - CLKPOLARITY = 1, CLK_PHASE = 0
SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // Normal Clock Phase
SpiaRegs.SPICCR.bit.CLKPOLARITY = 1; // Shift Clock Polarity
SpiaRegs.SPICCR.bit.SPILBK = 0; // Loopback
SpiaRegs.SPIBRR = 36; // Baud Rate = LSPCLK/(36+1) = 37.5MHz/(36+1) = 1MHz
SpiaRegs.SPICCR.bit.SPICHAR = 7; // 8-bit word
SpiaRegs.SPISTS.all = 0; // Clear OVERRUN_FLAG, INT_FLAG, BUFFULL_FLAG
// FIFO SPI
SpiaRegs.SPIFFTX.bit.SPIRST = 0; // Software reset FIFO SPI
SpiaRegs.SPIFFTX.bit.SPIFFENA = 1; // Enable SPI FIFO
SpiaRegs.SPIFFTX.bit.TXFIFO = 1; // Release TX FIFO from Reset
SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1; // TXFIFO Interrupt Clear
SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 1; // Receive FIFO Overflow Clear
SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1; // Receive FIFO Interrupt Clear
SpiaRegs.SPIFFTX.bit.TXFFIENA = 1; // TX FIFO Interrupt Enable
//SpiaRegs.SPIFFRX.bit.RXFFIENA = 1; // RX FIFO Interrupt Enable
SpiaRegs.SPIFFTX.bit.SPIRST = 1; // Release SPI FIFO
SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1; // Re-enable receive FIFO operation
SpiaRegs.SPICCR.bit.SPISWRESET = 1; // Release SPI
(*_gpio_setup)();
//
}//
//
void SPIA::setup(DSP28335::SPISetup& setup)
{
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
//
}//
//
void SPIA::get_default_configuration(DSP28335::SPIConfiguration& config)
{
//
}//
//
void SPIA::get_configuration(DSP28335::SPIConfiguration& config)
{
//
}//
//
void SPIA::set_configuration(DSP28335::SPIConfiguration& config)
{
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void SPIA::clear_tx_interrupt()
{
// Interrupt acknowledge SPITXINTA
SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void SPIA::write(Uint16 data, Uint16 addr)
{
m_fifo_tx[0] = FRAM_OPCODE_WREN;
m_fifo_tx[1] = FRAM_OPCODE_WRITE;
m_fifo_tx[2] = addr & 0xff00;
m_fifo_tx[3] = (addr & 0x00ff) << 8;
m_fifo_tx[4] = data & 0xff00;
m_fifo_tx[5] = (data & 0x00ff) << 8;
m_fifo_tx[6] = 0;
m_fifo_tx[7] = 0;
m_fifo_tx[8] = 0;
m_fifo_tx[9] = 0;
m_fifo_tx[10] = 0;
m_fifo_tx[11] = 0;
m_fifo_tx[12] = 0;
m_fifo_tx[13] = 0;
m_fifo_tx[14] = 0;
m_fifo_tx[15] = 0;
//
m_data_tx_len = 6;
SpiaRegs.SPIFFTX.bit.TXFIFO = 0;
for(m_data_tx_counter = 0; m_data_tx_counter < m_data_tx_len; m_data_tx_counter++)
{
SpiaRegs.SPITXBUF = m_fifo_tx[m_data_tx_counter];
//
}//for
SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void SPIA::erase(Uint16 addr)
{
m_fifo_tx[0] = FRAM_OPCODE_WREN;
m_fifo_tx[1] = FRAM_OPCODE_WRITE;
m_fifo_tx[2] = addr & 0xff00;
m_fifo_tx[3] = (addr & 0x00ff) << 8;
m_fifo_tx[4] = FRAM_OPCODE_ERASE;
m_fifo_tx[5] = FRAM_OPCODE_ERASE;
m_fifo_tx[6] = 0;
m_fifo_tx[7] = 0;
m_fifo_tx[8] = 0;
m_fifo_tx[9] = 0;
m_fifo_tx[10] = 0;
m_fifo_tx[11] = 0;
m_fifo_tx[12] = 0;
m_fifo_tx[13] = 0;
m_fifo_tx[14] = 0;
m_fifo_tx[15] = 0;
//
m_data_tx_len = 6;
SpiaRegs.SPIFFTX.bit.TXFIFO = 0;
for(m_data_tx_counter = 0; m_data_tx_counter < m_data_tx_len; m_data_tx_counter++)
{
SpiaRegs.SPITXBUF = m_fifo_tx[m_data_tx_counter];
//
}//for
SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void SPIA::read(Uint16 addr)
{
m_fifo_tx[0] = FRAM_OPCODE_READ;
m_fifo_tx[1] = addr & 0xff00;
m_fifo_tx[2] = (addr & 0x00ff) << 8;
m_fifo_tx[3] = FRAM_OPCODE_DUMMY;
m_fifo_tx[4] = FRAM_OPCODE_DUMMY;
m_fifo_tx[5] = 0;
m_fifo_tx[6] = 0;
m_fifo_tx[7] = 0;
m_fifo_tx[8] = 0;
m_fifo_tx[9] = 0;
m_fifo_tx[10] = 0;
m_fifo_tx[11] = 0;
m_fifo_tx[12] = 0;
m_fifo_tx[13] = 0;
m_fifo_tx[14] = 0;
m_fifo_tx[15] = 0;
m_data_tx_len = 5;
SpiaRegs.SPIFFTX.bit.TXFIFO = 0;
for(m_data_tx_counter = 0; m_data_tx_counter < m_data_tx_len; m_data_tx_counter++)
{
SpiaRegs.SPITXBUF = m_fifo_tx[m_data_tx_counter];
m_fifo_tx[m_data_tx_counter] = 0;
//
}//for
SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
Uint16 SPIA::get_read_data()
{
m_fifo_rx[0] = SpiaRegs.SPIRXBUF;
m_fifo_rx[1] = SpiaRegs.SPIRXBUF;
m_fifo_rx[2] = SpiaRegs.SPIRXBUF;
m_fifo_rx[3] = SpiaRegs.SPIRXBUF;
m_fifo_rx[4] = SpiaRegs.SPIRXBUF;
m_fifo_rx[5] = 0;
m_fifo_rx[6] = 0;
m_fifo_rx[7] = 0;
m_fifo_rx[8] = 0;
m_fifo_rx[9] = 0;
m_fifo_rx[10] = 0;
m_fifo_rx[11] = 0;
m_fifo_rx[12] = 0;
m_fifo_rx[13] = 0;
m_fifo_rx[14] = 0;
m_fifo_rx[15] = 0;
//
return (Uint16)((m_fifo_rx[3] << 8) | (m_fifo_rx[4] & 0x00ff));
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
Uint16 SPIA::get_fifo_tx_status()
{
return m_fifo_tx_status = (Uint16)SpiaRegs.SPIFFTX.bit.TXFFST;
//
}//
//
void SPIA::_configure(DSP28335::SPIConfiguration& config)
{
//
}//
//
} /* namespace DSP28335 */

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/*
* SPIA.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/SPIBase.h"
#ifndef DSP28335_SPIA_H_
#define DSP28335_SPIA_H_
#ifndef SPIA_GPIO_SETUP_DEFAULT_DEFINES
#define SPIA_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_spia_setup)
#define SPIA_GPIO_SETUP_DEFAULT_DEFINES
#endif
#ifndef FRAM_OPCODE_WREN_DEFINES
#define FRAM_OPCODE_WREN (uint16_t)0x0600
#define FRAM_OPCODE_WREN_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRDI_DEFINES
#define FRAM_OPCODE_WRDI (uint16_t)0x0400
#define FRAM_OPCODE_WRDI_DEFINES
#endif
//
#ifndef FRAM_OPCODE_RDSR_DEFINES
#define FRAM_OPCODE_RDSR (uint16_t)0x0500
#define FRAM_OPCODE_RDSR_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRSR_DEFINES
#define FRAM_OPCODE_WRSR (uint16_t)0x0100
#define FRAM_OPCODE_WRSR_DEFINES
#endif
//
#ifndef FRAM_OPCODE_READ_DEFINES
#define FRAM_OPCODE_READ (uint16_t)0x0300
#define FRAM_OPCODE_READ_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRITE_DEFINES
#define FRAM_OPCODE_WRITE (uint16_t)0x0200
#define FRAM_OPCODE_WRITE_DEFINES
#endif
//
#ifndef FRAM_OPCODE_DUMMY_DEFINES
#define FRAM_OPCODE_DUMMY (uint16_t)0x5500
#define FRAM_OPCODE_DUMMY_DEFINES
#endif
//
#ifndef FRAM_OPCODE_ERASE_DEFINES
#define FRAM_OPCODE_ERASE (uint16_t)0xFF00
#define FRAM_OPCODE_ERASE_DEFINES
#endif
//
namespace DSP28335
{
class SPIA: public SPIBase
{
public:
enum mode_t {UNDEFINED=0, CONFIGURATE=1, OPERATIONAL=2};
private:
Uint16 m_fifo_tx_status;
Uint16 m_data_tx_len;
Uint16 m_data_tx_counter;
private:
Uint16 m_fifo_tx[16];
Uint16 m_fifo_rx[16];
public:
SPIA();
public:
void clear_tx_interrupt();
public:
void setup();
void setup(DSP28335::SPISetup& setup);
void get_default_configuration(DSP28335::SPIConfiguration& config);
void get_configuration(DSP28335::SPIConfiguration& config);
void set_configuration(DSP28335::SPIConfiguration& config);
public:
void write(Uint16 data, Uint16 addr);
void erase(Uint16 addr);
void read(Uint16 addr);
Uint16 get_read_data();
Uint16 get_fifo_tx_status();
private:
void _configure(DSP28335::SPIConfiguration& config);
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_SPIA_H_ */

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DSP28335/SPIBase.cpp
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/*
* SPIBase.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/SPIBase.h"
namespace DSP28335
{
//CONSTRUCTOR
SPIBase::SPIBase()
{}//CONSTRUCTOR
} /* namespace DSP28335 */

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DSP28335/SPIBase.h
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/*
* SPIBase.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/GPIO.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef DSP28335_SPIBASE_H_
#define DSP28335_SPIBASE_H_
namespace DSP28335
{
struct SPIConfiguration
{
SPIConfiguration(){}
};//
struct SPISetup
{
pGPIO_FUNCTION gpio_setup;
SPISetup():
gpio_setup(&DSP28335::GPIO::gpio_spia_setup)
{}
};//SPISetup
class SPIBase
{
public:
SPIBase();
public:
virtual void setup() = 0;
virtual void setup(DSP28335::SPISetup& setup) = 0;
virtual void get_default_configuration(DSP28335::SPIConfiguration& config) = 0;
virtual void get_configuration(DSP28335::SPIConfiguration& config) = 0;
virtual void set_configuration(DSP28335::SPIConfiguration& config) = 0;
protected:
virtual void _configure(DSP28335::SPIConfiguration& config) = 0;
};
} /* namespace DSP28335 */
#endif /* DSP28335_SPIBASE_H_ */

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DSP28335/XINTF.cpp
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/*
* XINTF.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/XINTF.h"
namespace DSP28335
{
//CONSTRUCTOR
XINTF::XINTF():
CPUBase(),
_gpio_setup(&DSP28335::GPIO::gpio_xintf_16bit_setup)
{}//CONSTRUCTOR
void XINTF::setup(DSP28335::XINTFSetup& setup)
{
if(m_mode == DSP28335::XINTF::UNDEFINED)
{
//
// This shows how to write to the XINTF registers. The
// values used here are the default state after reset.
// Different hardware will require a different configuration.
//
//
// Any changes to XINTF timing should only be made by code
// running outside of the XINTF.
//
//
// All Zones
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
//
//struct XINTCNF2_BITS { // bits description
// Uint16 WRBUFF:2; // 1:0 Write buffer depth
// Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
// Uint16 CLKOFF:1; // 3 Disable XCLKOUT
// Uint16 rsvd1:2; // 5:4 reserved
// Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
// Uint16 rsvd2:1; // 8 reserved
// Uint16 HOLD:1; // 9 Hold enable/disable
// Uint16 HOLDS:1; // 10 Current state of HOLDn input
// Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
// Uint16 rsvd3:4; // 15:12 reserved
// Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
// Uint16 rsvd4:13; // 31:19 reserved
//};
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
//
// No write buffering
//
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
//
// XCLKOUT is enabled
//
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
//
// XCLKOUT = XTIMCLK/2
//
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
//
// WLEVEL
//
XintfRegs.XINTCNF2.bit.WLEVEL = 0;
//
// HOLD
//
XintfRegs.XINTCNF2.bit.HOLD = 0;
//
// HOLDS
//
XintfRegs.XINTCNF2.bit.HOLDS = 1;
//
// HOLDAS
//
XintfRegs.XINTCNF2.bit.HOLDAS = 1;
//
// Zone 0
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
//
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
XintfRegs.XTIMING0.bit.XWRACTIVE = 5; // default 7;
XintfRegs.XTIMING0.bit.XWRTRAIL = 1; // default 3;
//
// Zone read timing
//
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE = 5; // default 7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 1; // default 3;
//
// double all Zone read/write lead/active/trail timing
//
XintfRegs.XTIMING0.bit.X2TIMING = 1;
//
// Zone will sample XREADY signal
//
XintfRegs.XTIMING0.bit.USEREADY = 1;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
//
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
//
XintfRegs.XTIMING0.bit.XSIZE = 3;
//
// Zone 6
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
//
XintfRegs.XTIMING6.bit.XWRLEAD = 3;
XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
//
// Zone read timing
//
XintfRegs.XTIMING6.bit.XRDLEAD = 3;
XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
//
// double all Zone read/write lead/active/trail timing
//
XintfRegs.XTIMING6.bit.X2TIMING = 1;
//
// Zone will sample XREADY signal
//
XintfRegs.XTIMING6.bit.USEREADY = 1;
XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
//
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
//
XintfRegs.XTIMING6.bit.XSIZE = 3;
//
// Zone 7
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
//
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
//
// Zone read timing
//
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
//
// double all Zone read/write lead/active/trail timing
//
XintfRegs.XTIMING7.bit.X2TIMING = 1;
//
// Zone will sample XREADY signal
//
XintfRegs.XTIMING7.bit.USEREADY = 1;
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
//
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
//
XintfRegs.XTIMING7.bit.XSIZE = 3;
//
// Bank switching
// Assume Zone 7 is slow, so add additional BCYC cycles
// when ever switching from Zone 7 to another Zone.
// This will help avoid bus contention.
//
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;
EDIS;
//
// Force a pipeline flush to ensure that the write to the last register
// configured occurs before returning.
//
asm(" RPT #7 || NOP");
if(setup.gpio_setup != 0)
{
_gpio_setup = setup.gpio_setup;
//
(*_gpio_setup)();
//
m_mode = DSP28335::XINTF::OPERATIONAL;
m_status = true;
//
}//if
//
}//if
//
}//
//
} /* namespace DSP28335 */

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DSP28335/XINTF.h
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/*
* XINTF.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/GPIO.h"
#include "DSP28335/CPUBase.h"
#ifndef DSP28335_XINTF_H_
#define DSP28335_XINTF_H_
namespace DSP28335
{
struct XINTFSetup
{
pGPIO_FUNCTION gpio_setup;
XINTFSetup():
gpio_setup(&DSP28335::GPIO::gpio_xintf_16bit_setup)
{}
};//
class XINTF: public CPUBase
{
public:
XINTF();
void setup(DSP28335::XINTFSetup& setup);
private:
void (*_gpio_setup)();
};//
} /* namespace DSP28335 */
#endif /* DSP28335_XINTF_H_ */

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PERIPHERY/AnalogFault.cpp
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/*
* AnalogFault.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/AnalogFault.h"
namespace PERIPHERY
{
//CONSTRUCTOR
AnalogFault::AnalogFault():
m_fault(0),
_gpio_analog_fault_setup(&DSP28335::GPIO::gpio_analog_fault_setup),
_analog_fault_read(&DSP28335::GPIO::gpio_analog_fault_read)
{}//CONSTRUCTOR
void AnalogFault::setup(const AnaloFaultSetup& setup)
{
_gpio_analog_fault_setup = setup.p_gpio_analog_fault_setup;
_analog_fault_read = setup.p_analog_fault_read;
//
}//
//
void AnalogFault::get_hard_code_setup(AnaloFaultSetup& hsetup)
{
hsetup.set_default();
//
}//
//
void AnalogFault::get_fault(uint16_t& analog_fault)
{
(*_analog_fault_read)(m_fault);
analog_fault = m_fault;
//
}//
//
} /* namespace PERIPHERY */

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PERIPHERY/AnalogFault.h
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/*
* AnalogFault.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include "DSP28335/GPIO.h"
#include "PERIPHERY/PeripheryMap.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef PERIPHERY_ANALOGFAULT_H_
#define PERIPHERY_ANALOGFAULT_H_
namespace PERIPHERY
{
struct AnaloFaultSetup
{
pGPIO_FUNCTION p_gpio_analog_fault_setup;
pGPIO_FUNCTION_UINT p_analog_fault_read;
void set_default()
{
p_gpio_analog_fault_setup = &DSP28335::GPIO::gpio_analog_fault_setup;
p_analog_fault_read = &DSP28335::GPIO::gpio_analog_fault_read;
};
AnaloFaultSetup():
p_gpio_analog_fault_setup(&DSP28335::GPIO::gpio_analog_fault_setup),
p_analog_fault_read(&DSP28335::GPIO::gpio_analog_fault_read)
{}
};//AnaloFaultSetup
class AnalogFault
{
private:
uint16_t m_fault;
public:
AnalogFault();
public:
void setup(const AnaloFaultSetup& setup);
void get_hard_code_setup(AnaloFaultSetup& hsetup);
public:
void get_fault(uint16_t& analog_fault);
private:
void (*_gpio_analog_fault_setup)();
void (*_analog_fault_read)(uint16_t& data);
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_ANALOGFAULT_H_ */

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PERIPHERY/DigitalIO.cpp
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/*
* DigitalIO.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/DigitalIO.h"
namespace PERIPHERY
{
//CONSRUCTOR
DigitalIO::DigitalIO():
m_pointer(0)
{}//CONSRUCTOR
//#pragma CODE_SECTION("ramfuncs");
void DigitalIO::setup(uint16_t *memzone)
{
m_pointer = memzone + OFFSET_DATA_DISCRETE_IO;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void DigitalIO::readDigitalIO(uint16_t& data)
{
NOP;
NOP;
NOP;
data = *m_pointer;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void DigitalIO::writeDigitalIO(uint16_t data)
{
NOP;
NOP;
NOP;
*m_pointer = data;
NOP;
NOP;
NOP;
//
}//
//
} /* namespace PERIPHERY */

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PERIPHERY/DigitalIO.h
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/*
* DigitalIO.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include "PERIPHERY/PeripheryMap.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef PERIPHERY_DIGITALIO_H_
#define PERIPHERY_DIGITALIO_H_
namespace PERIPHERY
{
struct DigitalIODataBitField
{
uint16_t b00: 1;
uint16_t b01: 1;
uint16_t b02: 1;
uint16_t b03: 1;
uint16_t b04: 1;
uint16_t b05: 1;
uint16_t b06: 1;
uint16_t b07: 1;
uint16_t b08: 1;
uint16_t b09: 1;
uint16_t b10: 1;
uint16_t b11: 1;
uint16_t b12: 1;
uint16_t b13: 1;
uint16_t b14: 1;
uint16_t b15: 1;
};//
union DigitalIODataRegister
{
uint16_t all;
DigitalIODataBitField bit;
DigitalIODataRegister():
all(0)
{}
};//
struct DigitalIOData
{
DigitalIODataRegister input;
DigitalIODataRegister output;
DigitalIOData():
input(),
output()
{}
};//
class DigitalIO
{
private:
uint16_t *m_pointer;
public:
DigitalIO();
void setup(uint16_t *memzone);
public:
void readDigitalIO(uint16_t& data);
void writeDigitalIO(uint16_t data);
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_DIGITALIO_H_ */

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PERIPHERY/ExtADC.cpp
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/*
* ExtADC.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/ExtADC.h"
namespace PERIPHERY
{
//CONSTRUCTOR
ExtADC::ExtADC():
p_channel_00(0),
p_channel_01(0),
p_channel_02(0),
p_channel_03(0),
p_channel_04(0),
p_channel_05(0),
p_channel_06(0),
p_channel_07(0),
p_channel_08(0),
p_channel_09(0),
p_channel_10(0),
p_channel_11(0),
p_channel_12(0),
p_channel_13(0),
p_channel_14(0),
p_channel_15(0),
p_channel_16(0),
p_channel_17(0),
_gpio_setup(&DSP28335::GPIO::ext_adc_start_convertion_setup),
_start_convertion(&DSP28335::GPIO::set_ext_adc_start_convertion),
_stop_convertion(&DSP28335::GPIO::clear_ext_adc_start_convertion)
//
{}//CONSTRUCTOR
void ExtADC::setup(uint16_t *memzone)
{
p_channel_00 = memzone + OFFSET_ADC_0_CHANNEL_0;
p_channel_01 = memzone + OFFSET_ADC_0_CHANNEL_1;
p_channel_02 = memzone + OFFSET_ADC_0_CHANNEL_2;
p_channel_03 = memzone + OFFSET_ADC_0_CHANNEL_3;
p_channel_04 = memzone + OFFSET_ADC_0_CHANNEL_4;
p_channel_05 = memzone + OFFSET_ADC_0_CHANNEL_5;
p_channel_06 = memzone + OFFSET_ADC_1_CHANNEL_0;
p_channel_07 = memzone + OFFSET_ADC_1_CHANNEL_1;;
p_channel_08 = memzone + OFFSET_ADC_1_CHANNEL_2;
p_channel_09 = memzone + OFFSET_ADC_1_CHANNEL_3;
p_channel_10 = memzone + OFFSET_ADC_1_CHANNEL_4;
p_channel_11 = memzone + OFFSET_ADC_1_CHANNEL_5;
p_channel_12 = memzone + OFFSET_ADC_2_CHANNEL_0;
p_channel_13 = memzone + OFFSET_ADC_2_CHANNEL_1;
p_channel_14 = memzone + OFFSET_ADC_2_CHANNEL_2;
p_channel_15 = memzone + OFFSET_ADC_2_CHANNEL_3;
p_channel_16 = memzone + OFFSET_ADC_2_CHANNEL_4;
p_channel_17 = memzone + OFFSET_ADC_2_CHANNEL_5;
(*_gpio_setup)();
//
}//
//
void ExtADC::setup(uint16_t *memzone, const ExtADCSetup& setup)
{
p_channel_00 = memzone + OFFSET_ADC_0_CHANNEL_0;
p_channel_01 = memzone + OFFSET_ADC_0_CHANNEL_1;
p_channel_02 = memzone + OFFSET_ADC_0_CHANNEL_2;
p_channel_03 = memzone + OFFSET_ADC_0_CHANNEL_3;
p_channel_04 = memzone + OFFSET_ADC_0_CHANNEL_4;
p_channel_05 = memzone + OFFSET_ADC_0_CHANNEL_5;
p_channel_06 = memzone + OFFSET_ADC_1_CHANNEL_0;
p_channel_07 = memzone + OFFSET_ADC_1_CHANNEL_1;;
p_channel_08 = memzone + OFFSET_ADC_1_CHANNEL_2;
p_channel_09 = memzone + OFFSET_ADC_1_CHANNEL_3;
p_channel_10 = memzone + OFFSET_ADC_1_CHANNEL_4;
p_channel_11 = memzone + OFFSET_ADC_1_CHANNEL_5;
p_channel_12 = memzone + OFFSET_ADC_2_CHANNEL_0;
p_channel_13 = memzone + OFFSET_ADC_2_CHANNEL_1;
p_channel_14 = memzone + OFFSET_ADC_2_CHANNEL_2;
p_channel_15 = memzone + OFFSET_ADC_2_CHANNEL_3;
p_channel_16 = memzone + OFFSET_ADC_2_CHANNEL_4;
p_channel_17 = memzone + OFFSET_ADC_2_CHANNEL_5;
_gpio_setup = setup.p_gpio_setup;
_start_convertion = setup.p_start_convertion;
_stop_convertion = setup.p_stop_convertion;
(*_gpio_setup)();
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void ExtADC::read_adc(ADC_RESULT& adc_result)
{
NOP;
NOP;
adc_result.channel_00 = *p_channel_00;
adc_result.channel_01 = *p_channel_01;
adc_result.channel_02 = *p_channel_02;
adc_result.channel_03 = *p_channel_03;
adc_result.channel_04 = *p_channel_04;
adc_result.channel_05 = *p_channel_05;
adc_result.channel_06 = *p_channel_06;
adc_result.channel_07 = *p_channel_07;
adc_result.channel_08 = *p_channel_08;
adc_result.channel_09 = *p_channel_09;
adc_result.channel_10 = *p_channel_10;
adc_result.channel_11 = *p_channel_11;
adc_result.channel_12 = *p_channel_12;
adc_result.channel_13 = *p_channel_13;
adc_result.channel_14 = *p_channel_14;
adc_result.channel_15 = *p_channel_15;
adc_result.channel_16 = *p_channel_16;
adc_result.channel_17 = *p_channel_17;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void ExtADC::read_adc(uint16_t adc_result[18])
{
NOP;
NOP;
adc_result[0] = *p_channel_00;
adc_result[1] = *p_channel_01;
adc_result[2] = *p_channel_02;
adc_result[3] = *p_channel_03;
adc_result[4] = *p_channel_04;
adc_result[5] = *p_channel_05;
adc_result[6] = *p_channel_06;
adc_result[7] = *p_channel_07;
adc_result[8] = *p_channel_08;
adc_result[9] = *p_channel_09;
adc_result[10] = *p_channel_10;
adc_result[11] = *p_channel_11;
adc_result[12] = *p_channel_12;
adc_result[13] = *p_channel_13;
adc_result[14] = *p_channel_14;
adc_result[15] = *p_channel_15;
adc_result[16] = *p_channel_16;
adc_result[17] = *p_channel_17;
NOP;
NOP;
NOP;
}//
//
#pragma CODE_SECTION("ramfuncs");
void ExtADC::start_convertion()
{
(*_start_convertion)();
//
}//
//
#pragma CODE_SECTION("ramfuncs");
void ExtADC::stop_convertion()
{
(*_stop_convertion)();
//
}//
//
} /* namespace PERIPHERY */

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/*
* ExtADC.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/GPIO.h"
#include "PERIPHERY/PeripheryMap.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef PERIPHERY_EXTADC_H_
#define PERIPHERY_EXTADC_H_
namespace PERIPHERY
{
struct ExtADCSetup
{
pGPIO_FUNCTION p_gpio_setup;
pGPIO_FUNCTION p_start_convertion;
pGPIO_FUNCTION p_stop_convertion;
void set_default()
{
p_gpio_setup = &DSP28335::GPIO::ext_adc_start_convertion_setup;
p_start_convertion = &DSP28335::GPIO::set_ext_adc_start_convertion;
p_stop_convertion = &DSP28335::GPIO::clear_ext_adc_start_convertion;
};
ExtADCSetup():
p_gpio_setup(&DSP28335::GPIO::ext_adc_start_convertion_setup),
p_start_convertion(&DSP28335::GPIO::set_ext_adc_start_convertion),
p_stop_convertion(&DSP28335::GPIO::clear_ext_adc_start_convertion)
{}
//
};//
struct ExtADCStatusBitField
{
uint16_t busy: 1;
uint16_t read: 1;
uint16_t ready: 1;
};//ExtADCStatus
union ExtADCStatusRegister
{
uint16_t all;
ExtADCStatusBitField bit;
ExtADCStatusRegister():
all(0)
{}
};//
union ADC_RESULT_TYPE
{
uint16_t u16;
int16_t i16;
ADC_RESULT_TYPE():
u16(0)
{}
};//ADC_RESULT_TYPE
struct ADC_RESULT
{
int16_t channel_00;
int16_t channel_01;
int16_t channel_02;
int16_t channel_03;
int16_t channel_04;
int16_t channel_05;
int16_t channel_06;
int16_t channel_07;
int16_t channel_08;
int16_t channel_09;
int16_t channel_10;
int16_t channel_11;
int16_t channel_12;
int16_t channel_13;
int16_t channel_14;
int16_t channel_15;
int16_t channel_16;
int16_t channel_17;
ADC_RESULT():
channel_00(0),
channel_01(0),
channel_02(0),
channel_03(0),
channel_04(0),
channel_05(0),
channel_06(0),
channel_07(0),
channel_08(0),
channel_09(0),
channel_10(0),
channel_11(0),
channel_12(0),
channel_13(0),
channel_14(0),
channel_15(0),
channel_16(0),
channel_17(0)
{}
};//
class ExtADC
{
private:
uint16_t *p_channel_00;
uint16_t *p_channel_01;
uint16_t *p_channel_02;
uint16_t *p_channel_03;
uint16_t *p_channel_04;
uint16_t *p_channel_05;
uint16_t *p_channel_06;
uint16_t *p_channel_07;
uint16_t *p_channel_08;
uint16_t *p_channel_09;
uint16_t *p_channel_10;
uint16_t *p_channel_11;
uint16_t *p_channel_12;
uint16_t *p_channel_13;
uint16_t *p_channel_14;
uint16_t *p_channel_15;
uint16_t *p_channel_16;
uint16_t *p_channel_17;
public:
ExtADC();
void setup(uint16_t *memzone);
void setup(uint16_t *memzone, const ExtADCSetup& setup);
public:
void read_adc(ADC_RESULT& adc_result);
void read_adc(uint16_t adc_result[18]);
void start_convertion();
void stop_convertion();
private:
void (*_gpio_setup)();
void (*_start_convertion)();
void (*_stop_convertion)();
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_EXTADC_H_ */

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/*
* ExtDAC.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/ExtDAC.h"
namespace PERIPHERY
{
//CONSTRUCTOR
ExtDAC::ExtDAC():
p_channel_a(0),
p_channel_b(0),
p_channel_c(0),
p_channel_d(0)
{}//CONSTRUCTOR
//
//
void ExtDAC::setup(uint16_t *memzone)
{
p_channel_a = memzone + OFFSET_DAC_CHANNEL_A;
p_channel_b = memzone + OFFSET_DAC_CHANNEL_B;
p_channel_c = memzone + OFFSET_DAC_CHANNEL_C;
p_channel_d = memzone + OFFSET_DAC_CHANNEL_D;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void ExtDAC::write_data(int16_t data_a, int16_t data_b, int16_t data_c, int16_t data_d)
{
NOP;
NOP;
*p_channel_a = data_a;
*p_channel_b = data_b;
*p_channel_c = data_c;
*p_channel_d = data_d;
NOP;
NOP;
NOP;
//
}//
//
} /* namespace PERIPHERAL */

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/*
* ExtDAC.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PeripheryMap.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef PERIPHERY_EXTDAC_H_
#define PERIPHERY_EXTDAC_H_
namespace PERIPHERY
{
struct DataDACCreator
{
int16_t offset_a;
int16_t offset_b;
int16_t offset_c;
int16_t offset_d;
int16_t channel_a;
int16_t channel_b;
int16_t channel_c;
int16_t channel_d;
DataDACCreator():
offset_a((int16_t)2048),
offset_b((int16_t)2048),
offset_c((int16_t)2048),
offset_d((int16_t)2048),
channel_a((int16_t)0),
channel_b((int16_t)0),
channel_c((int16_t)0),
channel_d((int16_t)0)
{}
};//DataDACCreator
class ExtDAC
{
private:
uint16_t *p_channel_a;
uint16_t *p_channel_b;
uint16_t *p_channel_c;
uint16_t *p_channel_d;
public:
ExtDAC();
void setup(uint16_t *memzone);
public:
void write_data(int16_t data_a, int16_t data_b, int16_t data_c, int16_t data_d);
public:
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_EXTDAC_H_ */

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PERIPHERY/FRAMInterface.cpp
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PERIPHERY/FRAMInterface.h
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/*
* FRAMInterface.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <stdint.h>
#include "F28335/DSP28x_Project.h"
#include "DSP28335/GPIO.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef PERIPHERY_FRAM_H_
#define PERIPHERY_FRAM_H_
#ifndef SPIA_GPIO_SETUP_DEFAULT_DEFINES
#define SPIA_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_spia_setup)
#define SPIA_GPIO_SETUP_DEFAULT_DEFINES
#endif
#ifndef SPIA_GPIO_WRITE_PROTECT_SET_DEFINES
#define SPIA_GPIO_WRITE_PROTECT_SET (&DSP28335::GPIO::gpio_spia_write_protect_set)
#define SPIA_GPIO_WRITE_PROTECT_SET_DEFINES
#endif
//
#ifndef SPIA_GPIO_WRITE_PROTECT_CLEAR_DEFINES
#define SPIA_GPIO_WRITE_PROTECT_CLEAR (&DSP28335::GPIO::gpio_spia_write_protect_clear)
#define SPIA_GPIO_WRITE_PROTECT_CLEAR_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WREN_DEFINES
#define FRAM_OPCODE_WREN (uint16_t)0x0600
#define FRAM_OPCODE_WREN_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRDI_DEFINES
#define FRAM_OPCODE_WRDI (uint16_t)0x0400
#define FRAM_OPCODE_WRDI_DEFINES
#endif
//
#ifndef FRAM_OPCODE_RDSR_DEFINES
#define FRAM_OPCODE_RDSR (uint16_t)0x0500
#define FRAM_OPCODE_RDSR_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRSR_DEFINES
#define FRAM_OPCODE_WRSR (uint16_t)0x0100
#define FRAM_OPCODE_WRSR_DEFINES
#endif
//
#ifndef FRAM_OPCODE_READ_DEFINES
#define FRAM_OPCODE_READ (uint16_t)0x0300
#define FRAM_OPCODE_READ_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRITE_DEFINES
#define FRAM_OPCODE_WRITE (uint16_t)0x0200
#define FRAM_OPCODE_WRITE_DEFINES
#endif
//
#ifndef FRAM_OPCODE_DUMMY_DEFINES
#define FRAM_OPCODE_DUMMY (uint16_t)0x5500
#define FRAM_OPCODE_DUMMY_DEFINES
#endif
//
#ifndef FRAM_OPCODE_ERASE_DEFINES
#define FRAM_OPCODE_ERASE (uint16_t)0xFF00
#define FRAM_OPCODE_ERASE_DEFINES
#endif
//
namespace PERIPHERY
{
struct FRAMSetup
{
pGPIO_FUNCTION gpio_setup;
pGPIO_FUNCTION write_protect_set;
pGPIO_FUNCTION write_protect_clear;
FRAMSetup():
gpio_setup(SPIA_GPIO_SETUP_DEFAULT),
write_protect_set(SPIA_GPIO_WRITE_PROTECT_SET),
write_protect_clear(SPIA_GPIO_WRITE_PROTECT_CLEAR)
{}
};//
struct FRAMDATAWordField
{
uint16_t low :8;
uint16_t high :8;
};//
union FRAMDATAWord
{
uint16_t all;
FRAMDATAWordField byte;
};//
struct FRAMDATALongWord
{
FRAMDATAWord wL;
FRAMDATAWord wH;
};//
union FRAMDataVariant
{
int16_t i16;
uint16_t u16;
int32_t i32;
uint32_t u32;
float f;
bool b;
FRAMDATALongWord lw;
FRAMDataVariant():
u32((uint32_t)0)
{}
};//
class FRAMInterface
{
public:
enum mode_t {WAIT, READ, WRITE, ERASE, VERIFY, READY, RESTORE};
protected:
mode_t m_mode;
private:
//Uint16 m_fifo_tx_status;
//Uint16 m_fifo_rx_status;
private:
Uint16 m_fifo_tx[16];
Uint16 m_fifo_rx[16];
private:
uint16_t *m_buffer_pointer;
uint16_t m_buffer_size;
uint16_t m_buffer_index;
uint16_t m_fram_start_addr;
uint16_t m_fram_addr;
uint16_t m_data_fram;
uint16_t m_data_buffer;
FRAMDataVariant m_data_variant;
bool m_verify_status;
bool *m_p_verify_status;
uint16_t m_delay;
void *m_destination;
public:
FRAMInterface();
void setup();
public:
FRAMInterface::mode_t get_mode();
bool compare_mode(FRAMInterface::mode_t mode);
public:
void break_fram();
void write_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
void read_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
void erase_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
void verify_buffer(uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size, bool *verify_status);
public:
void write_slow_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
void read_slow_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
void erase_slow_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
public:
void write_int16 (uint16_t addr, int16_t data);
void write_uint16(uint16_t addr, uint16_t data);
void write_int32 (uint16_t addr, int32_t data);
void write_uint32(uint16_t addr, uint32_t data);
void write_float (uint16_t addr, float data);
void write_bool (uint16_t addr, bool data);
public:
void read_int16 (uint16_t addr, int16_t *destination);
void read_uint16(uint16_t addr, uint16_t *destination);
void read_int32 (uint16_t addr, int32_t *destination);
void read_uint32(uint16_t addr, uint32_t *destination);
void read_float (uint16_t addr, float *destination);
void read_bool (uint16_t addr, bool *destination);
private:
void (*_gpio_setup)();
public:
void set_wp();
void clear_wp();
private:
void (*_set_wp)();
void (*_clear_wp)();
public:
void execute();
private:
void (FRAMInterface::*_execute)();
void _execute_free();
void _execute_ready();
void _execute_read_buffer_get_data();
void _execute_read_status_register();
void _write_buffer();
void _read_buffer_send_opcode();
void _erase_buffer();
void _verify_buffer_send_opcode();
void _execute_verify_buffer_data();
inline void _break_fram();
private:
void _execute_ready_wren_write_buffer();
void _execute_ready_wren_erase_buffer();
void _execute_ready_write_buffer();
void _execute_ready_erase_buffer();
private:
void _execute_ready_wren_write_int16();
void _execute_ready_wren_write_uint16();
void _execute_ready_wren_write_int32();
void _execute_ready_wren_write_uint32();
void _execute_ready_wren_write_float();
void _execute_ready_wren_write_bool();
private:
void _execute_ready_write_int16();
void _execute_ready_write_uint16();
void _execute_ready_write_int32();
void _execute_ready_write_uint32();
void _execute_ready_write_float();
void _execute_ready_write_bool();
private:
void _execute_ready_read_buffer();
void _execute_ready_read_int16();
void _execute_ready_read_uint16();
void _execute_ready_read_int32();
void _execute_ready_read_uint32();
void _execute_ready_read_float();
void _execute_ready_read_bool();
private:
void _execute_write_register();
void _execute_write_16();
void _execute_ready_opcode_wren();
void _execute_ready_opcode_wrsr();
private:
inline void _prepare_execute(uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
//
inline void _spi_opcode_wren();
inline void _spi_opcode_wrsr();
//
inline void _spi_write_16();
inline void _spi_erase_16();
inline void _spi_read_16();
//
inline void _spi_write_32();
inline void _spi_erase_32();
inline void _spi_read_32();
//
inline void _spi_get_read_data_16();
inline void _spi_get_read_data_32();
inline void _spi_get_status_register();
inline uint16_t _spi_get_fifo_tx_status();
//
};//
} /* namespace PERIPHERY */
#endif /* PERIPHERY_FRAM_H_ */

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PERIPHERY/IIIPeriphery.cpp
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/*
* IIIPeriphery.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/IIIPeriphery.h"
namespace PERIPHERY
{
//CONSTRUCTOR
IIIPeriphery::IIIPeriphery():
Periphery(),
pwm_brd()
{}//CONSTRUCTOR
//
void IIIPeriphery::setup(uint16_t *memzone)
{
p_memzone = memzone;
dio.setup(p_memzone);
adc.setup(p_memzone);
dac.setup(p_memzone);
fram.setup();
pwm_brd.setup(p_memzone);
//
}//
//
void IIIPeriphery::setup(uint16_t *memzone, const IIIPeripherySetup& setup)
{
p_memzone = memzone;
dio.setup(p_memzone);
adc.setup(p_memzone, setup.extadc);
dac.setup(p_memzone);
fram.setup();
analog_faults.setup(setup.analog_faults);
pwm_brd.setup(p_memzone, setup.pwm_brd);
//
}//
//
//void IIIPeriphery::configure(IIIPeripheryConfiguration& config)
//{
//pwm_brd.configure(config.pwm_brd);
//
//}//
void IIIPeriphery::get_hard_code_setup(IIIPeripherySetup& hsetup)
{
hsetup.pwm_brd.set_default();
hsetup.extadc.set_default();
hsetup.analog_faults.set_default();
//
}//
//
} /* namespace PERIPHERY */

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PERIPHERY/IIIPeriphery.h
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/*
* IIIPeriphery.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/Periphery.h"
#ifndef PERIPHERY_IIIPERIPHERY_H_
#define PERIPHERY_IIIPERIPHERY_H_
namespace PERIPHERY
{
struct IIIPeripherySetup: public PeripherySetup
{
PWMStructureSetup pwm_brd;
IIIPeripherySetup():
PeripherySetup(),
pwm_brd()
{}
};//
//struct IIIPeripheryConfiguration
//{
//PWMABCInterfaceConfiguration pwm_brd;
// IIIPeripheryConfiguration()
// pwm_brd()
// {}
//};//PeripheryConfiguration
class IIIPeriphery: public Periphery
{
public:
PERIPHERY::PWMABCInterace pwm_brd;
public:
IIIPeriphery();
void setup(uint16_t *memzone);
void setup(uint16_t *memzone, const IIIPeripherySetup& setup);
//void configure(IIIPeripheryConfiguration& config);
void get_hard_code_setup(IIIPeripherySetup& hsetup);
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_IIIPERIPHERY_H_ */

54
PERIPHERY/IPeriphery.cpp
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/*
* IPeriphery.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/IPeriphery.h"
namespace PERIPHERY
{
//CONSTRUCTOR
IPeriphery::IPeriphery():
Periphery()
// pwm_brd()
{}//CONSTRUCTOR
//
void IPeriphery::setup(uint16_t *memzone)
{
// p_memzone = memzone;
// dio.setup(p_memzone);
// adc.setup(p_memzone);
// dac.setup(p_memzone);
// fram.setup();
// pwm_brd.setup(p_memzone);
}//
//
void IPeriphery::setup(uint16_t *memzone, const IPeripherySetup& setup)
{
// p_memzone = memzone;
// dio.setup(p_memzone);
// adc.setup(p_memzone, setup.extadc);
// dac.setup(p_memzone);
// fram.setup();
// analog_faults.setup(setup.analog_faults);
// pwm_brd.setup(p_memzone, setup.pwm_brd);
}//
//
//void IPeriphery::configure(IPeripheryConfiguration& config)
//{
// pwm_brd.configure(config.pwm_brd);
//
//}//
//
void IPeriphery::get_hard_code_setup(IPeripherySetup& hsetup)
{
// hsetup.pwm_brd.set_default();
// hsetup.extadc.set_default();
// hsetup.analog_faults.set_default();
//
}//
//
} /* namespace PERIPHERY */

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PERIPHERY/IPeriphery.h
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/*
* IPeriphery.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/Periphery.h"
#ifndef PERIPHERY_IPERIFHERY_H_
#define PERIPHERY_IPERIFHERY_H_
namespace PERIPHERY
{
struct IPeripherySetup: public PeripherySetup
{
PWMStructureSetup pwm_brd;
IPeripherySetup():
PeripherySetup(),
pwm_brd()
{}
};//
struct IPeripheryConfiguration
{
PWMSInterfaceConfiguration pwm_brd;
IPeripheryConfiguration():
pwm_brd()
{}
};//PeripheryConfiguration
class IPeriphery: public Periphery
{
public:
// PERIPHERY::PWMSInterace pwm_brd;
public:
IPeriphery();
void setup(uint16_t *memzone);
void setup(uint16_t *memzone, const IPeripherySetup& setup);
// void configure(IPeripheryConfiguration& config);
void get_hard_code_setup(IPeripherySetup& hsetup);
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_IPERIFHERY_H_ */

492
PERIPHERY/PWMABCInterace.cpp
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/*
* PWMInterace.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PWMABCInterace.h"
namespace PERIPHERY
{
//CONSTRUCTOR
PWMABCInterace::PWMABCInterace():
PWMInterface(),
m_counter_phase(0),
m_telemetry_phase_counter(0),
m_telemetry_phase_quantity(3),
m_phase(),
_telemetry_execute(&PWMABCInterace::_telemetry_sequence_one)
//
{}//CONSTRUCTOR
//
void PWMABCInterace::setup(uint16_t *memzone)
{
_setup_phase(m_phase[0], memzone + OFFSET_PWM_PHASE_A);
_setup_phase(m_phase[1], memzone + OFFSET_PWM_PHASE_B);
_setup_phase(m_phase[2], memzone + OFFSET_PWM_PHASE_C);
m_broadcast.p_order = memzone + OFFSET_BROADCAST_ORDER;
m_broadcast.p_cell_quantity_in_phase = memzone + OFFSET_BROADCAST_CELLNUMBER;
m_broadcast.p_freq = memzone + OFFSET_BROADCAST_FREQ;
//
_gpio_hard_fault_setup = &DSP28335::GPIO::gpio_hard_fault_setup;
_hard_fault_read = &DSP28335::GPIO::gpio_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
void PWMABCInterace::setup(const PWMStructureSetup& setup)
{
_gpio_hard_fault_setup = setup.p_gpio_hard_fault_setup;
_hard_fault_read = setup.p_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
void PWMABCInterace::setup(uint16_t *memzone, const PWMStructureSetup& setup)
{
_setup_phase(m_phase[0], memzone + OFFSET_PWM_PHASE_A);
_setup_phase(m_phase[1], memzone + OFFSET_PWM_PHASE_B);
_setup_phase(m_phase[2], memzone + OFFSET_PWM_PHASE_C);
m_broadcast.p_order = memzone + OFFSET_BROADCAST_ORDER;
m_broadcast.p_cell_quantity_in_phase = memzone + OFFSET_BROADCAST_CELLNUMBER;
m_broadcast.p_freq = memzone + OFFSET_BROADCAST_FREQ;
//
_gpio_hard_fault_setup = setup.p_gpio_hard_fault_setup;
_hard_fault_read = setup.p_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::initialization(PWMABCInterfaceConfiguration& config)
{
//set_frequency((uint16_t)config.pwm_frequency);
set_cell_quantity_phase(config.cell_quantity[0], config.cell_quantity[1], config.cell_quantity[2]);
set_cmp(0, 0, 0);
set_order(0);
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::_setup_phase(PWMPhaseStructure& phase, uint16_t *base)
{
phase.p_pwm_frequency = base + OFFSET_FREQ_PWM;
phase.p_cell_quantity_in_phase = base + OFFSET_CQ_IN_PHASE;
phase.p_compare = base + OFFSET_CMP;
phase.p_order = base + OFFSET_ORDER;
phase.p_pwm_state = base + OFFSET_PWM_STATE;
phase.p_pwm_version = base + OFFSET_PWM_VERSION;
phase.a_cell_quantity_in_cascade[0] = base + OFFSET_CQ_IN_CASC_00;
phase.a_cell_quantity_in_cascade[1] = base + OFFSET_CQ_IN_CASC_01;
phase.a_cell_quantity_in_cascade[2] = base + OFFSET_CQ_IN_CASC_02;
phase.a_cell_quantity_in_cascade[3] = base + OFFSET_CQ_IN_CASC_03;
phase.a_cell_quantity_in_cascade[4] = base + OFFSET_CQ_IN_CASC_04;
phase.a_cell_quantity_in_cascade[5] = base + OFFSET_CQ_IN_CASC_05;
phase.a_cell_quantity_in_cascade[6] = base + OFFSET_CQ_IN_CASC_06;
phase.a_cell_quantity_in_cascade[7] = base + OFFSET_CQ_IN_CASC_07;
phase.a_cell_quantity_in_cascade[8] = base + OFFSET_CQ_IN_CASC_08;
phase.a_cell_quantity_in_cascade[9] = base + OFFSET_CQ_IN_CASC_09;
phase.a_cell_quantity_in_cascade[10] = base + OFFSET_CQ_IN_CASC_10;
phase.a_cell_quantity_in_cascade[11] = base + OFFSET_CQ_IN_CASC_11;
phase.a_cell_quantity_in_cascade[12] = base + OFFSET_CQ_IN_CASC_12;
phase.a_cell_quantity_in_cascade[13] = base + OFFSET_CQ_IN_CASC_13;
phase.a_cell_quantity_in_cascade[14] = base + OFFSET_CQ_IN_CASC_14;
phase.a_cell_quantity_in_cascade[15] = base + OFFSET_CQ_IN_CASC_15;
phase.a_cell_quantity_in_cascade[16] = base + OFFSET_CQ_IN_CASC_16;
phase.a_cell_quantity_in_cascade[17] = base + OFFSET_CQ_IN_CASC_17;
phase.p_telemetry_box = base + OFFSET_TELEMETRY;
phase.p_breakdown_cell_state = base + OFFSET_CELL_BREAKDOWN;
phase.p_breakdown_cell_address = base + OFFSET_CELL_BREAKDOWN_ADR;
phase.a_cascade_pointers[0] = base + OFFSET_CASCADE_00;
phase.a_cascade_pointers[1] = base + OFFSET_CASCADE_01;
phase.a_cascade_pointers[2] = base + OFFSET_CASCADE_02;
phase.a_cascade_pointers[3] = base + OFFSET_CASCADE_03;
phase.a_cascade_pointers[4] = base + OFFSET_CASCADE_04;
phase.a_cascade_pointers[5] = base + OFFSET_CASCADE_05;
phase.a_cascade_pointers[6] = base + OFFSET_CASCADE_06;
phase.a_cascade_pointers[7] = base + OFFSET_CASCADE_07;
phase.a_cascade_pointers[8] = base + OFFSET_CASCADE_08;
phase.a_cascade_pointers[9] = base + OFFSET_CASCADE_09;
phase.a_cascade_pointers[10] = base + OFFSET_CASCADE_10;
phase.a_cascade_pointers[11] = base + OFFSET_CASCADE_11;
phase.a_cascade_pointers[12] = base + OFFSET_CASCADE_12;
phase.a_cascade_pointers[13] = base + OFFSET_CASCADE_13;
phase.a_cascade_pointers[14] = base + OFFSET_CASCADE_14;
phase.a_cascade_pointers[15] = base + OFFSET_CASCADE_15;
phase.a_cascade_pointers[16] = base + OFFSET_CASCADE_16;
phase.a_cascade_pointers[17] = base + OFFSET_CASCADE_17;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_frequency(uint16_t freq)
{
NOP;
NOP;
NOP;
*m_phase[0].p_pwm_frequency = freq;
*m_phase[1].p_pwm_frequency = freq;
*m_phase[2].p_pwm_frequency = freq;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cascade_quantity()
{
//m_config.cascade_quantity[0] = quant_a;
//m_config.cascade_quantity[1] = quant_b;
//m_config.cascade_quantity[2] = quant_c;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cell_quantity_phase(uint16_t quant_a, uint16_t quant_b, uint16_t quant_c)
{
// m_config.cell_quantity[0]= quant_a;
// m_config.cell_quantity[1]= quant_b;
// m_config.cell_quantity[2]= quant_c;
NOP;
NOP;
NOP;
*m_phase[0].p_cell_quantity_in_phase = quant_a;
*m_phase[1].p_cell_quantity_in_phase = quant_b;
*m_phase[2].p_cell_quantity_in_phase = quant_c;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cmp(uint16_t cmpra, uint16_t cmprb, uint16_t cmprc)
{
NOP;
NOP;
NOP;
*m_phase[0].p_compare = cmpra;
*m_phase[1].p_compare = cmprb;
*m_phase[2].p_compare = cmprc;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_order(uint16_t order)
{
NOP;
NOP;
NOP;
*m_phase[0].p_order = order;
*m_phase[1].p_order = order;
*m_phase[2].p_order = order;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_board_state(uint16_t& state_pwm_a, uint16_t& state_pwm_b, uint16_t& state_pwm_c)
{
NOP;
NOP;
NOP;
state_pwm_a = *m_phase[0].p_pwm_state;
state_pwm_b = *m_phase[1].p_pwm_state;
state_pwm_c = *m_phase[2].p_pwm_state;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_sw_version(uint16_t& version_pwm_a, uint16_t& version_pwm_b, uint16_t& version_pwm_c)
{
NOP;
NOP;
NOP;
version_pwm_a = *m_phase[0].p_pwm_version;
version_pwm_b = *m_phase[1].p_pwm_version;
version_pwm_c = *m_phase[2].p_pwm_version;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_breakdown_cell_state(uint16_t& cellstate_pwm_a, uint16_t& cellstate_pwm_b, uint16_t& cellstate_pwm_c)
{
NOP;
NOP;
NOP;
cellstate_pwm_a = *m_phase[0].p_breakdown_cell_state;
cellstate_pwm_b = *m_phase[1].p_breakdown_cell_state;
cellstate_pwm_c = *m_phase[2].p_breakdown_cell_state;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_breakdown_cell_index(uint16_t& cellindex_pwm_a, uint16_t& cellindex_pwm_b, uint16_t& cellindex_pwm_c)
{
NOP;
NOP;
NOP;
cellindex_pwm_a = *m_phase[0].p_breakdown_cell_address;
cellindex_pwm_b = *m_phase[1].p_breakdown_cell_address;
cellindex_pwm_c = *m_phase[2].p_breakdown_cell_address;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cell_quantity_cascade(uint16_t phase_index, uint16_t cascadenum, uint16_t quant)
{
// m_config.cell_quantity_in_cascade[phase_index][cascadenum] = quant;
NOP;
NOP;
NOP;
*m_phase[phase_index].a_cell_quantity_in_cascade[cascadenum] = quant;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::broadcast_order(uint16_t order)
{
NOP;
NOP;
NOP;
*m_broadcast.p_order = order;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::broadcast_cell_quantity_phase(uint16_t quant)
{
// m_config.cell_quantity[0]= quant;
// m_config.cell_quantity[1]= quant;
// m_config.cell_quantity[2]= quant;
NOP;
NOP;
NOP;
*m_broadcast.p_cell_quantity_in_phase = quant;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::broadcast_freq(uint16_t freq)
{
// m_config.pwm_frequency = freq;
NOP;
NOP;
NOP;
*m_broadcast.p_freq = freq;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_hard_fault(uint16_t& hard_fault)
{
(*_hard_fault_read)(m_hard_fault.all);
hard_fault = m_hard_fault.all;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_indirect_access(uint16_t phase, uint16_t cascade, uint16_t cell, uint16_t offset, uint16_t& telemetry)
{
m_aux_pointer = m_phase[phase].a_cascade_pointers[cascade] + m_offset_cells.cell_offset[cell];
NOP;
NOP;
NOP;
*m_phase[phase].p_telemetry_box = offset;
telemetry = *m_aux_pointer;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::telemetry_execute(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3])
{
(this->*_telemetry_execute)(config, telemetry_phase);
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::reset_telemetry()
{
m_telemetry_phase_counter = 0;
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_telemetry_sequence_one()
{
m_telemetry_phase_counter = 0;
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
_telemetry_execute = &PWMABCInterace::_telemetry_sequence_one;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_telemetry_sequence_two()
{
m_telemetry_phase_counter = 0;
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
_telemetry_execute = &PWMABCInterace::_telemetry_sequence_two;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::_telemetry_sequence_one(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3])
{
//
m_telemetry_function_quantity = 11;
m_telemetry_cascade_quantity = config.cascade_quantity[m_telemetry_phase_counter];
m_telemetry_cell_quantity = config.cell_quantity_in_cascade[m_telemetry_phase_counter][m_telemetry_cascade_counter];
//
switch(m_telemetry_function_counter)
{
case 0:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.state, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].state);
break;
}
case 1:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.saw_init_val, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].saw_init_val);
break;
}
case 2:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.version, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].version);
break;
}
case 3:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.t_pcb, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].t_pcb);
break;
}
case 4:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.ctrl_faults, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].ctrl_faults);
break;
}
case 5:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.int_bd_l, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].int_bd_l);
break;
}
case 6:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.voltage, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].voltage);
break;
}
case 7:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.freq_pwm, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].freq_pwm);
break;
}
case 8:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.time_cntr, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].time_cntr);
break;
}
case 9:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.t_rad, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].t_rad);
break;
}
case 10:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.sync_faults, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].sync_faults);
break;
}
case 11:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.int_bd_h, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].int_bd_h);
break;
}
default:{}
}//switch
m_telemetry_cell_counter++;
if(m_telemetry_cell_counter >= m_telemetry_cell_quantity)
{
m_telemetry_cell_counter = 0;
m_telemetry_cascade_counter++;
if(m_telemetry_cascade_counter >= m_telemetry_cascade_quantity)
{
m_telemetry_cascade_counter = 0;
m_telemetry_function_counter++;
if(m_telemetry_function_counter > m_telemetry_function_quantity)
{
m_telemetry_function_counter = 0;
m_telemetry_phase_counter++;
if(m_telemetry_phase_counter >= m_telemetry_phase_quantity)
{
m_telemetry_phase_counter = 0;
//
}//if
}//if
//
}//if
//
}//if
//
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::_telemetry_sequence_two(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3])
{
//
}//
//
//
} /* namespace PERIPHERAL */

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/*
* PWMABCInterace.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PWMInterface.h"
#ifndef PERIPHERY_PWMABCINTERACE_H_
#define PERIPHERY_PWMABCINTERACE_H_
namespace PERIPHERY
{
struct PWMABCInterfaceConfiguration: public PWMInterfaceConfiguration
{
uint16_t cascade_quantity[3];
uint16_t cell_quantity[3];
uint16_t cell_quantity_in_cascade[3][18];
PWMABCInterfaceConfiguration():
PWMInterfaceConfiguration(),
cascade_quantity(),
cell_quantity(),
cell_quantity_in_cascade()
{}
};//PWMInterfaceConfiguration
struct PWMABCPhaseValueStructure
{
uint16_t pwm_frequency;
uint16_t adc_isr_multiplier;
uint16_t cascade_quantity[3];
uint16_t cell_quantity_in_phase[3];
uint16_t cmp[3];
uint16_t order;
uint16_t pwm_state[3];
uint16_t pwm_version[3];
uint16_t cell_quantity_in_cascade[3][18];
uint16_t breakdown_cell_state[3];
PWMBreakdownCellAddressRegister breakdown_cell_address[3];
PWMABCPhaseValueStructure():
pwm_frequency(0),
adc_isr_multiplier(1),
cascade_quantity(),
cell_quantity_in_phase(),
cmp(),
order(0),
pwm_state(),
pwm_version(),
cell_quantity_in_cascade(),
breakdown_cell_state(),
breakdown_cell_address()
{}
};//PWMABCPhaseValueStructure
struct PWMABCStructureReference: public PWMABCPhaseValueStructure
{
uint16_t broadcast_order;
uint16_t broadcast_cell_quantity;
uint16_t broadcast_freq;
PWMHardFaultRegister hard_fault;
PWMABCStructureReference():
PWMABCPhaseValueStructure(),
broadcast_order(),
broadcast_cell_quantity(),
broadcast_freq(),
hard_fault()
{}
};//PWMABCStructureReference
class PWMABCInterace: public PWMInterface
{
private:
uint16_t m_counter_phase;
private:
uint16_t m_telemetry_phase_counter;
uint16_t m_telemetry_phase_quantity;
private:
PWMPhaseStructure m_phase[3];
public:
PWMABCInterace();
public:
void setup(uint16_t *memzone);
void setup(const PWMStructureSetup& setup);
void setup(uint16_t *memzone, const PWMStructureSetup& setup);
public:
void initialization(PWMABCInterfaceConfiguration& config);
private:
void _setup_phase(PWMPhaseStructure& phase, uint16_t *base);
//
public:
void set_frequency(uint16_t freq);
void set_cascade_quantity();
void set_cell_quantity_phase(uint16_t quant_a, uint16_t quant_b, uint16_t quant_c);
void set_cmp(uint16_t cmpra, uint16_t cmprb, uint16_t cmprc);
void set_order(uint16_t order);
void get_board_state(uint16_t& state_pwm_a, uint16_t& state_pwm_b, uint16_t& state_pwm_c);
void get_sw_version(uint16_t& version_pwm_a, uint16_t& version_pwm_b, uint16_t& version_pwm_c);
void get_breakdown_cell_state(uint16_t& cellstate_pwm_a, uint16_t& cellstate_pwm_b, uint16_t& cellstate_pwm_c);
void get_breakdown_cell_index(uint16_t& cellindex_pwm_a, uint16_t& cellindex_pwm_b, uint16_t& cellindex_pwm_c);
void set_cell_quantity_cascade(uint16_t phase_index, uint16_t cascadenum, uint16_t quant);
//
void broadcast_order(uint16_t order);
void broadcast_cell_quantity_phase(uint16_t quant);
void broadcast_freq(uint16_t freq);
//
void get_hard_fault(uint16_t& hard_fault);
//
void get_indirect_access(uint16_t phase, uint16_t cascade, uint16_t cell, uint16_t offset, uint16_t& telemetry);
//
void telemetry_execute(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3]);
void reset_telemetry();
void set_telemetry_sequence_one();
void set_telemetry_sequence_two();
//
private:
void (PWMABCInterace::*_telemetry_execute)(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3]);
void _telemetry_sequence_one(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3]);
void _telemetry_sequence_two(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3]);
//
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_PWMABCINTERACE_H_ */

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/*
* PWMInterface.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PWMInterface.h"
namespace PERIPHERY
{
//CONSTRUCTOR
PWMInterface::PWMInterface():
m_counter_cascade(0),
m_counter_cells(0),
m_aux_offset(0),
m_aux_cell_quantity(0),
m_aux_pointer(0),
//
m_telemetry_function_counter(0),
m_telemetry_cascade_counter (0),
m_telemetry_cell_counter (0),
//
m_telemetry_function_quantity(0),
m_telemetry_cascade_quantity (0),
m_telemetry_cell_quantity (0),
//
m_broadcast(),
m_telemetry_fields_offset(0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x011, 0x012, 0x013, 0x014, 0x015, 0x016),
m_offset_cells(),
m_hard_fault(),
_gpio_hard_fault_setup(&DSP28335::GPIO::gpio_hard_fault_setup),
_hard_fault_read(&DSP28335::GPIO::gpio_hard_fault_read)
{}//CONSTRUCTOR
} /* namespace PERIPHERY */

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/*
* PWMInterface.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include "DSP28335/GPIO.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#include "PERIPHERY/PeripheryMap.h"
#ifndef PERIPHERY_PWMINTERFACE_H_
#define PERIPHERY_PWMINTERFACE_H_
namespace PERIPHERY
{
struct PWMStructureSetup
{
pGPIO_FUNCTION p_gpio_hard_fault_setup;
pGPIO_FUNCTION_UINT p_hard_fault_read;
void set_default()
{
p_gpio_hard_fault_setup = &DSP28335::GPIO::gpio_hard_fault_setup;
p_hard_fault_read = &DSP28335::GPIO::gpio_hard_fault_read;
};
PWMStructureSetup():
p_gpio_hard_fault_setup(&DSP28335::GPIO::gpio_hard_fault_setup),
p_hard_fault_read(&DSP28335::GPIO::gpio_hard_fault_read)
{}
};//PWMStructureSetup
struct PWMBreakdownCellAddressFields
{
uint16_t cell: 3;
uint16_t cascade: 5;
uint16_t reserved: 8;
};//PWMBreakdownCellAddressFields
union PWMBreakdownCellAddressRegister
{
uint16_t all;
PWMBreakdownCellAddressFields field;
PWMBreakdownCellAddressRegister():
all(0)
{}
//
};//PWMBreakdownCellAddressRegister
struct PWMHardFaultBitField
{
uint16_t a: 1;
uint16_t b: 1;
uint16_t c: 1;
//
};//PWMHardFaultBitField
union PWMHardFaultRegister
{
uint16_t all;
PWMHardFaultBitField bit;
PWMHardFaultRegister():
all(0)
{}
//
};//PWMHardFaultRegister
struct PWMBroadcastRegisters
{
uint16_t *p_order;
uint16_t *p_cell_quantity_in_phase;
uint16_t *p_freq;
PWMBroadcastRegisters():
p_order(0),
p_cell_quantity_in_phase(0),
p_freq(0)
{}
};//PWMBroadCastRegisters
struct PWMOffsetCells
{
uint16_t cell_offset[8];
PWMOffsetCells():
cell_offset()
{
cell_offset[0] = 0;
cell_offset[1] = 1;
cell_offset[2] = 2;
cell_offset[3] = 3;
cell_offset[4] = 4;
cell_offset[5] = 5;
cell_offset[6] = 6;
cell_offset[7] = 7;
}
};//PWMOffsetCells
struct PWMPhaseStructure
{
uint16_t *p_pwm_frequency;
uint16_t *p_cell_quantity_in_phase;
uint16_t *p_compare;
uint16_t *p_order;
uint16_t *p_pwm_state;
uint16_t *p_pwm_version;
uint16_t *a_cell_quantity_in_cascade[18];
uint16_t *a_cascade_pointers[18];
uint16_t *p_telemetry_box;
uint16_t *p_breakdown_cell_state;
uint16_t *p_breakdown_cell_address;
PWMPhaseStructure():
p_pwm_frequency(),
p_cell_quantity_in_phase(),
p_compare(),
p_order(),
p_pwm_state(),
p_pwm_version(),
a_cell_quantity_in_cascade(),
a_cascade_pointers(),
p_telemetry_box(),
p_breakdown_cell_state(),
p_breakdown_cell_address()
{}
};//PWMPhaseStructure
struct PWMPhaseValueStructure
{
uint16_t pwm_frequency;
uint16_t cascade_quantity;
uint16_t cell_quantity_in_phase;
uint16_t cmp;
uint16_t order;
uint16_t pwm_state;
uint16_t pwm_version;
uint16_t cell_quantity_in_cascade[18];
uint16_t breakdown_cell_state;
PWMBreakdownCellAddressRegister breakdown_cell_address;
PWMPhaseValueStructure():
pwm_frequency(0),
cascade_quantity(0),
cell_quantity_in_phase(0),
cmp(0),
order(0),
pwm_state(0),
pwm_version(0),
cell_quantity_in_cascade(),
breakdown_cell_state(),
breakdown_cell_address()
{}
};//PWMPhaseValueStructure
struct PWMTelemetryFieldsOffset
{
uint16_t state;
uint16_t saw_init_val;
uint16_t version;
uint16_t t_pcb;
uint16_t ctrl_faults;
uint16_t int_bd_l;
uint16_t voltage;
uint16_t freq_pwm;
uint16_t time_cntr;
uint16_t t_rad;
uint16_t sync_faults;
uint16_t int_bd_h;
PWMTelemetryFieldsOffset(
uint16_t state,
uint16_t saw_init_val,
uint16_t version,
uint16_t t_pcb,
uint16_t ctrl_faults,
uint16_t int_bd_l,
uint16_t voltage,
uint16_t freq_pwm,
uint16_t time_cntr,
uint16_t t_rad,
uint16_t sync_faults,
uint16_t int_bd_h
):
state(state),
saw_init_val(saw_init_val),
version(version),
t_pcb(t_pcb),
ctrl_faults(ctrl_faults),
int_bd_l(int_bd_l),
voltage(voltage),
freq_pwm(freq_pwm),
time_cntr(time_cntr),
t_rad(t_rad),
sync_faults(sync_faults),
int_bd_h(int_bd_h)
{}
};//PWMTelemetryFieldsOffset
struct PWMTelemetryCellFieldsValue
{
uint16_t state;
uint16_t saw_init_val;
uint16_t version;
uint16_t t_pcb;
uint16_t ctrl_faults;
uint16_t int_bd_l;
uint16_t voltage;
uint16_t freq_pwm;
uint16_t time_cntr;
uint16_t t_rad;
uint16_t sync_faults;
uint16_t int_bd_h;
PWMTelemetryCellFieldsValue():
state(0),
saw_init_val(0),
version(0),
t_pcb(0),
ctrl_faults(0),
int_bd_l(0),
voltage(0),
freq_pwm(0),
time_cntr(0),
t_rad(0),
sync_faults(0),
int_bd_h(0)
{}
};//PWMTelemetryCellFieldsValue
struct PWMCascadeTelemetryValue
{
PWMTelemetryCellFieldsValue cell[8];
PWMCascadeTelemetryValue():
cell()
{}
};//PWMCascadeTelemetryValue
struct PWMPhaseTelemetryValue
{
PWMCascadeTelemetryValue cascade[18];
PWMPhaseTelemetryValue():
cascade()
{}
};//PWMPhaseTelemetryValue
struct PWMStructureReference: public PWMPhaseValueStructure
{
uint16_t broadcast_order;
uint16_t broadcast_cell_quantity;
uint16_t broadcast_freq;
PWMHardFaultRegister hard_fault;
PWMStructureReference():
PWMPhaseValueStructure(),
broadcast_order(0),
broadcast_cell_quantity(0),
broadcast_freq(0),
hard_fault()
{}
};//PWMStructureReference
struct PWMInterfaceConfiguration
{
float pwm_frequency;
uint16_t adc_isr_quantity;
float adc_isr_offset_relative;
PWMInterfaceConfiguration():
pwm_frequency(500.0),
adc_isr_quantity(1),
adc_isr_offset_relative(FP_ZERO)
{}
//
};//PWMInterfaceConfiguration
struct PWMControlOrder
{
enum ORDER
{
START = 0x1111, // start the DVR, and cells start working and outputing
STOP = 0x2222, // stop the DVR, and cells stop working and outputing
RESET = 0x4444, // reset pwm fault and cells fault
SELFCHECK = 0x8888 // make cells to check themselves
};//
};
class PWMInterface
{
protected:
uint16_t m_counter_cascade;
uint16_t m_counter_cells;
uint16_t m_aux_offset;
uint16_t m_aux_cell_quantity;
uint16_t *m_aux_pointer;
protected:
uint16_t m_telemetry_function_counter;
uint16_t m_telemetry_cascade_counter;
uint16_t m_telemetry_cell_counter;
uint16_t m_telemetry_function_quantity;
uint16_t m_telemetry_cascade_quantity;
uint16_t m_telemetry_cell_quantity;
protected:
PWMBroadcastRegisters m_broadcast;
PWMTelemetryFieldsOffset m_telemetry_fields_offset;
PWMOffsetCells m_offset_cells;
PWMHardFaultRegister m_hard_fault;
public:
PWMInterface();
protected:
void (*_gpio_hard_fault_setup)();
void (*_hard_fault_read)(uint16_t& data);
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_PWMINTERFACE_H_ */

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/*
* PWMSingleInterace.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PWMSInterace.h"
namespace PERIPHERY
{
//CONSTRUCTOR
PWMSInterace::PWMSInterace():
PWMInterface(),
m_phase(),
//
_telemetry_execute(&PWMSInterace::_telemetry_sequence_one)
//
{}//CONSTRUCTOR
//
void PWMSInterace::setup(uint16_t *memzone)
{
_setup_phase(m_phase, memzone + OFFSET_PWM_PHASE);
m_broadcast.p_order = memzone + OFFSET_BROADCAST_ORDER;
m_broadcast.p_cell_quantity_in_phase = memzone + OFFSET_BROADCAST_CELLNUMBER;
m_broadcast.p_freq = memzone + OFFSET_BROADCAST_FREQ;
//
_gpio_hard_fault_setup = &DSP28335::GPIO::gpio_hard_fault_setup;
_hard_fault_read = &DSP28335::GPIO::gpio_hard_fault_read;
(*_gpio_hard_fault_setup)();
//
set_telemetry_sequence_one();
//
}//
//
//
void PWMSInterace::setup(const PWMStructureSetup& setup)
{
_gpio_hard_fault_setup = setup.p_gpio_hard_fault_setup;
_hard_fault_read = setup.p_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
void PWMSInterace::setup(uint16_t *memzone, const PWMStructureSetup& setup)
{
_setup_phase(m_phase, memzone + OFFSET_PWM_PHASE);
m_broadcast.p_order = memzone + OFFSET_BROADCAST_ORDER;
m_broadcast.p_cell_quantity_in_phase = memzone + OFFSET_BROADCAST_CELLNUMBER;
m_broadcast.p_freq = memzone + OFFSET_BROADCAST_FREQ;
//
_gpio_hard_fault_setup = setup.p_gpio_hard_fault_setup;
_hard_fault_read = setup.p_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
void PWMSInterace::_setup_phase(PWMPhaseStructure& phase, uint16_t *base)
{
phase.p_pwm_frequency = base + OFFSET_FREQ_PWM;
phase.p_cell_quantity_in_phase = base + OFFSET_CQ_IN_PHASE;
phase.p_compare = base + OFFSET_CMP;
phase.p_order = base + OFFSET_ORDER;
phase.p_pwm_state = base + OFFSET_PWM_STATE;
phase.p_pwm_version = base + OFFSET_PWM_VERSION;
phase.a_cell_quantity_in_cascade[0] = base + OFFSET_CQ_IN_CASC_00;
phase.a_cell_quantity_in_cascade[1] = base + OFFSET_CQ_IN_CASC_01;
phase.a_cell_quantity_in_cascade[2] = base + OFFSET_CQ_IN_CASC_02;
phase.a_cell_quantity_in_cascade[3] = base + OFFSET_CQ_IN_CASC_03;
phase.a_cell_quantity_in_cascade[4] = base + OFFSET_CQ_IN_CASC_04;
phase.a_cell_quantity_in_cascade[5] = base + OFFSET_CQ_IN_CASC_05;
phase.a_cell_quantity_in_cascade[6] = base + OFFSET_CQ_IN_CASC_06;
phase.a_cell_quantity_in_cascade[7] = base + OFFSET_CQ_IN_CASC_07;
phase.a_cell_quantity_in_cascade[8] = base + OFFSET_CQ_IN_CASC_08;
phase.a_cell_quantity_in_cascade[9] = base + OFFSET_CQ_IN_CASC_09;
phase.a_cell_quantity_in_cascade[10] = base + OFFSET_CQ_IN_CASC_10;
phase.a_cell_quantity_in_cascade[11] = base + OFFSET_CQ_IN_CASC_11;
phase.a_cell_quantity_in_cascade[12] = base + OFFSET_CQ_IN_CASC_12;
phase.a_cell_quantity_in_cascade[13] = base + OFFSET_CQ_IN_CASC_13;
phase.a_cell_quantity_in_cascade[14] = base + OFFSET_CQ_IN_CASC_14;
phase.a_cell_quantity_in_cascade[15] = base + OFFSET_CQ_IN_CASC_15;
phase.a_cell_quantity_in_cascade[16] = base + OFFSET_CQ_IN_CASC_16;
phase.a_cell_quantity_in_cascade[17] = base + OFFSET_CQ_IN_CASC_17;
phase.p_telemetry_box = base + OFFSET_TELEMETRY;
phase.p_breakdown_cell_state = base + OFFSET_CELL_BREAKDOWN;
phase.p_breakdown_cell_address = base + OFFSET_CELL_BREAKDOWN_ADR;
phase.a_cascade_pointers[0] = base + OFFSET_CASCADE_00;
phase.a_cascade_pointers[1] = base + OFFSET_CASCADE_01;
phase.a_cascade_pointers[2] = base + OFFSET_CASCADE_02;
phase.a_cascade_pointers[3] = base + OFFSET_CASCADE_03;
phase.a_cascade_pointers[4] = base + OFFSET_CASCADE_04;
phase.a_cascade_pointers[5] = base + OFFSET_CASCADE_05;
phase.a_cascade_pointers[6] = base + OFFSET_CASCADE_06;
phase.a_cascade_pointers[7] = base + OFFSET_CASCADE_07;
phase.a_cascade_pointers[8] = base + OFFSET_CASCADE_08;
phase.a_cascade_pointers[9] = base + OFFSET_CASCADE_09;
phase.a_cascade_pointers[10] = base + OFFSET_CASCADE_10;
phase.a_cascade_pointers[11] = base + OFFSET_CASCADE_11;
phase.a_cascade_pointers[12] = base + OFFSET_CASCADE_12;
phase.a_cascade_pointers[13] = base + OFFSET_CASCADE_13;
phase.a_cascade_pointers[14] = base + OFFSET_CASCADE_14;
phase.a_cascade_pointers[15] = base + OFFSET_CASCADE_15;
phase.a_cascade_pointers[16] = base + OFFSET_CASCADE_16;
phase.a_cascade_pointers[17] = base + OFFSET_CASCADE_17;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::set_frequency(uint16_t freq)
{
NOP;
NOP;
NOP;
*m_phase.p_pwm_frequency = freq;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
//void PWMSInterace::set_cascade_quantity(uint16_t quant)
//{
//m_config.cascade_quantity = quant;
//
//}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::set_cell_quantity_phase(uint16_t quant)
{
NOP;
NOP;
NOP;
*m_phase.p_cell_quantity_in_phase = quant;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::set_cmp(uint16_t cmpr)
{
NOP;
NOP;
NOP;
*m_phase.p_compare = cmpr;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::set_order(uint16_t order)
{
NOP;
NOP;
NOP;
*m_phase.p_order = order;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::get_board_state(uint16_t& state)
{
NOP;
NOP;
NOP;
state = *m_phase.p_pwm_state;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::get_sw_version(uint16_t& version)
{
NOP;
NOP;
NOP;
version = *m_phase.p_pwm_version;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::get_breakdown_cell_state(uint16_t& cellstate)
{
NOP;
NOP;
NOP;
cellstate = *m_phase.p_breakdown_cell_state;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::get_breakdown_cell_index(uint16_t& cellindex)
{
NOP;
NOP;
NOP;
cellindex = *m_phase.p_breakdown_cell_address;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::set_cell_quantity_cascade(uint16_t cascadenum, uint16_t quant)
{
NOP;
NOP;
NOP;
*m_phase.a_cell_quantity_in_cascade[cascadenum] = quant;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::broadcast_order(uint16_t order)
{
NOP;
NOP;
NOP;
*m_broadcast.p_order = order;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::broadcast_cell_quantity_phase(uint16_t quant)
{
NOP;
NOP;
NOP;
*m_broadcast.p_cell_quantity_in_phase = quant;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::broadcast_freq(uint16_t freq)
{
NOP;
NOP;
NOP;
*m_broadcast.p_freq = freq;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::get_hard_fault(uint16_t& hard_fault)
{
(*_hard_fault_read)(m_hard_fault.all);
hard_fault = m_hard_fault.all;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::get_indirect_access(uint16_t cascade, uint16_t cell, uint16_t offset, uint16_t& telemetry)
{
//
m_aux_pointer = m_phase.a_cascade_pointers[cascade] + m_offset_cells.cell_offset[cell];
//
NOP;
NOP;
NOP;
*m_phase.p_telemetry_box = offset;
telemetry = *m_aux_pointer;
NOP;
NOP;
NOP;
//
}//
//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::telemetry_execute(PWMSInterfaceConfiguration& config, PWMPhaseTelemetryValue& telemetry_phase)
{
(this->*_telemetry_execute)(config, telemetry_phase);
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::reset_telemetry()
{
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::set_telemetry_sequence_one()
{
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
_telemetry_execute = &PWMSInterace::_telemetry_sequence_one;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::set_telemetry_sequence_two()
{
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
_telemetry_execute = &PWMSInterace::_telemetry_sequence_two;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::_telemetry_sequence_one(PWMSInterfaceConfiguration& config, PWMPhaseTelemetryValue& telemetry_phase)
{
//
m_telemetry_function_quantity = 11;
m_telemetry_cascade_quantity = config.cascade_quantity;
m_telemetry_cell_quantity = config.cell_quantity_in_cascade[m_telemetry_cascade_counter];
//
switch(m_telemetry_function_counter)
{
case 0:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.state, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].state); break;}
case 1:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.saw_init_val, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].saw_init_val); break;}
case 2:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.version, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].version); break;}
case 3:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.t_pcb, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].t_pcb); break;}
case 4:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.ctrl_faults, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].ctrl_faults); break;}
case 5:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.int_bd_l, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].int_bd_l); break;}
case 6:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.voltage, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].voltage); break;}
case 7:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.freq_pwm, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].freq_pwm); break;}
case 8:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.time_cntr, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].time_cntr); break;}
case 9:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.t_rad, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].t_rad); break;}
case 10:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.sync_faults, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].sync_faults); break;}
case 11:{ get_indirect_access(m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.int_bd_h, telemetry_phase.cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].int_bd_h); break;}
default:{}
}//switch
//
m_telemetry_cell_counter++;
if(m_telemetry_cell_counter >= m_telemetry_cell_quantity)
{
m_telemetry_cell_counter = 0;
m_telemetry_cascade_counter++;
if(m_telemetry_cascade_counter >= m_telemetry_cascade_quantity)
{
m_telemetry_cascade_counter = 0;
m_telemetry_function_counter++;
if(m_telemetry_function_counter > m_telemetry_function_quantity)
{
m_telemetry_function_counter = 0;
}//if
//
}//if
//
}//if
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMSInterace::_telemetry_sequence_two(PWMSInterfaceConfiguration& config, PWMPhaseTelemetryValue& telemetry_phase)
{
//
}//
//
//
} /* namespace PERIPHERY */

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PERIPHERY/PWMSInterace.h
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/*
* PWMSingleInterace.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PWMInterface.h"
#ifndef CELLQAUNTITYINPHASE
#define CELLQAUNTITYINPHASE 5
#endif
#ifndef PERIPHERY_PWMSINGLEINTERFACE_H_
#define PERIPHERY_PWMSINGLEINTERFACE_H_
namespace PERIPHERY
{
struct PWMSInterfaceConfiguration: public PWMInterfaceConfiguration
{
uint16_t cascade_quantity;
uint16_t cell_quantity;
uint16_t cell_quantity_in_cascade[18];
PWMSInterfaceConfiguration():
PWMInterfaceConfiguration(),
cascade_quantity(),
cell_quantity(0),
cell_quantity_in_cascade()
{}
};//PWMSingleStructureConfiguration
class PWMSInterace: public PWMInterface
{
private:
PWMPhaseStructure m_phase;
PWMHardFaultRegister m_hard_fault;
public:
PWMSInterace();
public:
void setup(uint16_t *memzone);
void setup(const PWMStructureSetup& setup);
void setup(uint16_t *memzone, const PWMStructureSetup& setup);
private:
void _setup_phase(PWMPhaseStructure& phase, uint16_t *base);
public:
void set_frequency(uint16_t freq);
//void set_cascade_quantity(uint16_t quant);
void set_cell_quantity_phase(uint16_t quant);
void set_cmp(uint16_t cmpr);
void set_order(uint16_t order);
void get_board_state(uint16_t& statebard);
void get_sw_version(uint16_t& version);
void get_breakdown_cell_state(uint16_t& cellstate);
void get_breakdown_cell_index(uint16_t& cellindex);
void set_cell_quantity_cascade(uint16_t cascadenum, uint16_t quant);
//
void broadcast_order(uint16_t order);
void broadcast_cell_quantity_phase(uint16_t quant);
void broadcast_freq(uint16_t freq);
//
void get_hard_fault(uint16_t& hard_fault);
//
void get_indirect_access(uint16_t cascade, uint16_t cell, uint16_t offset, uint16_t& telemetry);
//
void telemetry_execute(PWMSInterfaceConfiguration& config, PWMPhaseTelemetryValue& telemetry_phase);
void reset_telemetry();
void set_telemetry_sequence_one();
void set_telemetry_sequence_two();
//
private:
void (PWMSInterace::*_telemetry_execute)(PWMSInterfaceConfiguration& config, PWMPhaseTelemetryValue& telemetry_phase);
void _telemetry_sequence_one(PWMSInterfaceConfiguration& config, PWMPhaseTelemetryValue& telemetry_phase);
void _telemetry_sequence_two(PWMSInterfaceConfiguration& config, PWMPhaseTelemetryValue& telemetry_phase);
//
};//class
} /* namespace PERIPHERY */
#endif /* PERIPHERY_PWMSINGLEINTERFACE_H_ */

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PERIPHERY/Periphery.cpp
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/*
* Periphery.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/Periphery.h"
// #include "PERIPHERY/CAN.h"
namespace PERIPHERY
{
//CONSTRUCTOR
Periphery::Periphery():
p_memzone(0),
dio(),
adc(),
dac(),
fram(),
analog_faults()
{}//CONSTRUCTOR
} /* namespace PERIPHERY */

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PERIPHERY/Periphery.h
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/*
* Periphery.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include "PERIPHERY/AnalogFault.h"
// #include "PERIPHERY/CAN.h"
#include "PERIPHERY/DigitalIO.h"
#include "PERIPHERY/ExtADC.h"
#include "PERIPHERY/ExtDAC.h"
#include "PERIPHERY/FRAMInterface.h"
#include "PERIPHERY/PeripheryMap.h"
#include "PERIPHERY/PWMABCInterace.h"
#include "PERIPHERY/PWMSInterace.h"
#ifndef PERIPHERAL_PERIPHERAL_H_
#define PERIPHERAL_PERIPHERAL_H_
namespace PERIPHERY
{
struct PeripherySetup
{
PERIPHERY::ExtADCSetup extadc;
PERIPHERY::AnaloFaultSetup analog_faults;
PeripherySetup():
extadc(),
analog_faults()
{}
};//PeripheralSetupStructure
class Periphery
{
protected:
uint16_t *p_memzone;
public:
PERIPHERY::DigitalIO dio;
PERIPHERY::ExtADC adc;
PERIPHERY::ExtDAC dac;
PERIPHERY::FRAMInterface fram;
PERIPHERY::AnalogFault analog_faults;
public:
Periphery();
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_PERIPHERY_H_ */

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PERIPHERY/PeripheryMap.h
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/*
* PeripheryMap.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#ifndef PERIPHERY_PERIPHERYMAP_H_
#define PERIPHERY_PERIPHERYMAP_H_
#define OFFSET_PWM_PHASE_A ((uint16_t)0x0100)
#define OFFSET_PWM_PHASE_B ((uint16_t)0x0200)
#define OFFSET_PWM_PHASE_C ((uint16_t)0x0300)
#define OFFSET_PWM_PHASE OFFSET_PWM_PHASE_C
#define OFFSET_BROADCAST_FREQ ((uint16_t)0x0490)
#define OFFSET_BROADCAST_CELLNUMBER ((uint16_t)0x0491)
#define OFFSET_BROADCAST_ORDER ((uint16_t)0x0493)
#define OFFSET_FREQ_PWM ((uint16_t)0x0090)
#define OFFSET_CQ_IN_PHASE ((uint16_t)0x0091)
#define OFFSET_CMP ((uint16_t)0x0092)
#define OFFSET_ORDER ((uint16_t)0x0093)
#define OFFSET_PWM_STATE ((uint16_t)0x0094)
#define OFFSET_PWM_VERSION ((uint16_t)0x0095)
#define OFFSET_CQ_IN_CASC_00 ((uint16_t)0x0096)
#define OFFSET_CQ_IN_CASC_01 ((uint16_t)0x0097)
#define OFFSET_CQ_IN_CASC_02 ((uint16_t)0x0098)
#define OFFSET_CQ_IN_CASC_03 ((uint16_t)0x0099)
#define OFFSET_CQ_IN_CASC_04 ((uint16_t)0x009A)
#define OFFSET_CQ_IN_CASC_05 ((uint16_t)0x009B)
#define OFFSET_CQ_IN_CASC_06 ((uint16_t)0x009C)
#define OFFSET_CQ_IN_CASC_07 ((uint16_t)0x009D)
#define OFFSET_CQ_IN_CASC_08 ((uint16_t)0x009E)
#define OFFSET_CQ_IN_CASC_09 ((uint16_t)0x009F)
#define OFFSET_CQ_IN_CASC_10 ((uint16_t)0x00A0)
#define OFFSET_CQ_IN_CASC_11 ((uint16_t)0x00A1)
#define OFFSET_CQ_IN_CASC_12 ((uint16_t)0x00A2)
#define OFFSET_CQ_IN_CASC_13 ((uint16_t)0x00A3)
#define OFFSET_CQ_IN_CASC_14 ((uint16_t)0x00A4)
#define OFFSET_CQ_IN_CASC_15 ((uint16_t)0x00A5)
#define OFFSET_CQ_IN_CASC_16 ((uint16_t)0x00A6)
#define OFFSET_CQ_IN_CASC_17 ((uint16_t)0x00A7)
#define OFFSET_CELL_BREAKDOWN ((uint16_t)0x00A8)
#define OFFSET_CELL_BREAKDOWN_ADR ((uint16_t)0x00A9)
#define OFFSET_TELEMETRY ((uint16_t)0x00FF)
#define OFFSET_CASCADE_00 ((uint16_t)0x0000)
#define OFFSET_CASCADE_01 ((uint16_t)0x0008)
#define OFFSET_CASCADE_02 ((uint16_t)0x0010)
#define OFFSET_CASCADE_03 ((uint16_t)0x0018)
#define OFFSET_CASCADE_04 ((uint16_t)0x0020)
#define OFFSET_CASCADE_05 ((uint16_t)0x0028)
#define OFFSET_CASCADE_06 ((uint16_t)0x0030)
#define OFFSET_CASCADE_07 ((uint16_t)0x0038)
#define OFFSET_CASCADE_08 ((uint16_t)0x0040)
#define OFFSET_CASCADE_09 ((uint16_t)0x0048)
#define OFFSET_CASCADE_10 ((uint16_t)0x0050)
#define OFFSET_CASCADE_11 ((uint16_t)0x0058)
#define OFFSET_CASCADE_12 ((uint16_t)0x0060)
#define OFFSET_CASCADE_13 ((uint16_t)0x0068)
#define OFFSET_CASCADE_14 ((uint16_t)0x0070)
#define OFFSET_CASCADE_15 ((uint16_t)0x0078)
#define OFFSET_CASCADE_16 ((uint16_t)0x0080)
#define OFFSET_CASCADE_17 ((uint16_t)0x0088)
#define OFFSET_DATA_DISCRETE_IO ((uint16_t)0x0900)
#define OFFSET_DAC_CHANNEL_A ((uint16_t)0x0800)
#define OFFSET_DAC_CHANNEL_B ((uint16_t)0x0801)
#define OFFSET_DAC_CHANNEL_C ((uint16_t)0x0802)
#define OFFSET_DAC_CHANNEL_D ((uint16_t)0x0803)
#define OFFSET_ADC_0_CHANNEL_0 ((uint16_t)0x0D00)
#define OFFSET_ADC_0_CHANNEL_1 ((uint16_t)0x0D01)
#define OFFSET_ADC_0_CHANNEL_2 ((uint16_t)0x0D02)
#define OFFSET_ADC_0_CHANNEL_3 ((uint16_t)0x0D03)
#define OFFSET_ADC_0_CHANNEL_4 ((uint16_t)0x0D04)
#define OFFSET_ADC_0_CHANNEL_5 ((uint16_t)0x0D05)
#define OFFSET_ADC_1_CHANNEL_0 ((uint16_t)0x0E05)
#define OFFSET_ADC_1_CHANNEL_1 ((uint16_t)0x0E06)
#define OFFSET_ADC_1_CHANNEL_2 ((uint16_t)0x0E07)
#define OFFSET_ADC_1_CHANNEL_3 ((uint16_t)0x0E08)
#define OFFSET_ADC_1_CHANNEL_4 ((uint16_t)0x0E09)
#define OFFSET_ADC_1_CHANNEL_5 ((uint16_t)0x0E0A)
#define OFFSET_ADC_2_CHANNEL_0 ((uint16_t)0x0F0A)
#define OFFSET_ADC_2_CHANNEL_1 ((uint16_t)0x0F0B)
#define OFFSET_ADC_2_CHANNEL_2 ((uint16_t)0x0F0C)
#define OFFSET_ADC_2_CHANNEL_3 ((uint16_t)0x0F0D)
#define OFFSET_ADC_2_CHANNEL_4 ((uint16_t)0x0F0E)
#define OFFSET_ADC_2_CHANNEL_5 ((uint16_t)0x0F0F)
#endif /* PERIPHERY_PERIPHERYMAP_H_ */

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RUDRIVEFRAMEWORK/HeaderRUDRIVEFRAMEWORK.h
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/*
* HeaderRUDRIVEFRAMEWORK.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#ifndef RUDRIVEFRAMEWORK_HEADERRUDRIVEFRAMEWORK_H_
#define RUDRIVEFRAMEWORK_HEADERRUDRIVEFRAMEWORK_H_
#include "DSP28335/CPUBase.h"
#include "DSP28335/ADC.h"
// #include "DSP28335/CANBUS.h"
#include "DSP28335/CPU.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/CPUTimers.h"
#include "DSP28335/DiscreteOutputs.h"
#include "DSP28335/ECANA.h"
#include "DSP28335/ECANB.h"
#include "DSP28335/EPWM.h"
#include "DSP28335/EQEP1.h"
#include "DSP28335/FLASH.h"
#include "DSP28335/GPIO.h"
#include "DSP28335/MeasureTimeInterval.h"
#include "DSP28335/MeasureTimePeriod.h"
#include "DSP28335/MemoryZone.h"
#include "DSP28335/MemoryZone0.h"
#include "DSP28335/MemoryZone7.h"
#include "DSP28335/SCIA.h"
#include "DSP28335/SCIB.h"
#include "DSP28335/SCIBase.h"
#include "DSP28335/SCIC.h"
#include "DSP28335/SPIBase.h"
#include "DSP28335/SPIA.h"
#include "DSP28335/XINTF.h"
// #include "INTERFACE/CANBUSDataStructures.h"
// #include "INTERFACE/CANOPENParameters.h"
// #include "INTERFACE/CANOpenServer.h"
// #include "INTERFACE/DatabaseConfiguration.h"
// #include "INTERFACE/SDO.h"
#include "MODBUSRTU/ModbusRTUCRC.h"
#include "MODBUSRTU/ModbusRTUDefines.h"
#include "MODBUSRTU/ModbusRTUTransceiver.h"
#include "MODBUSRTU/ModbusRTUVariant.h"
#include "MODBUSRTU/ModbusRTUTransceiverBase.h"
#include "PERIPHERY/DigitalIO.h"
#include "PERIPHERY/ExtADC.h"
#include "PERIPHERY/ExtDAC.h"
#include "PERIPHERY/FRAMInterface.h"
#include "PERIPHERY/IIIPeriphery.h"
#include "PERIPHERY/IPeriphery.h"
#include "PERIPHERY/Periphery.h"
#include "PERIPHERY/PeripheryMap.h"
#include "PERIPHERY/PWMABCInterace.h"
#include "PERIPHERY/PWMInterface.h"
#include "PERIPHERY/PWMSInterace.h"
// #include "PERIPHERY/COMMBoard.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/PhaseBase.h"
#include "RUDRIVEFRAMEWORK/MultiPhaseDafaults.h"
#include "RUDRIVEFRAMEWORK/SinglePhaseDefaults.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#include "RUDRIVEFRAMEWORK/MultiPhase.h"
#include "RUDRIVEFRAMEWORK/SinglePhase.h"
#endif /* RUDRIVEFRAMEWORK_HEADERRUDRIVEFRAMEWORK_H_ */

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RUDRIVEFRAMEWORK/MultiPhase.cpp
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/*
* MultiPhase.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "RUDRIVEFRAMEWORK/MultiPhase.h"
namespace RUDRIVEFRAMEWORK
{
//CONSTRUCTOR
MultiPhase::MultiPhase(uint16_t *memzone):
PhaseBase(memzone),
periphery(),
crc(),
modbus_port(cpu.scib, cpu.interval_measure, crc)
{}//CONSTRUCTOR
void MultiPhase::setup(MultiPhaseSetup& setup)
{
cpu.setup(setup.cpu);
periphery.setup(m_memzone);
modbus_port.setup(setup.modbus);
//
}//
//
void MultiPhase::get_hard_code_setup(MultiPhaseSetup& hsetup)
{
cpu.get_hard_code_setup(hsetup.cpu);
// hsetup.cpu.epwm.parameters.fpwm = MULTI_PHASE_PWM_FREQUENCY;
// hsetup.cpu.epwm.parameters.adc_soc_quantity = MULTI_PHASE_ADC_ISR_QUANTITY;
// hsetup.cpu.epwm.parameters.adc_soc_offset = MULTI_PHASE_ADC_ISR_OFFSET_RELATIVE;
//
periphery.get_hard_code_setup(hsetup.periphery);
//
hsetup.modbus.gpio_re_de_setup = &DSP28335::GPIO::gpio_scib_re_de_setup;
hsetup.modbus.gpio_driver_enable = &DSP28335::GPIO::gpio_scib_re_de_set;
hsetup.modbus.gpio_receiver_enable = &DSP28335::GPIO::gpio_scib_re_de_clear;
//
}//
//
} /* namespace RUDRIVEFRAMEWORK */

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RUDRIVEFRAMEWORK/MultiPhase.h
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/*
* MultiPhase.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "RUDRIVEFRAMEWORK/PhaseBase.h"
//#include "RUDRIVEFRAMEWORK/HeaderRUDRIVEFRAMEWORK.h"
#ifndef RUDRIVEFRAMEWORK_MULTIPHASE_H_
#define RUDRIVEFRAMEWORK_MULTIPHASE_H_
namespace RUDRIVEFRAMEWORK
{
struct MultiPhaseSetup
{
DSP28335::CPUSetup cpu;
PERIPHERY::IIIPeripherySetup periphery;
MODBUSRTU::ModbusRTUTransceiverSetup modbus;
MultiPhaseSetup():
cpu(),
periphery(),
modbus()
{}
};//MultiPhaseSetup
struct MultiPhaseConfiguration
{
DSP28335::SCIConfiguration scib;
DSP28335::SCIConfiguration scic;
DSP28335::EPWMConfiguration epwm;
MultiPhaseConfiguration():
scib(),
scic(),
epwm()
{}
};//MultiPhaseConfiguration
struct MultiPhasePWMConfiguration: public PERIPHERY::PWMABCInterfaceConfiguration
{
MultiPhasePWMConfiguration():
PWMABCInterfaceConfiguration()
{}
};//
class MultiPhase: public PhaseBase
{
public:
PERIPHERY::IIIPeriphery periphery;
MODBUSRTU::ModbusRTUCRC crc;
MODBUSRTU::ModbusRTUTransceiver modbus_port;
public:
MultiPhase(uint16_t *memzone);
public:
void setup(MultiPhaseSetup& setup);
public:
void get_hard_code_setup(MultiPhaseSetup& hsetup);
};
} /* namespace RUDRIVEFRAMEWORK */
#endif /* RUDRIVEFRAMEWORK_MULTIPHASE_H_ */

18
RUDRIVEFRAMEWORK/PhaseBase.cpp
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/*
* PhaseBase.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "RUDRIVEFRAMEWORK/PhaseBase.h"
namespace RUDRIVEFRAMEWORK
{
//CONSTRUCTOR
PhaseBase::PhaseBase(uint16_t *memzone):
m_memzone(memzone),
cpu()
{}//CONSTRUCTOR
} /* namespace RUDRIVEFRAMEWORK */

45
RUDRIVEFRAMEWORK/PhaseBase.h
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/*
* PhaseBase.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include "F28335/DSP28x_Project.h"
#include "F28335/DSP2833x_Examples.h"
#include "RUDRIVEFRAMEWORK/HeaderRUDRIVEFRAMEWORK.h"
#ifndef RUDRIVEFRAMEWORK_PHASEBASE_H_
#define RUDRIVEFRAMEWORK_PHASEBASE_H_
namespace RUDRIVEFRAMEWORK
{
class PhaseBase
{
protected:
uint16_t *m_memzone;
protected:
//float m_time_sample_adc;
//float m_pwm_frequency;
//uint16_t m_adc_isr_quantity;
//float m_adc_isr_offset_relative;
public:
DSP28335::CPU cpu;
public:
PhaseBase(uint16_t *memzone);
public:
//virtual float get_time_sample_adc() = 0;
//virtual float get_pwm_frequency() = 0;
//virtual uint16_t get_adc_isr_quantity() = 0;
//virtual float get_adc_isr_offset_relative() = 0;
};
} /* namespace RUDRIVEFRAMEWORK */
#endif /* RUDRIVEFRAMEWORK_PHASEBASE_H_ */

52
RUDRIVEFRAMEWORK/SinglePhase.cpp
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/*
* SinglePhase.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "RUDRIVEFRAMEWORK/SinglePhase.h"
// #include "PERIPHERY/CAN.h"
// #include "PERIPHERY/COMMBoard.h"
namespace RUDRIVEFRAMEWORK
{
//CONSTRUCTOR
SinglePhase::SinglePhase(uint16_t *memzone):
PhaseBase(memzone),
// periphery(),
crc(),
modbus_port(cpu.scib, cpu.interval_measure, crc)
// comm_board(canSpace::CANB)
{}//CONSTRUCTOR
void SinglePhase::setup(SinglePhaseSetup& setup)
{
cpu.setup(setup.cpu);
// periphery.setup(m_memzone);
modbus_port.setup(setup.modbus);
// comm_board.config();
//
}//
//
//
void SinglePhase::get_hard_code_setup(SinglePhaseSetup& hsetup)
{
cpu.get_hard_code_setup(hsetup.cpu);
// hsetup.cpu.epwm.parameters.fpwm = SINGLE_PHASE_PWM_FREQUENCY;
// hsetup.cpu.epwm.parameters.adc_soc_quantity = SINGLE_PHASE_ADC_ISR_QUANTITY;
// hsetup.cpu.epwm.parameters.adc_soc_offset = SINGLE_PHASE_ADC_ISR_OFFSET_RELATIVE;
//
// periphery.get_hard_code_setup(hsetup.periphery);
//
hsetup.modbus.gpio_re_de_setup = &DSP28335::GPIO::gpio_scib_re_de_setup;
hsetup.modbus.gpio_driver_enable = &DSP28335::GPIO::gpio_scib_re_de_set;
hsetup.modbus.gpio_receiver_enable = &DSP28335::GPIO::gpio_scib_re_de_clear;
//
}//
//
} /* namespace RUDRIVEFRAMEWORK */

75
RUDRIVEFRAMEWORK/SinglePhase.h
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/*
* SinglePhase.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
// #include "PERIPHERY/COMMBoard.h"
#include "RUDRIVEFRAMEWORK/PhaseBase.h"
//#include "RUDRIVEFRAMEWORK/HeaderRUDRIVEFRAMEWORK.h"
#ifndef RUDRIVEFRAMEWORK_SINGLEPHASE_H_
#define RUDRIVEFRAMEWORK_SINGLEPHASE_H_
void write_fram (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
namespace RUDRIVEFRAMEWORK
{
struct SinglePhaseSetup
{
DSP28335::CPUSetup cpu;
// PERIPHERY::IPeripherySetup periphery;
MODBUSRTU::ModbusRTUTransceiverSetup modbus;
SinglePhaseSetup():
cpu(),
// periphery(),
modbus()
{}
};//SinglePhaseSetup
struct SinglePhaseConfiguration
{
DSP28335::SCIConfiguration scib;
DSP28335::SCIConfiguration scic;
DSP28335::EPWMConfiguration epwm;
SinglePhaseConfiguration():
scib(),
scic(),
epwm()
{}
};//SinglePhaseConfiguration
struct SinglePhasePWMConfiguration: public PERIPHERY::PWMSInterfaceConfiguration
{
SinglePhasePWMConfiguration():
PWMSInterfaceConfiguration()
{}
};//
class SinglePhase: public RUDRIVEFRAMEWORK::PhaseBase
{
public:
// PERIPHERY::IPeriphery periphery;
MODBUSRTU::ModbusRTUCRC crc;
MODBUSRTU::ModbusRTUTransceiver modbus_port;
// PERIPHERY::COMMBoard comm_board;
public:
SinglePhase(uint16_t *memzone);
public:
void setup(SinglePhaseSetup& setup);
public:
void get_hard_code_setup(SinglePhaseSetup& hsetup);
};// SinglePhase
} /* namespace RUDRIVEFRAMEWORK */
#endif /* RUDRIVEFRAMEWORK_SINGLEPHASE_H_ */

39
RUDRIVEFRAMEWORK/SinglePhaseDefaults.h
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/*
* SinglePhaseDefaults.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#ifndef RUDRIVEFRAMEWORK_SINGLEPHASEDEFAULTS_H_
#define RUDRIVEFRAMEWORK_SINGLEPHASEDEFAULTS_H_
#define SINGLE_PHASE_PWM_FREQUENCY (float)500
#define SINGLE_PHASE_ADC_ISR_QUANTITY (uint16_t)2
#define SINGLE_PHASE_ADC_ISR_OFFSET_RELATIVE (float)FP_ZERO
#define SINGLE_PHASE_CASCADE_QUANTITY (uint16_t)1
#define SINGLE_PHASE_CELL_QUANTITY (uint16_t)1
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_00 (uint16_t)1
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_01 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_02 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_03 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_04 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_05 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_06 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_07 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_08 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_09 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_10 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_11 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_12 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_13 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_14 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_15 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_16 (uint16_t)0
#define SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_17 (uint16_t)0
#endif /* RUDRIVEFRAMEWORK_SINGLEPHASEDEFAULTS_H_ */

124
main2.cpp
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@ -12,12 +12,21 @@
// #include "Protocol/DigitalIO.h"
#include "Periphery.h"
#include "SinglePhaseDefaults.h"
#include "RUDRIVEFRAMEWORK/HeaderRUDRIVEFRAMEWORK.h"
#include "DSP28335/GPIO.h"
#include "DSP28335/SCIB.h"
#include "DSP28335/SCIBase.h"
#include "MODBUSRTU/ModbusRTUCRC.h"
#include "MODBUSRTU/ModbusRTUDefines.h"
#include "MODBUSRTU/ModbusRTUTransceiver.h"
#include "MODBUSRTU/ModbusRTUVariant.h"
#include "MODBUSRTU/ModbusRTUTransceiverBase.h"
#include "DSP28335/MeasureTimeInterval.h"
#include "WEINBUS/HeaderWeinbus.h"
#include "PERIPHERY/PWMSInterace.h"
//Functions declarations
@ -53,9 +62,6 @@ WEINBUS::REGISTER_32 test_hmi_float_reg_403 = WEINBUS::REGISTER_32(0);
WEINBUS::REGISTER_32 test_hmi_float_reg_404 = WEINBUS::REGISTER_32(0);
//<>
void modify_hardware_setup(RUDRIVEFRAMEWORK::SinglePhaseSetup& setup);
void hardcode_pwm_configuration(PERIPHERY::PWMSInterfaceConfiguration& config);
void test_init_hmi_buffers();
void clear_array(uint16_t *pointer, uint16_t sizearray);
//----------------------------------------------------------------------------------------
@ -155,7 +161,7 @@ void main()
modbus_port.setRXBuffer((uint16_t*)hmi.rxStack, &hmi.rxLength);
modbus_port.setTXBuffer((uint16_t*)hmi.txStack, &hmi.txLength);
// interval_measure.set_magic(19);
interval_measure.set_magic(19);
//----------------------------------------------------------------------------------------
@ -298,107 +304,3 @@ void clear_array(uint16_t *pointer, uint16_t sizearray)
}
//
}//
void modify_hardware_setup(RUDRIVEFRAMEWORK::SinglePhaseSetup& setup)
{
//
// SCIB - interface with monitor? RS485, MODBUS RTU
//
//setup.cpu.scib.config.baudrate = SCIB_BAUDRATE_DEFAULT;
//setup.cpu.scib.config.parity = SCIB_PARITY_DEFAULT;
//setup.cpu.scib.config.stopbits = SCIB_STOPBITS_DEFAULT;
//setup.cpu.scib.config.lenght = SCIB_LENGHT_DEFAULT;
//setup.cpu.scib.gpio_setup = SCIB_GPIO_SETUP_DEFAULT;
//
// SCIC - internal interface
//
//setup.cpu.scic.config.baudrate = SCIC_BAUDRATE_DEFAULT;
//setup.cpu.scic.config.parity = SCIC_PARITY_DEFAULT;
//setup.cpu.scic.config.stopbits = SCIC_STOPBITS_DEFAULT;
//setup.cpu.scic.config.lenght = SCIC_LENGHT_DEFAULT;
//setup.cpu.scic.gpio_setup = SCIC_GPIO_SETUP_DEFAULT;
//
// CPU Timers
//
//setup.cpu.cpu_timers.frequency = 150.0; //150MHz
//setup.cpu.cpu_timers.period = 1000.0; //1000us
//
// EPWM
//
// setup.cpu.epwm.parameters.fpwm = 750.0; //Hz
//setup.cpu.epwm.parameters.pulse_sync = 1.0e-6; //s
//setup.cpu.epwm.parameters.pulse_adc_soc = 32.0e-6; //s
//setup.cpu.epwm.parameters.adc_soc_offset = FP_ZERO; //relative
// setup.cpu.epwm.parameters.adc_soc_quantity = 3;
//setup.cpu.epwm.gpio_setup = &DSP28335::GPIO::gpio_epwm_setup;
//
// XINTF
//
//setup.cpu.xintf.gpio_setup = &DSP28335::GPIO::gpio_xintf_16bit_setup;
//
// ECANA
//
//setup.cpu.ecana.gpio_setup = &DSP28335::GPIO::gpio_cana_setup;
//
// ECANB
//
//setup.cpu.ecanb.gpio_setup = &DSP28335::GPIO::gpio_canb_setup;
//
// EQEP
//
//setup.cpu.eqep1.gpio_setup = &DSP28335::GPIO::gpio_eqep_setup;
//
// Discrete Outputs
//
//setup.cpu.dout.gpio_setup = &DSP28335::GPIO::gpio_dicrete_outputs_setup;
//
// Analog Faults
//
//setup.periphery.analog_faults.p_gpio_analog_fault_setup = &DSP28335::GPIO::gpio_analog_fault_setup;
//setup.periphery.analog_faults.p_analog_fault_read = &DSP28335::GPIO::gpio_analog_fault_read;
}//
void hardcode_pwm_configuration(PERIPHERY::PWMSInterfaceConfiguration& config)
{
config.pwm_frequency = SINGLE_PHASE_PWM_FREQUENCY;
config.adc_isr_quantity = SINGLE_PHASE_ADC_ISR_QUANTITY;
config.adc_isr_offset_relative = SINGLE_PHASE_ADC_ISR_OFFSET_RELATIVE;
config.cascade_quantity = SINGLE_PHASE_CASCADE_QUANTITY;
config.cell_quantity = SINGLE_PHASE_CELL_QUANTITY;
config.cell_quantity_in_cascade[0] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_00;
config.cell_quantity_in_cascade[1] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_01;
config.cell_quantity_in_cascade[2] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_02;
config.cell_quantity_in_cascade[3] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_03;
config.cell_quantity_in_cascade[4] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_04;
config.cell_quantity_in_cascade[5] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_05;
config.cell_quantity_in_cascade[6] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_06;
config.cell_quantity_in_cascade[7] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_07;
config.cell_quantity_in_cascade[8] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_08;
config.cell_quantity_in_cascade[9] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_09;
config.cell_quantity_in_cascade[10] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_10;
config.cell_quantity_in_cascade[11] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_11;
config.cell_quantity_in_cascade[12] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_12;
config.cell_quantity_in_cascade[13] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_13;
config.cell_quantity_in_cascade[14] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_14;
config.cell_quantity_in_cascade[15] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_15;
config.cell_quantity_in_cascade[16] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_16;
config.cell_quantity_in_cascade[17] = SINGLE_PHASE_CELL_QANTITY_IN_CASCADE_17;
//
}//
//

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