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Modbus still working here

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feature/Modbus
Oleg 4 weeks ago
parent 5f28745064
commit a0fef5214d
156 changed files with 21874 additions and 4 deletions
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187
DSP28335/ADC.cpp
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/*
* ADC.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/ADC.h"
namespace DSP28335
{
//CONSTRUCTOR
ADC::ADC():
DSP28335::CPUBase(),
m_status(false)
//
{}//end CONSTRUCTOR
//
void DSP28335::ADC::setup()
{
if(m_mode == DSP28335::ADC::UNDEFINED)
{
//--- Configure the other ADC registers
AdcRegs.ADCREFSEL.bit.REF_SEL = 0; // ADC reference, 0=internal, 1=external
//--- Power-up the ADC
//AdcRegs.ADCTRL3.all = 0x00EC; // Power-up reference and main ADC
//AdcRegs.ADCTRL3.all = 0x00F4; // Power-up reference and main ADC /20
//AdcRegs.ADCTRL3.all = 0x00EE; // Power-up reference and main ADC /14
//AdcRegs.ADCTRL3.all = 0x00EA; // Power-up reference and main ADC /10
//AdcRegs.ADCTRL3.all = 0x00E8; // Power-up reference and main ADC /8
//AdcRegs.ADCTRL3.all = 0x00E4; // Power-up reference and main ADC /4
// bit 15-8 0's: reserved
// bit 7-6 11: ADCBGRFDN, reference power, 00=off, 11=on
// bit 5 1: ADCPWDN, main ADC power, 0=off, 1=on
// bit 4-1 0110: ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
// bit 0 0: SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling
AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x0008; // bit 4-1 0110: ADCCLKPS, clock prescaler, FCLK=HSPCLK/(2*ADCCLKPS)
AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x0000; // bit 0 0: SMODE_SEL, 0=sequential sampling, 1=simultaneous sampling
AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x0003; // bit 7-6 11: ADCBGRFDN, reference power, 00=off, 11=on
AdcRegs.ADCTRL3.bit.ADCPWDN = 0x0001; // bit 5 1: ADCPWDN, main ADC power, 0=off, 1=on
DELAY_US(5000); // Wait 5 ms before using the ADC
//AdcRegs.ADCTRL1.all = 0x0710;
// bit 15 0: reserved
// bit 14 0: RESET, 0=no action, 1=reset ADC
// bit 13-12 00: SUSMOD, 00=ignore emulation suspend
// bit 11-8 0111: ACQ_PS (Acquisition), 0111 = 8 x ADCCLK
// bit 7 0: CPS (Core clock), 0: ADCCLK=FCLK/1, 1: ADCCLK=FCLK/2
// bit 6 0: CONT_RUN, 0=start/stop mode, 1=continuous run
// bit 5 0: SEQ_OVRD, 0=disabled, 1=enabled
// bit 4 1: SEQ_CASC, 0=dual sequencer, 1=cascaded sequencer
// bit 3-0 0000: reserved
AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Cascaded mode
AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0; // Disable Sequencer override
AdcRegs.ADCTRL1.bit.CONT_RUN = 0x0; // Start-stop mode
AdcRegs.ADCTRL1.bit.CPS = 0x0; // Core Clock Prescaler = 1 (ADCCLK=Fclk/1)
AdcRegs.ADCTRL1.bit.ACQ_PS = 0x2; // Acqusition window size
AdcRegs.ADCTRL1.bit.SUSMOD = 0x0; // Emulation-suspend mode
//AdcRegs.ADCTRL2.all = 0x0900;
// bit 15 0: ePWM_SOCB_SEQ, 0=no action
// bit 14 0: RST_SEQ1, 0=no action
// bit 13 0: SOC_SEQ1, 0=clear any pending SOCs
// bit 12 0: reserved
// bit 11 1: INT_ENA_SEQ1, 1=enable interrupt
// bit 10 0: INT_MOD_SEQ1, 0=int on every SEQ1 conv
// bit 9 0: reserved
// bit 8 1: ePWM_SOCA_SEQ1, 1=SEQ1 start from ePWM_SOCA trigger
// bit 7 0: EXT_SOC_SEQ1, 1=SEQ1 start from ADCSOC pin
// bit 6 0: RST_SEQ2, 0=no action
// bit 5 0: SOC_SEQ2, no effect in cascaded mode
// bit 4 0: reserved
// bit 3 0: INT_ENA_SEQ2, 0=int disabled
// bit 2 0: INT_MOD_SEQ2, 0=int on every other SEQ2 conv
// bit 1 0: reserved
// bit 0 0: ePWM_SOCB_SEQ2, 0=no action
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ2 = 0x0; // ePWM SOCB enable bit for SEQ2
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ2 = 0x0; // SEQ2 interrupt mode
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ2 = 0x0; // SEQ2 interrupt enable
AdcRegs.ADCTRL2.bit.SOC_SEQ2 = 0x0; // SOC SEQ2
AdcRegs.ADCTRL2.bit.RST_SEQ2 = 0x0; // Reset SEQ2
AdcRegs.ADCTRL2.bit.EXT_SOC_SEQ1 = 0x0; // external SOC SEQ1
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 0x0; // ePWM SOCB enable bit for SEQ1
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0x0; // SEQ1 interrupt mode
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; // SEQ1 interrupt enable
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0x0; // SOC SEQ1
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1; // Reset SEQ1
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ = 0x0; // ePWM SOCB enable for cascaded sequencer
AdcRegs.ADCMAXCONV.all = 15;
// bit 15-7 0's: reserved
// bit 6-4 000: MAX_CONV2 value
// bit 3-0 0000: MAX_CONV1 value (0 means 1 conversion)
// Since we are only doing 1 conversion in the sequence, we only need to
// configure the ADCCHSELSEQ1 register, and only the CONV00 field. All
// other channel selection fields are don't cares in this example.
//AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0; // Convert Channel 0
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA3 as 1st SEQ conv.
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup ADCINA2 as 2nd SEQ conv.
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup ADCINA2 as 3nd SEQ conv.
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup ADCINA2 as 4nd SEQ conv.
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Setup ADCINA3 as 5st SEQ conv.
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Setup ADCINA2 as 6nd SEQ conv.
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Setup ADCINA2 as 7nd SEQ conv.
AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; // Setup ADCINA2 as 8nd SEQ conv.
AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8; // Setup ADCINA3 as 9st SEQ conv.
AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9; // Setup ADCINA2 as 10nd SEQ conv.
AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xA; // Setup ADCINA2 as 11nd SEQ conv.
AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xB; // Setup ADCINA2 as 12nd SEQ conv.
AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xC; // Setup ADCINA3 as 13st SEQ conv.
AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xD; // Setup ADCINA2 as 14nd SEQ conv.
AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0xE; // Setup ADCINA2 as 15nd SEQ conv.
AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0xF; // Setup ADCINA2 as 16nd SEQ conv.
//
//
//
m_mode = DSP28335::ADC::OPERATIONAL;
//
}//end if
//
}//end
//.TI.ramfunc
// #pragma CODE_SECTION("ramfuncs");
bool DSP28335::ADC::is_ready()
{
return m_status;
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::clear_status()
{
m_status = false;
//
}//end
// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::sw_soc_seq1()
{
if(m_mode == DSP28335::ADC::OPERATIONAL)
{
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;
//
}//if
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::sw_soc_seq2()
{
if(m_mode == DSP28335::ADC::OPERATIONAL)
{
AdcRegs.ADCTRL2.bit.SOC_SEQ2 = 1;
//
}//if
//
}//end
// #pragma CODE_SECTION("ramfuncs");
void DSP28335::ADC::interrupt_ack()
{
m_status = true;
//AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
//PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
// Reinitialize for next ADC sequence
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
//
}//end
//
} /* namespace DSP28335 */

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DSP28335/ADC.h
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/*
* ADC.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#ifndef DSP28335_ADC_H_
#define DSP28335_ADC_H_
namespace DSP28335
{
class ADC: public DSP28335::CPUBase
{
private:
bool m_status;
public:
ADC();
void setup();
public:
bool is_ready();
void clear_status();
public:
void sw_soc_seq1();
void sw_soc_seq2();
public:
void interrupt_ack();
//
};
} /* namespace DSP28335 */
#endif /* DSP28335_ADC_H_ */

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DSP28335/CPU.cpp
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/*
* CPUCore.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/CPU.h"
namespace DSP28335
{
//CONSTRUCTOR
CPU::CPU():
DSP28335::CPUBase(),
scib(ScibRegs),
// scic(ScicRegs),
// cpu_timers(CpuTimer0),
// epwm(),
// ecana(),
// ecanb(),
// eqep1(),
// period_measure(DSP28335::MeasureTimePeriod(CpuTimer2)),
interval_measure(DSP28335::MeasureTimeInterval(CpuTimer1)),
// xintf(),
// dout(),
// m_counter_startup(0),
// m_counter_sync(0),
_execute(&CPU::_execute_undef)
//
{}//end CONSTRUCTOR
void CPU::setup(DSP28335::CPUSetup& setup)
{
//adc.setup();
//
//
scib.setup(setup.scib);
//
// scic.setup(setup.scic);
//
// cpu_timers.setup(setup.timers);
//
// epwm.setup(setup.epwm);
//
// xintf.setup(setup.xintf);
//
// period_measure.set_magic((Uint32)0);
// period_measure.reset();
//
interval_measure.set_magic((Uint32)0);
interval_measure.reset();
//
// ecana.setup(setup.ecana);
// //
// ecanb.setup(setup.ecanb);
// eqep1.setup(setup.eqep1);
// dout.setup(setup.dout);
// m_counter_startup = setup.startup_period;
// m_counter_sync = setup.period_sync;
if(//adc.compare(DSP28335::ADC::OPERATIONAL) &&
//scib.compare(DSP28335::SCIB::OPERATIONAL) &&
//scic.compare(DSP28335::SCIC::OPERATIONAL) &&
// cpu_timers.compare(DSP28335::CPUTimers::OPERATIONAL) // &&
// epwm.compare(DSP28335::EPWM::OPERATIONAL) &&
// xintf.compare(DSP28335::XINTF::OPERATIONAL) &&
// ecana.compare(DSP28335::ECANA::OPERATIONAL) &&
// ecanb.compare(DSP28335::ECANB::OPERATIONAL) &&
// eqep1.compare(DSP28335::EQEP1::OPERATIONAL) &&
// dout.compare(DSP28335::DiscreteOutputs::OPERATIONAL)
true)
{
m_mode = DSP28335::CPUBase::OPERATIONAL;
//_execute = &CPUCore::_execute_mode_i;
//_execute = &CPUCore::_execute_mode_500HZ;
_execute = &CPU::_execute_undef;
// epwm.set_actions();
//
}//if
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void CPU::execute()
{
(this->*_execute)();
//
}//
//
void CPU::_execute_undef()
{}//
//
// #pragma CODE_SECTION("ramfuncs");
void CPU::_execute_mode_i()
{
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void CPU::_execute_mode_ii()
{
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void CPU::_execute_mode_iii()
{}//
//
//
} /* namespace DSP28335 */

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DSP28335/CPU.h
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/*
* SYSCore.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/ADC.h"
#include "DSP28335/CPUTimers.h"
#include "DSP28335/DiscreteOutputs.h"
#include "DSP28335/ECANA.h"
#include "DSP28335/ECANB.h"
#include "DSP28335/EPWM.h"
#include "DSP28335/EQEP1.h"
#include "DSP28335/GPIO.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/MeasureTimeInterval.h"
#include "DSP28335/MeasureTimePeriod.h"
#include "DSP28335/MemoryZone.h"
#include "DSP28335/MemoryZone0.h"
#include "DSP28335/MemoryZone7.h"
#include "DSP28335/SCIA.h"
#include "DSP28335/SCIB.h"
#include "DSP28335/SCIBase.h"
#include "DSP28335/SCIC.h"
#include "DSP28335/SPIBase.h"
#include "DSP28335/SPIA.h"
#include "DSP28335/XINTF.h"
#ifndef DSP28335_CPUCORE_H_
#define DSP28335_CPUCORE_H_
namespace DSP28335
{
struct CPUSetup
{
DSP28335::SCISetup scib;
DSP28335::SCISetup scic;
DSP28335::CPUTimersSetup timers;
DSP28335::EPWMSetup epwm;
DSP28335::XINTFSetup xintf;
// DSP28335::ECANASetup ecana;
// DSP28335::ECANBSetup ecanb;
// DSP28335::EQEP1Setup eqep1;
// DSP28335::DiscreteOutputsSetup dout;
// Uint16 period_sync;
// Uint16 startup_period;
CPUSetup():
scib(),
scic(),
timers(),
epwm(),
xintf()
// ecana(),
// ecanb(),
// eqep1(),
// dout(),
// period_sync(0),
// startup_period(0)
{}
};//end SYSCoreSetup
struct CPUConfiguration
{
DSP28335::SCIConfiguration scib;
DSP28335::SCIConfiguration scic;
DSP28335::EPWMConfiguration epwm;
CPUConfiguration():
scib(),
scic(),
epwm()
{}
};//CPUConfiguration
class CPU: public DSP28335::CPUBase
{
public:
// DSP28335::GPIO gpio;
DSP28335::SCIB scib;
// DSP28335::SCIC scic;
// DSP28335::CPUTimers cpu_timers;
// DSP28335::EPWM epwm;
// DSP28335::MeasureTimePeriod period_measure;
DSP28335::MeasureTimeInterval interval_measure;
// DSP28335::XINTF xintf;
// DSP28335::ECANA ecana;
// DSP28335::ECANB ecanb;
// DSP28335::EQEP1 eqep1;
// DSP28335::DiscreteOutputs dout;
private:
// Uint16 m_counter_startup;
// Uint16 m_counter_sync;
public:
CPU();
public:
void setup(DSP28335::CPUSetup& setup);
void get_hard_code_setup(DSP28335::CPUSetup& hsetup);
public:
void execute();
private:
void (CPU::*_execute)();
void _execute_undef();
void _execute_mode_i();
void _execute_mode_ii();
void _execute_mode_iii();
//
};// CPU
} /* namespace DSP28335 */
#endif /* DSP28335_CPUCORE_H_ */

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DSP28335/CPUBase.cpp
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/*
* CPUBase.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/CPUBase.h"
namespace DSP28335
{
//CONSTRUCTOR
CPUBase::CPUBase():
m_mode(DSP28335::CPUBase::UNDEFINED),
m_status(false)
//
{}//end CONSTRUCTOR
//
DSP28335::CPUBase::mode_t DSP28335::CPUBase::get_mode() const
{
return m_mode;
//
}//end
//
bool DSP28335::CPUBase::compare(DSP28335::CPUBase::mode_t mode) const
{
return m_mode == mode;
//
}//end
//
} /* namespace DSP28335 */

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DSP28335/CPUBase.h
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/*
* CPUBase.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
//
#include "F28335/DSP28x_Project.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef DSP28335_CPUBase_H_
#define DSP28335_CPUBase_H_
namespace DSP28335
{
struct CPUBaseSetup
{
pGPIO_FUNCTION gpio_setup;
CPUBaseSetup():
gpio_setup(0)
{}
};//CPUBaseSetup
class CPUBase
{
public:
enum mode_t {UNDEFINED=0, OPERATIONAL=1};
protected:
mode_t m_mode;
bool m_status;
public:
CPUBase();
public:
mode_t get_mode() const;
bool compare(mode_t mode) const;
//
};// class
} /* namespace DSP28335 */
#endif /* DSP28335_CPUBase_H_ */

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DSP28335/CPUCoreHardCodeSetup.cpp
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/*
* SYSCoreHardCodeSetup.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/CPU.h"
namespace DSP28335
{
void DSP28335::CPU::get_hard_code_setup(DSP28335::CPUSetup& hsetup)
{
// At startup number synchronization pwm's periods
// hsetup.startup_period = 20;
// // // synchronization every pwm's cycle
// hsetup.period_sync = 5;
//
// SCIB - interface with monitor? RS485, MODBUS RTU
//
hsetup.scib.config.baudrate = SCIB_BAUDRATE_DEFAULT;
hsetup.scib.config.parity = SCIB_PARITY_DEFAULT;
hsetup.scib.config.stopbits = SCIB_STOPBITS_DEFAULT;
hsetup.scib.config.lenght = SCIB_LENGHT_DEFAULT;
hsetup.scib.gpio_setup = SCIB_GPIO_SETUP_DEFAULT;
//
// SCIC - internal interface
//
// hsetup.scic.config.baudrate = SCIC_BAUDRATE_DEFAULT;
// hsetup.scic.config.parity = SCIC_PARITY_DEFAULT;
// hsetup.scic.config.stopbits = SCIC_STOPBITS_DEFAULT;
// hsetup.scic.config.lenght = SCIC_LENGHT_DEFAULT;
// hsetup.scic.gpio_setup = SCIC_GPIO_SETUP_DEFAULT;
//
// CPU Timers
//
// hsetup.timers.frequency = 150.0; //150MHz
// hsetup.timers.period = 1000.0; //1000us
//
// EPWM
//
// hsetup.epwm.parameters.fpwm = 500; //Hz
// hsetup.epwm.parameters.pulse_sync = 1.0e-6; //s
// hsetup.epwm.parameters.pulse_adc_soc = 32.0e-6; //s
// hsetup.epwm.parameters.adc_soc_offset = FP_ZERO; //relative
// hsetup.epwm.parameters.adc_soc_quantity = 2;
// hsetup.epwm.gpio_setup = &DSP28335::GPIO::gpio_epwm_setup;
//
// XINTF
//
// hsetup.xintf.gpio_setup = &DSP28335::GPIO::gpio_xintf_16bit_setup;
//
// ECANA
//
// hsetup.ecana.gpio_setup = &DSP28335::GPIO::gpio_cana_setup;
//
// ECANB
//
// hsetup.ecanb.gpio_setup = &DSP28335::GPIO::gpio_canb_setup;
//
// EQEP
//
// hsetup.eqep1.gpio_setup = &DSP28335::GPIO::gpio_eqep_setup;
//
// Discrete Outputs
//
// hsetup.dout.gpio_setup = &DSP28335::GPIO::gpio_dicrete_outputs_setup;
//
}//end
} /* namespace DSP28335 */

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DSP28335/CPUTimers.cpp
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/*
* CPUTimers.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/CPUTimers.h"
namespace DSP28335
{
//CONSTRUCTOR
CPUTimers::CPUTimers(CPUTIMER_VARS& CPUTimer):
DSP28335::CPUBase(),
CPUTimer(CPUTimer)
//
{}//end CONSTRUCTOR
void CPUTimers::setup(const CPUTimersSetup& setup)
{
if(m_mode == DSP28335::CPUBase::UNDEFINED)
{
InitCpuTimers();
ConfigCpuTimer(&CPUTimer, setup.frequency, setup.period); // 1ms
//
m_mode = DSP28335::CPUBase::OPERATIONAL;
//
}//end if
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void CPUTimers::start()
{
//
CPUTimer.RegsAddr->TCR.bit.TSS = 0;
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void CPUTimers::interrupt_ack()
{
// Acknowledge this interrupt to receive more interrupts from group 1
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;
//
}//end
//
} /* namespace DSP28335 */

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DSP28335/CPUTimers.h
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/*
* CPUTimers.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#ifndef DSP28335_CPUTIMERS_H_
#define DSP28335_CPUTIMERS_H_
namespace DSP28335
{
struct CPUTimersSetup
{
float frequency;
float period;
CPUTimersSetup():
frequency(150.0),
period(1000.0)
{}
};//end CPUTimersSetup
class CPUTimers: public DSP28335::CPUBase
{
public:
CPUTIMER_VARS& CPUTimer;
public:
CPUTimers(CPUTIMER_VARS& CPUTimer);
void setup(const CPUTimersSetup& setup);
public:
void start();
void interrupt_ack();
//
};//end class CPUTimers
} /* namespace DSP28335 */
#endif /* DSP28335_CPUTIMERS_H_ */

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DSP28335/DiscreteOutputs.cpp
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/*
* DiscreteOutputs.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/DiscreteOutputs.h"
namespace DSP28335
{
//CONSTRUCTOR
DiscreteOutputs::DiscreteOutputs():
DSP28335::CPUBase(),
_gpio_setup(&DSP28335::GPIO::gpio_dicrete_outputs_setup)
{}//CONSTRUCTOR
void DiscreteOutputs::setup(const DiscreteOutputsSetup& setup)
{
if(m_mode == DSP28335::DiscreteOutputs::UNDEFINED)
{
if(setup.gpio_setup != 0)
{
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
m_mode = DSP28335::DiscreteOutputs::OPERATIONAL;
//
}//if
//
}//if
//
//
}//
} /* namespace DSP28335 */

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DSP28335/DiscreteOutputs.h
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/*
* DiscreteOutputs.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/GPIO.h"
#ifndef DSP28335_DISCRETEOUTPUTS_H_
#define DSP28335_DISCRETEOUTPUTS_H_
namespace DSP28335
{
struct DiscreteOutputsSetup: public DSP28335::CPUBaseSetup
{
DiscreteOutputsSetup():
DSP28335::CPUBaseSetup()
{}
};//
class DiscreteOutputs: public DSP28335::CPUBase
{
public:
DiscreteOutputs();
void setup(const DiscreteOutputsSetup& setup);
private:
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_DISCRETEOUTPUTS_H_ */

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DSP28335/ECANA.cpp
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/*
* ECANA.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/ECANA.h"
namespace DSP28335
{
//CONSTRUCTOR
ECANA::ECANA():
CPUBase(),
_gpio_setup(&DSP28335::GPIO::gpio_cana_setup)
{}//CONSTRUCTOR
void ECANA::setup(const ECANASetup& setup)
{
if(m_mode == DSP28335::ECANA::UNDEFINED)
{
InitECana();
if(setup.gpio_setup != 0)
{
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
m_mode = DSP28335::ECANA::OPERATIONAL;
//
}//if
//
}//if
//
}//
} /* namespace DSP28335 */

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DSP28335/ECANA.h
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/*
* ECANA.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/GPIO.h"
#ifndef DSP28335_ECANA_H_
#define DSP28335_ECANA_H_
namespace DSP28335
{
struct ECANASetup: public DSP28335::CPUBaseSetup
{
ECANASetup():
DSP28335::CPUBaseSetup()
{}
};//ECANASetup
class ECANA: public DSP28335::CPUBase
{
public:
ECANA();
void setup(const ECANASetup& setup);
private:
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_ECANA_H_ */

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DSP28335/ECANB.cpp
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/*
* ECANB.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/ECANB.h"
namespace DSP28335
{
//CONSTRUCTOR
ECANB::ECANB():
CPUBase(),
_gpio_setup(&DSP28335::GPIO::gpio_canb_setup)
{}//CONSTRUCTOR
void ECANB::setup(const ECANBSetup& setup)
{
if(m_mode == DSP28335::ECANB::UNDEFINED)
{
InitECanb();
if(setup.gpio_setup != 0)
{
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
m_mode = DSP28335::ECANB::OPERATIONAL;
//
}//if
//
}//if
//
}//
} /* namespace DSP28335 */

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DSP28335/ECANB.h
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/*
* ECANB.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/GPIO.h"
#ifndef CPU_ECANB_H_
#define CPU_ECANB_H_
namespace DSP28335
{
struct ECANBSetup: public DSP28335::CPUBaseSetup
{
ECANBSetup():
DSP28335::CPUBaseSetup()
{}
};//ECANBSetup
class ECANB: public CPUBase
{
public:
ECANB();
void setup(const ECANBSetup& setup);
private:
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* CPU_ECANB_H_ */

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DSP28335/EPWM.cpp
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/*
* EPWM.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/EPWM.h"
namespace DSP28335
{
//CONSTRUCTOR
EPWMConfigModificator::EPWMConfigModificator():
m_config(),
modify(true)
{}//CONSTRUCTOR
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_config(EPWMConfiguration& refconfig)
{
if(m_config.fpwm != refconfig.fpwm)
{
m_config.fpwm = refconfig.fpwm;
modify = true;
}//
if(m_config.pulse_sync != refconfig.pulse_sync)
{
m_config.pulse_sync = refconfig.pulse_sync;
modify = true;
}//
if(m_config.pulse_adc_soc != refconfig.pulse_adc_soc)
{
m_config.pulse_adc_soc = refconfig.pulse_adc_soc;
modify = true;
}//
//
if(m_config.adc_soc_offset != refconfig.adc_soc_offset)
{
m_config.adc_soc_offset = refconfig.adc_soc_offset;
modify = true;
}//
//
if(m_config.adc_soc_quantity != refconfig.adc_soc_quantity)
{
m_config.adc_soc_quantity = refconfig.adc_soc_quantity;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
EPWMConfiguration EPWMConfigModificator::get_config()
{
return m_config;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::reset()
{
modify = false;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_pwm_frquency(float fpwm)
{
if(m_config.fpwm != fpwm)
{
m_config.fpwm = fpwm;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_pulse_sync(float pulse_sync)
{
if(m_config.pulse_sync != pulse_sync)
{
m_config.pulse_sync = pulse_sync;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_pulse_adc_soc(float pulse_adc_soc)
{
if(m_config.pulse_adc_soc != pulse_adc_soc)
{
m_config.pulse_adc_soc = pulse_adc_soc;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_adc_soc_offset(float adc_soc_offset)
{
if(m_config.adc_soc_offset != adc_soc_offset)
{
m_config.adc_soc_offset = adc_soc_offset;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWMConfigModificator::set_adc_soc_quantity(Uint16 adc_soc_quantity)
{
if(m_config.adc_soc_quantity != adc_soc_quantity)
{
m_config.adc_soc_quantity = adc_soc_quantity;
modify = true;
}//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_pwm_frquency()
{
return m_config.fpwm;
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_pulse_sync()
{
return m_config.pulse_sync;
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_pulse_adc_soc()
{
return m_config.pulse_adc_soc;
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWMConfigModificator::get_adc_soc_offset()
{
return m_config.adc_soc_offset;
}//
//
// #pragma CODE_SECTION("ramfuncs");
Uint16 EPWMConfigModificator::get_adc_soc_quantity()
{
return m_config.adc_soc_quantity;
}//
//
//CONSTRUCTOR
EPWM::EPWM():
DSP28335::CPUBase(),
m_configuration_current(),
m_configuration_new(),
m_fcpu(150.0e6),
m_timer_period(FP_ZERO),
m_timer_step(FP_ZERO),
m_time_sample_adc(FP_ZERO),
m_clock_prescale_list(),
m_high_speed_clock_prescale(),
m_tbprd(FP_ZERO),
m_clkdiv(0),
m_hspclkdiv(0),
m_cmpr_sync(0),
m_cmpr_adc_offset(0),
m_cmpr_adc_start(0),
m_cmpr_adc_stop(0),
m_cmpr_adc_width(0),
m_cmpr_adc_step(0),
m_adc_soc_quantity(0),
m_adc_soc_counter(0),
_epwm2_adc_drive(0),
status(),
_gpio_setup(0)
//
{
m_clock_prescale_list[0] = 1.0;
m_clock_prescale_list[1] = 2.0;
m_clock_prescale_list[2] = 4.0;
m_clock_prescale_list[3] = 8.0;
m_clock_prescale_list[4] = 16.0;
m_clock_prescale_list[5] = 32.0;
m_clock_prescale_list[6] = 64.0;
m_clock_prescale_list[7] = 128.0;
//
m_high_speed_clock_prescale[0] = 1.0;
m_high_speed_clock_prescale[1] = 2.0;
m_high_speed_clock_prescale[2] = 4.0;
m_high_speed_clock_prescale[3] = 6.0;
m_high_speed_clock_prescale[4] = 8.0;
m_high_speed_clock_prescale[5] = 10.0;
m_high_speed_clock_prescale[6] = 12.0;
m_high_speed_clock_prescale[7] = 14.0;
//
}//end CONSTRUCTOR
void EPWM::setup(const EPWMSetup& setup)
{
m_status = true;
//m_status &= m_mode == DSP28335::EPWM::UNDEFINED ? true : false;
m_status &= setup.parameters.fpwm > (float)(5.0) ? true : false;
m_status &= setup.parameters.pulse_sync != FP_ZERO ? true : false;
m_status &= setup.parameters.pulse_adc_soc != FP_ZERO ? true : false;
m_status &= setup.parameters.adc_soc_offset >= FP_ZERO ? true : false;
m_status &= setup.parameters.adc_soc_quantity >= 1 ? true : false;
m_status &= setup.gpio_setup != 0 ? true : false;
//
if(m_status)
{
m_configuration_current = setup.parameters;
m_tbprd = 0;
m_clkdiv = 0;
m_hspclkdiv = 0;
m_cmpr_sync = 0;
//
m_cmpr_adc_start = 0;
m_cmpr_adc_stop = 0;
m_cmpr_adc_width = 0;
m_cmpr_adc_step = 0;
//
m_adc_soc_quantity = setup.parameters.adc_soc_quantity;
m_adc_soc_counter = 0;
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/setup.parameters.fpwm;
//
while(m_timer_period>(float)(32767.0))
{
m_clkdiv++;
if(m_clkdiv >= 8)
{
m_clkdiv = 0;
m_hspclkdiv++;
//
}//if
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/setup.parameters.fpwm;
//
}//while
//
m_timer_step = (m_clock_prescale_list[m_clkdiv] * m_high_speed_clock_prescale[m_hspclkdiv])/m_fcpu;
m_tbprd = (Uint16)m_timer_period;
m_cmpr_sync = m_tbprd - (Uint16)(setup.parameters.pulse_sync/m_timer_step);
m_cmpr_adc_width = (Uint16)((float)(setup.parameters.pulse_adc_soc/m_timer_step));
m_cmpr_adc_step = (Uint16)((float)((float)m_timer_period/((float)setup.parameters.adc_soc_quantity)));
m_cmpr_adc_offset = (Uint16)((float)(m_timer_period * setup.parameters.adc_soc_offset));
m_time_sample_adc = m_timer_step * ((float)m_cmpr_adc_step);
status.all = 0;
//
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
// Setup TBCLK
EPwm1Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //
EPwm1Regs.TBCTL.bit.PHSEN = 0x0; //
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm1Regs.TBCTL.bit.CLKDIV = m_clkdiv;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm1Regs.AQCTLB.all = 0;
EPwm1Regs.AQSFRC.bit.ACTSFA = 0;
EPwm1Regs.AQSFRC.bit.ACTSFB = 0;
EPwm1Regs.AQSFRC.bit.OTSFA = 0;
EPwm1Regs.AQSFRC.bit.OTSFB = 0;
EPwm1Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm1Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm1Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm1Regs.DBCTL.bit.POLSEL = 0; // Active High complementary
EPwm1Regs.DBCTL.bit.IN_MODE = 0; //
EPwm1Regs.DBFED = 0;
EPwm1Regs.DBRED = 0;
// Set Compare values
EPwm1Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm1Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
//EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA; // Select INT on equal to CMPA
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
//EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // SOCA equal to zero: 1-zero; 2-period
//EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Disable INT EPWMxSOCA
//EPwm1Regs.ETSEL.bit.SOCBSEL = 2 // SOCB equal to period
//EPwm1Regs.ETSEL.bit.SOCBEN = 0; // Disable INT EPWMxSOCB
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; //
EPwm1Regs.ETPS.bit.INTCNT = 0;
// PWM-Chopper
EPwm1Regs.PCCTL.all = 0; // PWM-Chopper Control Register
// Trip-Zone Submodule
EPwm1Regs.TZSEL.all = 0; // Trip-Zone Select Register
EPwm1Regs.TZCTL.all = 0; // Trip-Zone Control Register
EPwm1Regs.TZEINT.all = 0; // Trip-Zone Enable Interrupt Register
//EPwm1Regs.TZFLG.all = 0; // Trip-Zone Flag Register
//EPwm1Regs.TZCLR.all = 0; // Trip-Zone Clear Register
//EPwm1Regs.TZFRC.all = 0; // Trip-Zone Force Register
// Setup TBCLK
EPwm2Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; //
EPwm2Regs.TBCTL.bit.PHSEN = 0x0; //
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm2Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm2Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm2Regs.AQCTLB.all = 0;
EPwm2Regs.AQSFRC.bit.ACTSFA = 0;
EPwm2Regs.AQSFRC.bit.ACTSFB = 0;
EPwm2Regs.AQSFRC.bit.OTSFA = 0;
EPwm2Regs.AQSFRC.bit.OTSFB = 0;
EPwm2Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm2Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm2Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm2Regs.DBCTL.bit.POLSEL = 0; // Active High complementary
EPwm2Regs.DBCTL.bit.IN_MODE = 0; //
EPwm2Regs.DBFED = 0;
EPwm2Regs.DBRED = 0;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_offset; // Set compare A value
EPwm2Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTRU_CMPA; //
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
//EPwm2Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // SOCA equal to zero: 1-zero; 2-period
//EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Disable INT EPWMxSOCA
//EPwm2Regs.ETSEL.bit.SOCBSEL = 2 // SOCB equal to period
//EPwm2Regs.ETSEL.bit.SOCBEN = 0; // Disable INT EPWMxSOCB
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; //
EPwm2Regs.ETPS.bit.INTCNT = 0;
// Setup TBCLK
EPwm5Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm5Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;// Count up/down
EPwm5Regs.TBCTL.bit.PHSEN = 0x0; // Disable phase loading
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm5Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm5Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm5Regs.CMPCTL.bit.LOADAMODE = 0; // Load on Zero
EPwm5Regs.CMPCTL.bit.LOADBMODE = 0;
// Set actions
EPwm5Regs.AQCTLA.all = 0;
EPwm5Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm5Regs.AQCTLB.bit.PRD = AQ_CLEAR;
EPwm5Regs.AQSFRC.bit.ACTSFA = 0;
EPwm5Regs.AQSFRC.bit.ACTSFB = 0;
EPwm5Regs.AQSFRC.bit.OTSFA = 0;
EPwm5Regs.AQSFRC.bit.OTSFB = 0;
EPwm5Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm5Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm5Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm5Regs.DBCTL.bit.POLSEL = 0; // Active Hi complementary
EPwm5Regs.DBCTL.bit.IN_MODE = 0; //
EPwm5Regs.DBFED = 0;
EPwm5Regs.DBRED = 0;
// Set Compare values
EPwm5Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm5Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
EPwm5Regs.ETSEL.all = 0;
EPwm5Regs.ETPS.all = 0;
// PWM-Chopper
EPwm5Regs.PCCTL.all = 0; // PWM-Chopper Control Register
// Trip-Zone Submodule
EPwm5Regs.TZSEL.all = 0; // Trip-Zone Select Register
EPwm5Regs.TZCTL.all = 0; // Trip-Zone Control Register
EPwm5Regs.TZEINT.all = 0; // Trip-Zone Enable Interrupt Register
// Setup TBCLK
EPwm6Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm6Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;// Count up/down
EPwm6Regs.TBCTL.bit.PHSEN = 0x0; // Disable phase loading
EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW; //
EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
//
EPwm6Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
EPwm6Regs.TBCTL.bit.FREE_SOFT = 0;
// Setup shadowing
EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm6Regs.CMPCTL.bit.LOADAMODE = 0; // Load on Zero
EPwm6Regs.CMPCTL.bit.LOADBMODE = 0;
// Set actions
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count
EPwm6Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm6Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm6Regs.AQCTLB.bit.PRD = AQ_CLEAR;
EPwm6Regs.AQSFRC.bit.ACTSFA = 0;
EPwm6Regs.AQSFRC.bit.ACTSFB = 0;
EPwm6Regs.AQSFRC.bit.OTSFA = 0;
EPwm6Regs.AQSFRC.bit.OTSFB = 0;
EPwm6Regs.AQCSFRC.bit.CSFA = 0; // Forces a continuous low on output A
EPwm6Regs.AQCSFRC.bit.CSFB = 0; // Forces a continuous low on output B
// Dead-band
EPwm6Regs.DBCTL.bit.OUT_MODE = 0; // Enable module
EPwm6Regs.DBCTL.bit.POLSEL = 0; // Active Hi complementary
EPwm6Regs.DBCTL.bit.IN_MODE = 0; //
EPwm6Regs.DBFED = 0;
EPwm6Regs.DBRED = 0;
// Set Compare values
EPwm6Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm6Regs.CMPB = 0; // Set Compare B value
// Interrupt where we will change the Compare Values
EPwm6Regs.ETSEL.all = 0;
//EPwm6Regs.ETPS.bit.INTPRD = 0; //
EPwm6Regs.ETPS.all = 0;
// PWM-Chopper
EPwm6Regs.PCCTL.all = 0; // PWM-Chopper Control Register
// Trip-Zone Submodule
EPwm6Regs.TZSEL.all = 0; // Trip-Zone Select Register
EPwm6Regs.TZCTL.all = 0; // Trip-Zone Control Register
EPwm6Regs.TZEINT.all = 0; // Trip-Zone Enable Interrupt Register
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_start;
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
m_mode = DSP28335::EPWM::OPERATIONAL;
//
}
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::configure(const EPWMConfiguration& config)
{
m_status = true;
m_status &= config.fpwm > (float)(5.0) ? true : false;
m_status &= config.pulse_sync != FP_ZERO ? true : false;
m_status &= config.pulse_adc_soc != FP_ZERO ? true : false;
m_status &= config.adc_soc_offset >= FP_ZERO ? true : false;
m_status &= config.adc_soc_quantity >= 1 ? true : false;
//
if(m_status)
{
m_configuration_current = config;
m_tbprd = 0;
m_clkdiv = 0;
m_hspclkdiv = 0;
m_cmpr_sync = 0;
//
m_cmpr_adc_start = 0;
m_cmpr_adc_stop = 0;
m_cmpr_adc_width = 0;
m_cmpr_adc_step = 0;
//
m_adc_soc_quantity = config.adc_soc_quantity;
m_adc_soc_counter = 0;
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/config.fpwm;
//
while(m_timer_period>(float)(32767.0))
{
m_clkdiv++;
if(m_clkdiv >= 8)
{
m_clkdiv = 0;
m_hspclkdiv++;
//
}//if
//
m_timer_period = m_fcpu/m_clock_prescale_list[m_clkdiv]/m_high_speed_clock_prescale[m_hspclkdiv]/config.fpwm;
//
}//while
//
m_timer_step = (m_clock_prescale_list[m_clkdiv] * m_high_speed_clock_prescale[m_hspclkdiv])/m_fcpu;
m_tbprd = (Uint16)m_timer_period;
m_cmpr_sync = m_tbprd - (Uint16)(config.pulse_sync/m_timer_step);
m_cmpr_adc_width = (Uint16)((float)(config.pulse_adc_soc/m_timer_step));
//m_cmpr_adc_step = (Uint16)(m_tbprd/config.adc_soc_quantity);
m_cmpr_adc_step = (Uint16)((float)((float)m_timer_period/((float)config.adc_soc_quantity)));
m_cmpr_adc_offset = (Uint16)((float)(m_timer_period * config.adc_soc_offset));
m_time_sample_adc = m_timer_step * ((float)m_cmpr_adc_step);
status.all = 0x0001;
//
//
EPwm1Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm1Regs.TBCTL.bit.CLKDIV = m_clkdiv;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
EPwm1Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
EPwm2Regs.TBPRD = m_tbprd;
EPwm2Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
//
// EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_offset; // Set compare A value
EPwm5Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm5Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
EPwm5Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
// Setup TBCLK
EPwm6Regs.TBPRD = m_tbprd; // Set timer period 801 TBCLKs
EPwm6Regs.TBCTL.bit.CLKDIV = m_clkdiv;;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = m_hspclkdiv;
EPwm6Regs.CMPA.half.CMPA = m_cmpr_sync; // Set compare A value
//
}
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::set_actions()
{
// Set EPWM1 actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;
//EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on event A, up count
//EPwm1Regs.AQCTLA.bit.PRD = AQ_SET;
//
// Set EPWM5 actions
EPwm5Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm5Regs.AQCTLB.bit.PRD = AQ_CLEAR;
//EPwm5Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2B on event B, up count
//EPwm5Regs.AQCTLB.bit.PRD = AQ_SET;
//
// Set EPWM6 actions
EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on event A, up count
EPwm6Regs.AQCTLA.bit.PRD = AQ_CLEAR;
EPwm6Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2B on event B, up count
EPwm6Regs.AQCTLB.bit.PRD = AQ_CLEAR;
//EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on event A, up count
//EPwm6Regs.AQCTLA.bit.PRD = AQ_SET;
//EPwm6Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2B on event B, up count
//EPwm6Regs.AQCTLB.bit.PRD = AQ_SET;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::clear_actions()
{
// Clear actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
EPwm1Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
//
// Set EPWM5 actions
EPwm5Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
EPwm5Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
//
// Set EPWM6 actions
EPwm6Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
EPwm6Regs.AQCTLA.bit.PRD = AQ_NO_ACTION;
EPwm6Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
EPwm6Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
float EPWM::get_time_sample_adc()
{
return m_time_sample_adc;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm1_adc_drive()
{
m_adc_soc_counter = 0;
m_cmpr_adc_start = m_cmpr_adc_offset;
m_cmpr_adc_stop = m_cmpr_adc_offset + m_cmpr_adc_width;
//
//new_cycle = 1;
//adc_soc = 0;
//adc_ready = 0;
status.all = 0x001;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_start; // Set compare A value
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_start;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm2_adc_drive()
{
(this->*_epwm2_adc_drive)();
//
}//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::_epwm2_adc_drive_mode_start()
{
//new_cycle = 0;
//adc_soc = 1;
//adc_ready = 0;
status.all = 0x002;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_stop; // Set compare A value
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_stop;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::_epwm2_adc_drive_mode_stop()
{
m_adc_soc_counter++;
m_cmpr_adc_start += m_cmpr_adc_step;
m_cmpr_adc_stop += m_cmpr_adc_step;
//new_cycle = 0;
//adc_soc = 0;
//adc_ready = 1;
status.all = 0x004;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = m_cmpr_adc_start; // Set compare A value
_epwm2_adc_drive = &DSP28335::EPWM::_epwm2_adc_drive_mode_start;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm1_interrupt_ack()
{
EPwm1Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void EPWM::epwm2_interrupt_ack()
{
EPwm2Regs.ETCLR.bit.INT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//
}//
//
} /* namespace DSP28335 */

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/*
* EPWM.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#ifndef DSP28335_EPWM_H_
#define DSP28335_EPWM_H_
namespace DSP28335
{
enum CLOCKPRESCALE {DIV01, DIV02, DIV04, DIV08, DIV16, DIV32, DIV64, DIV128};
enum HIGHSPEEDCLOCKPRESCALE {HSDIV01, HSDIV02, HSDIV04, HSDIV06, HSDIV08, HSDIV10, HSDIV12, HSDIV14};
struct EPWMStatusBitField
{
Uint16 new_cycle:1;
Uint16 adc_soc:1;
Uint16 adc_ready:1;
};//EPWMStatusBitField
union EPWMStatusRegister
{
Uint16 all;
EPWMStatusBitField bit;
EPWMStatusRegister():
all(0)
{}
};//EPWMStatusRegister
struct EPWMConfiguration
{
float fpwm;
float pulse_sync;
float pulse_adc_soc;
float adc_soc_offset;
Uint16 adc_soc_quantity;
EPWMConfiguration():
fpwm(500.0),
pulse_sync(1.0e-6),
pulse_adc_soc(10.0e-6),
adc_soc_offset(FP_ZERO),
adc_soc_quantity(1)
{}
};//EPWMConfiguration
class EPWMConfigModificator
{
private:
EPWMConfiguration m_config;
public:
bool modify;
public:
EPWMConfigModificator();
void set_config(EPWMConfiguration& refconfig);
EPWMConfiguration get_config();
public:
void reset();
public:
void set_pwm_frquency(float fpwm);
void set_pulse_sync(float pulse_sync);
void set_pulse_adc_soc(float pulse_adc_soc);
void set_adc_soc_offset(float adc_soc_offset);
void set_adc_soc_quantity(Uint16 adc_soc_quantity);
public:
float get_pwm_frquency();
float get_pulse_sync();
float get_pulse_adc_soc();
float get_adc_soc_offset();
Uint16 get_adc_soc_quantity();
//
};//EPWMConfigModificator
struct EPWMSetup: public DSP28335::CPUBaseSetup
{
EPWMConfiguration parameters;
EPWMSetup():
DSP28335::CPUBaseSetup(),
parameters()
{}
};//EPWMSetup
class EPWM: public DSP28335::CPUBase
{
private:
EPWMConfiguration m_configuration_current;
EPWMConfiguration m_configuration_new;
private:
float m_fcpu;
float m_timer_period;
float m_timer_step;
float m_time_sample_adc;
float m_clock_prescale_list[8];
float m_high_speed_clock_prescale[8];
Uint16 m_tbprd; //TBPRD
Uint16 m_clkdiv;
Uint16 m_hspclkdiv;
Uint16 m_cmpr_sync;
Uint16 m_cmpr_adc_offset;
Uint16 m_cmpr_adc_start;
Uint16 m_cmpr_adc_stop;
Uint16 m_cmpr_adc_width;
Uint16 m_cmpr_adc_step;
Uint16 m_adc_soc_quantity;
Uint16 m_adc_soc_counter;
public:
EPWMStatusRegister status;
public:
EPWM();
void setup(const EPWMSetup& setup);
void configure(const EPWMConfiguration& config);
public:
void set_actions();
void clear_actions();
public:
float get_time_sample_adc();
public:
void epwm1_adc_drive();
public:
void epwm2_adc_drive();
private:
void (EPWM::*_epwm2_adc_drive)();
void _epwm2_adc_drive_mode_start();
void _epwm2_adc_drive_mode_stop();
public:
void epwm1_interrupt_ack();
void epwm2_interrupt_ack();
private:
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_EPWM_H_ */

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DSP28335/EQEP1.cpp
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/*
* EQEP1.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/EQEP1.h"
namespace DSP28335
{
//CONSTRUCTOR
EQEP1::EQEP1():
DSP28335::CPUBase(),
_gpio_setup(&DSP28335::GPIO::gpio_eqep_setup)
//
{}//CONSTRUCTOR
void EQEP1::setup(const EQEP1Setup& setup)
{
m_status = m_mode == DSP28335::EQEP1::UNDEFINED ? true : false;
m_status &= setup.gpio_setup != 0 ? true : false;
if(m_status)
{
//
EQep1Regs.QDECCTL.bit.QSRC = 00;
EQep1Regs.QDECCTL.bit.XCR = 0;
EQep1Regs.QEPCTL.bit.FREE_SOFT = 2;
EQep1Regs.QPOSMAX = 0xffffffff;
EQep1Regs.QEPCTL.bit.QPEN = 1;
EQep1Regs.QPOSCNT = 0x00000000;
//
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
//
m_mode = DSP28335::EQEP1::OPERATIONAL;
//
}//if
//
//
}//
//
} /* namespace DSP28335 */

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DSP28335/EQEP1.h
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/*
* EQEP1.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#include "DSP28335/GPIO.h"
#ifndef DSP28335_EQEP1_H_
#define DSP28335_EQEP1_H_
namespace DSP28335
{
struct EQEP1Setup: public DSP28335::CPUBaseSetup
{
EQEP1Setup():
DSP28335::CPUBaseSetup()
{}
};//
class EQEP1: public DSP28335::CPUBase
{
public:
EQEP1();
void setup(const EQEP1Setup& setup);
private:
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_EQEP1_H_ */

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DSP28335/FLASH.cpp
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/*
* Flash.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/FLASH.h"
namespace DSP28335
{
//CONSTRUCTOR
FLASH::FLASH():
DSP28335::CPUBase(),
m_mask_sector(0),
//
m_operation_status_erase(0),
m_operation_status_program(0),
m_operation_status_verify(0),
//
m_version_hex_default(API_VERSION_DEFAULT),
m_version_hex(0)
{
m_sector.StartAddr = 0;
m_sector.EndAddr = 0;
//
m_status_erase.FirstFailAddr = 0;
m_status_erase.ExpectedData = 0;
m_status_erase.ActualData = 0;
//
m_status_program.FirstFailAddr = 0;
m_status_program.ExpectedData = 0;
m_status_program.ActualData = 0;
//
m_status_verify.FirstFailAddr = 0;
m_status_verify.ExpectedData = 0;
m_status_verify.ActualData = 0;
//
}//end CONSTRUCTOR
void FLASH::setup(Uint16 mask_sector, Uint16 *StartAddr, Uint16 *EndAddr)
{
m_mask_sector = mask_sector;
m_sector.StartAddr = StartAddr;
m_sector.EndAddr = EndAddr;
//SCALE_FACTOR is defined in Flash2833x_API_Config.h
//EALLOW;
Flash_CPUScaleFactor = SCALE_FACTOR;
//EDIS;
//
m_mode = DSP28335::FLASH::OPERATIONAL;
//
}//end
Uint16 FLASH::erase()
{
//Uint16 status = 0;
//Flash_Erase(Uint16 SectorMask, FLASH_ST *FEraseStat);
//status = Flash_Erase(m_mask_sector, &m_status_erase);
//return status;
return Flash_Erase(m_mask_sector, &m_status_erase);
//
}//end
Uint16 FLASH::read(Uint16 *Dest, Uint32 Length)
{
Uint16 *Source = m_sector.StartAddr;
Uint16 status = 0;
if(Length <= 0x4000)
{
for(Uint32 i=0; i<Length; i++)
{
(*Dest++) = (*Source++);
//
}//end for
status = 1;
//
}//end if
//
return status;
//
}//end
Uint16 FLASH::program(Uint16 *BufAddr, Uint32 Length)
{
Uint16 status = STATUS_SUCCESS;
m_status_erase.FirstFailAddr = 0;
m_status_erase.ExpectedData = 0;
m_status_erase.ActualData = 0;
m_status_program.FirstFailAddr = 0;
m_status_program.ExpectedData = 0;
m_status_program.ActualData = 0;
m_status_verify.FirstFailAddr = 0;
m_status_verify.ExpectedData = 0;
m_status_verify.ActualData = 0;
status = Flash_Erase(m_mask_sector, &m_status_erase);
if(status != STATUS_SUCCESS) return status;
//Flash_Program(Uint16 *FlashAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FProgStatus);
status = Flash_Program(m_sector.StartAddr, BufAddr, Length, &m_status_program);
if(status != STATUS_SUCCESS) return status;
//Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FVerifyStat);
status = Flash_Verify(m_sector.StartAddr, BufAddr, Length, &m_status_verify);
return status;
//
}//end
Uint16 FLASH::verify(Uint16 *BufAddr, Uint32 Length)
{
Uint16 status = STATUS_SUCCESS;
m_status_verify.FirstFailAddr = 0;
m_status_verify.ExpectedData = 0;
m_status_verify.ActualData = 0;
//Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FVerifyStat);
status = Flash_Verify(m_sector.StartAddr, BufAddr, Length, &m_status_verify);
return status;
//
}//end
Uint16 FLASH::APIVersionHex()
{
Uint16 version = 0;
version = Flash_APIVersionHex();
return version;
//
}//end
} /* namespace DSP28335 */

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/*
* Flash.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "F28335/Flash2833x_API_Config.h"
#include "F28335/Flash2833x_API_Library.h"
#include "DSP28335/CPUBase.h"
#ifndef DSP28335_FLASH_H_
#define DSP28335_FLASH_H_
#define API_VERSION_DEFAULT 0x0100
namespace DSP28335
{
typedef struct
{
Uint16 *StartAddr;
Uint16 *EndAddr;
}SECTOR;
class FLASH: public DSP28335::CPUBase
{
private:
Uint16 m_mask_sector;
SECTOR m_sector;
//
FLASH_ST m_status_erase;
FLASH_ST m_status_program;
FLASH_ST m_status_verify;
Uint16 m_operation_status_erase;
Uint16 m_operation_status_program;
Uint16 m_operation_status_verify;
//
Uint16 m_version_hex_default;
Uint16 m_version_hex;
//
public:
FLASH();
void setup(Uint16 mask_sector, Uint16 *StartAddr, Uint16 *EndAddr);
Uint16 erase();
Uint16 read(Uint16 *Dest, Uint32 Length);
Uint16 program(Uint16 *BufAddr, Uint32 Length);
Uint16 verify(Uint16 *BufAddr, Uint32 Length);
Uint16 APIVersionHex();
//
};//end class FLASH
} /* namespace DSP28335 */
#endif /* DSP28335_FLASH_H_ */

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DSP28335/GPIO.cpp
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/*
* GPIO.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/GPIO.h"
namespace DSP28335
{
//CONSTRUCTOR
GPIO::GPIO():
DSP28335::CPUBase()
//
{}//end CONSTRUCTOR
//EPWM
// #pragma CODE_SECTION("ramfuncs");
void GPIO::gpio_epwm_setup()
{
EALLOW;
//
// General Synchronization Signal GENSYNC - EPWM1A - GPIO0
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pull-up on GPIO0 (EPWM1A)
GpioDataRegs.GPACLEAR.bit.GPIO0 = 1; // Clear EPWM1A
GpioCtrlRegs.GPADIR.bit.GPIO0 = 0; // Output - EPWM1A
//
// Phase A (U) Synchronization Signal - EPWM5B - GPIO9
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Disable pull-up on GPIO9 (EPWM5B)
GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; // Clear EPWM5B
GpioCtrlRegs.GPADIR.bit.GPIO9 = 0; // Output - EPWM5B
//
// Phase B (V) Synchronization Signal - EPWM6A - GPIO10
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Disable pull-up on GPIO10 (EPWM6A)
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1; // Clear EPWM6A
GpioCtrlRegs.GPADIR.bit.GPIO10 = 0; // Output - EPWM6A
//
// Phase C (W) Synchronization Signal - EPWM6B - GPIO11
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO9 as EPWM6B
GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Disable pull-up on GPIO11 (EPWM6B)
GpioDataRegs.GPACLEAR.bit.GPIO11 = 1; // Clear EPWM6B
GpioCtrlRegs.GPADIR.bit.GPIO11 = 0; // Output - EPWM6B
//
EDIS;
//
}//end
//
//CAN Inteface
void GPIO::gpio_cana_setup()
{
EALLOW;
//
// Enable CANA on GPIO18, CPIO19
// CANRXA - GPIO18
// CANTXA - GPIO19
//
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pullup on GPIO18
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // GPIO18 = CANRXA
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input
GpioCtrlRegs.GPADIR.bit.GPIO18 = 0; // GPIO18 = 0/1 - input/output
GpioDataRegs.GPASET.bit.GPIO18 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO18 = 0; // Clear output
//
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pullup on GPIO19
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // GPIO19 = CANTXA
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 0; // Asynch input
GpioCtrlRegs.GPADIR.bit.GPIO19 = 0; // GPIO19 = 0/1 - input/output
GpioDataRegs.GPASET.bit.GPIO19 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO19 = 0; // Clear output
//
EDIS;
//
}//end
//
void GPIO::gpio_canb_setup()
{
EALLOW;
//
// Enable CANB on GPIO16, CPIO17
// CANTXB - GPIO16
// CANRXB - GPIO17
//
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2; // GPIO16 = CANTXA
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 0; // Asynch input
GpioCtrlRegs.GPADIR.bit.GPIO16 = 0; // GPIO16 = 0/1 - input/output
GpioDataRegs.GPASET.bit.GPIO16 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO16 = 0; // Clear output
//
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pullup on GPIO17
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2; // GPIO17 = CANRXA
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input
GpioCtrlRegs.GPADIR.bit.GPIO17 = 0; // GPIO17 = 0/1 - input/output
GpioDataRegs.GPASET.bit.GPIO17 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO17 = 0; // Clear output
//
EDIS;
//
}//end
//
//SCIA
void GPIO::gpio_scia_setup()
{}//
//
//RS485 - SCIB
void GPIO::gpio_scib_setup()
{
EALLOW;
//
// Enable SCI-B on GPIO21, GPIO22, GPIO23 - RS485
// SCIENBLB - GPIO21
// SCITXDB - GPIO22
// SCIRXDB - GPIO23
//
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; // GPIO22 = SCITXDB
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO22
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Asynch input
GpioCtrlRegs.GPADIR.bit.GPIO22 = 0; // GPIO22 = 0/1 - input/output
//
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; // GPIO23 = SCIRXDB
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pullup on GPIO23
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input
GpioCtrlRegs.GPADIR.bit.GPIO23 = 0; // GPIO23 = 0/1 - input/output
//
EDIS;
//
}//end
//
void GPIO::gpio_scib_re_de_setup()
{
EALLOW;
//
// Enable SCI-B on GPIO21, GPIO22, GPIO23 - RS485
// SCIENBLB - GPIO21
// SCITXDB - GPIO22
// SCIRXDB - GPIO23
//
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 0; // GPIO21 = DE-RS485
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pullup on GPIO21
GpioCtrlRegs.GPADIR.bit.GPIO21 = 1; // GPIO21 = 0/1 - input/output
GpioDataRegs.GPASET.bit.GPIO21 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO21 = 0; // Clear output
//
EDIS;
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void GPIO::gpio_scib_re_de_set()
{
//set GPIO21
GpioDataRegs.GPASET.bit.GPIO21 = 1;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void GPIO::gpio_scib_re_de_clear()
{
//clear GPIO21
GpioDataRegs.GPACLEAR.bit.GPIO21 = 1;
//
}//
//
//RS485 - SCIC
void GPIO::gpio_scic_setup()
{
EALLOW;
//
// Enable SCI-C on GPIO61, GPIO62, GPIO63 - RS485
// SCIENBLC - GPIO61
// SCIRXDC - GPIO62
// SCITXDC - GPIO63
//
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0; // GPIO61 = DE-RS485
GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pullup on GPIO61
GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1; // GPIO61 = 0/1 - input/output
GpioDataRegs.GPBSET.bit.GPIO61 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO61 = 0; // Clear output
//
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // GPIO62 = SCIRXDC
GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pullup on GPIO62
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input
GpioCtrlRegs.GPBDIR.bit.GPIO62 = 0; // GPIO62 = 0/1 - input/output
//
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // GPIO63 = SCITXDC
GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pullup on GPIO63
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0; // Asynch input
GpioCtrlRegs.GPBDIR.bit.GPIO63 = 0; // GPIO63 = 0/1 - input/output
//
EDIS;
//
}//end
//FRAM - SPIA
void GPIO::gpio_spia_setup()
{
EALLOW;
//
//GPIO54 - SPISIMOA
//GPIO55 - SPISOMIA
//GPIO56 - SPICLKA
//GPIO57 - SPISTEA
//GPIO58 - SPISWP - Write Protect
//
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA
GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO54 (SPISIMOA)
GpioCtrlRegs.GPBDIR.bit.GPIO54 = 1; // GPIO54 = 0/1 - input/output
//
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA
GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO55 (SPISOMIA)
GpioCtrlRegs.GPBDIR.bit.GPIO55 = 0; // GPIO55 = 0/1 - input/output
//
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA
GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO56 (SPICLKA)
GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1; // GPIO56 = 0/1 - input/output
//
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA
GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA)
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO57 (SPISTEA)
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1; // GPIO57 = 0/1 - input/output
//
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0; // Configure GPIO58 as GPIO
GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pull-up on GPIO58
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // Asynch input GPIO58
GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1; // GPIO58 = 0/1 - input/output
//
EDIS;
//
}//
//
void GPIO::gpio_spia_write_protect_set()
{
GpioDataRegs.GPBSET.bit.GPIO58 = 1; // Set output
//
}//
//
void GPIO::gpio_spia_write_protect_clear()
{
GpioDataRegs.GPBCLEAR.bit.GPIO58 = 1; // Set output
//
}//
//
//
void GPIO::gpio_eqep_setup()
{
EALLOW;
//
// Enable eQEP on GPIO50, CPIO51
// EQEP1A - GPIO50
// EQEP1B - GPIO51
//
GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0; // Enable pullup on GPIO50
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // GPIO50 = EQEP1A
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Asynch input
GpioCtrlRegs.GPBDIR.bit.GPIO50 = 0; // GPIO50 = 0/1 - input/output
GpioDataRegs.GPBSET.bit.GPIO50 = 1; //
GpioDataRegs.GPBCLEAR.bit.GPIO50 = 0; // Clear output
//
GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0; // Enable pullup on GPIO51
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // GPIO51 = EQEP1B
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Asynch input
GpioCtrlRegs.GPBDIR.bit.GPIO51 = 0; // GPIO51 = 0/1 - input/output
GpioDataRegs.GPBSET.bit.GPIO51 = 1; //
GpioDataRegs.GPBCLEAR.bit.GPIO51 = 0; // Clear output
//
EDIS;
//
}//
//
void GPIO::gpio_xintf_16bit_setup()
{
EALLOW;
//
// XINF - external interface
//
// GPIO34 - XREADY
GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pullup on GPIO34
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0; // GPIO34 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO34 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // GPIO34 = XREADY
GpioDataRegs.GPBSET.bit.GPIO34 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO34 = 0; // Clear output
//
// GPIO35 - XR/nW
GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pullup on GPIO35
GpioCtrlRegs.GPBDIR.bit.GPIO35 = 1; // GPIO35 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO35 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // GPIO35 = XR/nW
GpioDataRegs.GPBSET.bit.GPIO35 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO35 = 0; // Clear output
//
// GPIO36 - nXZCS0
GpioCtrlRegs.GPBPUD.bit.GPIO36 = 0; // Enable pullup on GPIO36
GpioCtrlRegs.GPBDIR.bit.GPIO36 = 1; // GPIO36 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO36 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // GPIO36 = nXZCS0
GpioDataRegs.GPBSET.bit.GPIO36 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO36 = 0; // Clear output
//
// GPIO28 - nXZCS6
GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28
GpioCtrlRegs.GPADIR.bit.GPIO28 = 1; // GPIO28 = 0/1 - input/output
GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 0; // Asynch input
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // GPIO28 = nXZCS6
GpioDataRegs.GPASET.bit.GPIO28 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO28 = 0; // Clear output
//
// GPIO37 - nXZCS7
GpioCtrlRegs.GPBPUD.bit.GPIO37 = 0; // Enable pullup on GPIO37
GpioCtrlRegs.GPBDIR.bit.GPIO37 = 1; // GPIO37 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO37 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // GPIO37 = nXZCS7
GpioDataRegs.GPBSET.bit.GPIO37 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO37 = 0; // Clear output
//
// GPIO38 - nXWE0
GpioCtrlRegs.GPBPUD.bit.GPIO38 = 0; // Enable pullup on GPIO38
GpioCtrlRegs.GPBDIR.bit.GPIO38 = 1; // GPIO38 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO38 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // GPIO38 = nXWE0
GpioDataRegs.GPBSET.bit.GPIO38 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO38 = 0; // Clear output
//
// GPIO39 - XA16
GpioCtrlRegs.GPBPUD.bit.GPIO39 = 0; // Enable pullup on GPIO39
GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0; // GPIO39 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO39 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // GPIO39 = XA16
GpioDataRegs.GPBSET.bit.GPIO39 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO39 = 0; // Clear output
//
// GPIO40 - XA0
GpioCtrlRegs.GPBPUD.bit.GPIO40 = 0; // Enable pullup on GPIO40
GpioCtrlRegs.GPBDIR.bit.GPIO40 = 0; // GPIO40 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO40 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // GPIO40 = XA0
GpioDataRegs.GPBSET.bit.GPIO40 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO40 = 0; // Clear output
//
// GPIO41 - XA1
GpioCtrlRegs.GPBPUD.bit.GPIO41 = 0; // Enable pullup on GPIO41
GpioCtrlRegs.GPBDIR.bit.GPIO41 = 0; // GPIO41 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO41 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // GPIO41 = XA1
GpioDataRegs.GPBSET.bit.GPIO41 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO41 = 0; // Clear output
//
// GPIO42 - XA2
GpioCtrlRegs.GPBPUD.bit.GPIO42 = 0; // Enable pullup on GPIO42
GpioCtrlRegs.GPBDIR.bit.GPIO42 = 0; // GPIO42 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO42 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // GPIO42 = XA2
GpioDataRegs.GPBSET.bit.GPIO42 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO42 = 0; // Clear output
//
// GPIO43 - XA3
GpioCtrlRegs.GPBPUD.bit.GPIO43 = 0; // Enable pullup on GPIO43
GpioCtrlRegs.GPBDIR.bit.GPIO43 = 0; // GPIO43 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO43 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // GPIO43 = XA3
GpioDataRegs.GPBSET.bit.GPIO43 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO43 = 0; // Clear output
//
// GPIO44 - XA4
GpioCtrlRegs.GPBPUD.bit.GPIO44 = 0; // Enable pullup on GPIO44
GpioCtrlRegs.GPBDIR.bit.GPIO44 = 0; // GPIO44 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO44 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // GPIO44 = XA4
GpioDataRegs.GPBSET.bit.GPIO44 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO44 = 0; // Clear output
//
// GPIO45 - XA5
GpioCtrlRegs.GPBPUD.bit.GPIO45 = 0; // Enable pullup on GPIO45
GpioCtrlRegs.GPBDIR.bit.GPIO45 = 0; // GPIO45 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO45 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // GPIO45 = XA5
GpioDataRegs.GPBSET.bit.GPIO45 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO45 = 0; // Clear output
//
// GPIO46 - XA6
GpioCtrlRegs.GPBPUD.bit.GPIO46 = 0; // Enable pullup on GPIO46
GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0; // GPIO46 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO46 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // GPIO46 = XA6
GpioDataRegs.GPBSET.bit.GPIO46 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO46 = 0; // Clear output
//
// GPIO47 - XA7
GpioCtrlRegs.GPBPUD.bit.GPIO47 = 0; // Enable pullup on GPIO47
GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0; // GPIO47 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO47 = 0; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // GPIO47 = XA7
GpioDataRegs.GPBSET.bit.GPIO47 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO47 = 0; // Clear output
//
// GPIO80 - XA8
GpioCtrlRegs.GPCPUD.bit.GPIO80 = 0; // Enable pullup on GPIO80
GpioCtrlRegs.GPCDIR.bit.GPIO80 = 0; // GPIO80 = 0/1 - input/output
GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 2; // GPIO80 = XA8
GpioDataRegs.GPCSET.bit.GPIO80 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO80 = 0; // Clear output
//
// GPIO81 - XA9
GpioCtrlRegs.GPCPUD.bit.GPIO81 = 0; // Enable pullup on GPIO81
GpioCtrlRegs.GPCDIR.bit.GPIO81 = 0; // GPIO81 = 0/1 - input/output
GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 2; // GPIO81 = XA9
GpioDataRegs.GPCSET.bit.GPIO81 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO81 = 0; // Clear output
//
// GPIO82 - XA10
GpioCtrlRegs.GPCPUD.bit.GPIO82 = 0; // Enable pullup on GPIO82
GpioCtrlRegs.GPCDIR.bit.GPIO82 = 0; // GPIO82 = 0/1 - input/output
GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 2; // GPIO82 = XA10
GpioDataRegs.GPCSET.bit.GPIO82 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO82 = 0; // Clear output
//
// GPIO83 - XA11
GpioCtrlRegs.GPCPUD.bit.GPIO83 = 0; // Enable pullup on GPIO83
GpioCtrlRegs.GPCDIR.bit.GPIO83 = 0; // GPIO83 = 0/1 - input/output
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 2; // GPIO83 = XA11
GpioDataRegs.GPCSET.bit.GPIO83 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO83 = 0; // Clear output
//
// GPIO84 - XA12
GpioCtrlRegs.GPCPUD.bit.GPIO84 = 0; // Enable pullup on GPIO84
GpioCtrlRegs.GPCDIR.bit.GPIO84 = 0; // GPIO84 = 0/1 - input/output
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2; // GPIO84 = XA12
GpioDataRegs.GPCSET.bit.GPIO84 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO84 = 0; // Clear output
//
// GPIO85 - XA13
GpioCtrlRegs.GPCPUD.bit.GPIO85 = 0; // Enable pullup on GPIO85
GpioCtrlRegs.GPCDIR.bit.GPIO85 = 0; // GPIO85 = 0/1 - input/output
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 2; // GPIO85 = XA13
GpioDataRegs.GPCSET.bit.GPIO85 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO85 = 0; // Clear output
//
// GPIO86 - XA14
GpioCtrlRegs.GPCPUD.bit.GPIO86 = 0; // Enable pullup on GPIO86
GpioCtrlRegs.GPCDIR.bit.GPIO86 = 0; // GPIO86 = 0/1 - input/output
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 2; // GPIO86 = XA14
GpioDataRegs.GPCSET.bit.GPIO86 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO86 = 0; // Clear output
//
// GPIO87 - XA15
GpioCtrlRegs.GPCPUD.bit.GPIO87 = 0; // Enable pullup on GPIO87
GpioCtrlRegs.GPCDIR.bit.GPIO87 = 0; // GPIO87 = 0/1 - input/output
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 2; // GPIO87 = XA15
GpioDataRegs.GPCSET.bit.GPIO87 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO87 = 0; // Clear output
//
// GPIO39 - XA16
GpioCtrlRegs.GPBPUD.bit.GPIO39 = 0; // Enable pullup on GPIO39
GpioCtrlRegs.GPBDIR.bit.GPIO39 = 0; // GPIO39 = 0/1 - input/output
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // GPIO39 = XA16
GpioDataRegs.GPBSET.bit.GPIO39 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO39 = 0; // Clear output
//
// GPIO31 - XA17
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pullup on GPIO31
GpioCtrlRegs.GPADIR.bit.GPIO31 = 0; // GPIO31 = 0/1 - input/output
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // GPIO31 = XA17
GpioDataRegs.GPASET.bit.GPIO31 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO31 = 0; // Clear output
//
// GPIO30 - XA18
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pullup on GPIO30
GpioCtrlRegs.GPADIR.bit.GPIO30 = 0; // GPIO30 = 0/1 - input/output
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // GPIO30 = XA18
GpioDataRegs.GPASET.bit.GPIO30 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO30 = 0; // Clear output
// GPIO29 - XA19
GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29
GpioCtrlRegs.GPADIR.bit.GPIO29 = 0; // GPIO29 = 0/1 - input/output
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // GPIO29 = XA19
GpioDataRegs.GPASET.bit.GPIO29 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO29 = 0; // Clear output
//
// GPIO64 - XD15
GpioCtrlRegs.GPCPUD.bit.GPIO64 = 0; // Enable pullup on GPIO64
GpioCtrlRegs.GPCDIR.bit.GPIO64 = 0; // GPIO64 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 2; // GPIO64 = XD
GpioDataRegs.GPCSET.bit.GPIO64 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO64 = 0; // Clear output
//
// GPIO65 - XD14
GpioCtrlRegs.GPCPUD.bit.GPIO65 = 0; // Enable pullup on GPIO65
GpioCtrlRegs.GPCDIR.bit.GPIO65 = 0; // GPIO65 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 2; // GPIO65 = XD14
GpioDataRegs.GPCSET.bit.GPIO65 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO65 = 0; // Clear output
//
// GPIO66 - XD13
GpioCtrlRegs.GPCPUD.bit.GPIO66 = 0; // Enable pullup on GPIO66
GpioCtrlRegs.GPCDIR.bit.GPIO66 = 0; // GPIO66 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 2; // GPIO66 = XD13
GpioDataRegs.GPCSET.bit.GPIO66 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO66 = 0; // Clear output
//
// GPIO67 - XD12
GpioCtrlRegs.GPCPUD.bit.GPIO67 = 0; // Enable pullup on GPIO67
GpioCtrlRegs.GPCDIR.bit.GPIO67 = 0; // GPIO67 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 2; // GPIO67 = XD12
GpioDataRegs.GPCSET.bit.GPIO67 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO67 = 0; // Clear output
//
// GPIO68 - XD11
GpioCtrlRegs.GPCPUD.bit.GPIO68 = 0; // Enable pullup on GPIO68
GpioCtrlRegs.GPCDIR.bit.GPIO68 = 0; // GPIO68 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 2; // GPIO68 = XD11
GpioDataRegs.GPCSET.bit.GPIO68 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO68 = 0; // Clear output
//
// GPIO69 - XD10
GpioCtrlRegs.GPCPUD.bit.GPIO69 = 0; // Enable pullup on GPIO69
GpioCtrlRegs.GPCDIR.bit.GPIO69 = 0; // GPIO69 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 2; // GPIO69 = XD10
GpioDataRegs.GPCSET.bit.GPIO69 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO69 = 0; // Clear output
//
// GPIO70 - XD9
GpioCtrlRegs.GPCPUD.bit.GPIO70 = 0; // Enable pullup on GPIO70
GpioCtrlRegs.GPCDIR.bit.GPIO70 = 0; // GPIO70 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 2; // GPIO70 = XD9
GpioDataRegs.GPCSET.bit.GPIO70 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO70 = 0; // Clear output
//
// GPIO71 - XD8
GpioCtrlRegs.GPCPUD.bit.GPIO71 = 0; // Enable pullup on GPIO71
GpioCtrlRegs.GPCDIR.bit.GPIO71 = 0; // GPIO71 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 2; // GPIO71 = XD8
GpioDataRegs.GPCSET.bit.GPIO71 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO71 = 0; // Clear output
//
// GPIO72 - XD7
GpioCtrlRegs.GPCPUD.bit.GPIO72 = 0; // Enable pullup on GPIO72
GpioCtrlRegs.GPCDIR.bit.GPIO72 = 0; // GPIO72 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 2; // GPIO72 = XD7
GpioDataRegs.GPCSET.bit.GPIO72 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO72 = 0; // Clear output
//
// GPIO73 - XD6
GpioCtrlRegs.GPCPUD.bit.GPIO73 = 0; // Enable pullup on GPIO73
GpioCtrlRegs.GPCDIR.bit.GPIO73 = 0; // GPIO73 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 2; // GPIO73 = XD6
GpioDataRegs.GPCSET.bit.GPIO73 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO73 = 0; // Clear output
//
// GPIO74 - XD5
GpioCtrlRegs.GPCPUD.bit.GPIO74 = 0; // Enable pullup on GPIO74
GpioCtrlRegs.GPCDIR.bit.GPIO74 = 0; // GPIO74 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 2; // GPIO74 = XD5
GpioDataRegs.GPCSET.bit.GPIO74 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO74 = 0; // Clear output
//
// GPIO75 - XD4
GpioCtrlRegs.GPCPUD.bit.GPIO75 = 0; // Enable pullup on GPIO75
GpioCtrlRegs.GPCDIR.bit.GPIO75 = 0; // GPIO75 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 2; // GPIO75 = XD4
GpioDataRegs.GPCSET.bit.GPIO75 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO75 = 0; // Clear output
//
// GPIO76 - XD3
GpioCtrlRegs.GPCPUD.bit.GPIO76 = 0; // Enable pullup on GPIO76
GpioCtrlRegs.GPCDIR.bit.GPIO76 = 0; // GPIO76 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 2; // GPIO76 = XD3
GpioDataRegs.GPCSET.bit.GPIO76 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO76 = 0; // Clear output
//
// GPIO77 - XD2
GpioCtrlRegs.GPCPUD.bit.GPIO77 = 0; // Enable pullup on GPIO77
GpioCtrlRegs.GPCDIR.bit.GPIO77 = 0; // GPIO77 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 2; // GPIO77 = XD2
GpioDataRegs.GPCSET.bit.GPIO77 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO77 = 0; // Clear output
//
// GPIO78 - XD1
GpioCtrlRegs.GPCPUD.bit.GPIO78 = 0; // Enable pullup on GPIO78
GpioCtrlRegs.GPCDIR.bit.GPIO78 = 0; // GPIO78 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 2; // GPIO78 = XD1
GpioDataRegs.GPCSET.bit.GPIO78 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO78 = 0; // Clear output
//
// GPIO79 - XD0
GpioCtrlRegs.GPCPUD.bit.GPIO79 = 0; // Enable pullup on GPIO79
GpioCtrlRegs.GPCDIR.bit.GPIO79 = 0; // GPIO79 = 0/1 - input/output
GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 2; // GPIO79 = XD0
GpioDataRegs.GPCSET.bit.GPIO79 = 0; //
GpioDataRegs.GPCCLEAR.bit.GPIO79 = 0; // Clear output
//
EDIS;
//
}//
//
void GPIO::gpio_xintf_32bit_setup()
{}//
//
void GPIO::gpio_dicrete_outputs_setup()
{
EALLOW;
//
// GPIO1
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; // GPIO1
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Enable pullup on GPIO1
GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; // GPIO1 = 0/1 - input/output
GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 0; // Asynch input
GpioDataRegs.GPASET.bit.GPIO1 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO1 = 0; // Clear output
//
// GPIO2
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0; // GPIO2
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Enable pullup on GPIO2
GpioCtrlRegs.GPADIR.bit.GPIO2 = 1; // GPIO2 = 0/1 - input/output
GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 0; // Asynch input
GpioDataRegs.GPASET.bit.GPIO2 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO2 = 0; // Clear output
//
// GPIO3
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0; // GPIO3
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Enable pullup on GPIO3
GpioCtrlRegs.GPADIR.bit.GPIO3 = 1; // GPIO3 = 0/1 - input/output
GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 0; // Asynch input
GpioDataRegs.GPASET.bit.GPIO3 = 0; //
GpioDataRegs.GPACLEAR.bit.GPIO3 = 0; // Clear output
//
//
// GPIO54
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 0; // GPIO54
GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pullup on GPIO54
GpioCtrlRegs.GPBDIR.bit.GPIO54 = 1; // GPIO54 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; // Asynch input
GpioDataRegs.GPBSET.bit.GPIO54 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO54 = 0; // Clear output
//
// GPIO56
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 0; // GPIO56
GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pullup on GPIO56
GpioCtrlRegs.GPBDIR.bit.GPIO56 = 1; // GPIO56 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 0; // Asynch input
GpioDataRegs.GPBSET.bit.GPIO56 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO56 = 0; // Clear output
//
// GPIO57
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 0; // GPIO57
GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pullup on GPIO57
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1; // GPIO57 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 0; // Asynch input
GpioDataRegs.GPBSET.bit.GPIO57 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO57 = 0; // Clear output
//
// GPIO58
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 0; // GPIO58
GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0; // Enable pullup on GPIO58
GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1; // GPIO58 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 0; // Asynch input
GpioDataRegs.GPBSET.bit.GPIO58 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO58 = 0; // Clear output
//
// GPIO61
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0; // GPIO61
GpioCtrlRegs.GPBPUD.bit.GPIO61 = 0; // Enable pullup on GPIO61
GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1; // GPIO61 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 0; // Asynch input
GpioDataRegs.GPBSET.bit.GPIO61 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO61 = 0; // Clear output
//
EDIS;
//
}//
//
void GPIO::ext_adc_start_convertion_setup()
{
EALLOW;
// GPIO33
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0; // GPIO33
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33
GpioCtrlRegs.GPBDIR.bit.GPIO33 = 1; // GPIO33 = 0/1 - input/output
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 0; // Asynch input
GpioDataRegs.GPBSET.bit.GPIO33 = 0; //
GpioDataRegs.GPBCLEAR.bit.GPIO33 = 0; // Clear output
//
EDIS;
//
}//
//
void GPIO::set_ext_adc_start_convertion()
{
//set GPIO33
GpioDataRegs.GPBSET.bit.GPIO33 = 1;
//
//
}//
//
void GPIO::clear_ext_adc_start_convertion()
{
//clear GPIO33
GpioDataRegs.GPBCLEAR.bit.GPIO33 = 1;
//
}//
//
void GPIO::gpio_hard_fault_setup()
{
EALLOW;
// GPIO4 - Fault A
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0; // GPIO4
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4
GpioCtrlRegs.GPADIR.bit.GPIO4 = 0; // GPIO4 = 0/1 - input/output
GpioCtrlRegs.GPAQSEL1.bit.GPIO4 = 0; // Asynch input
//
// GPIO6 - Fault B
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO6
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6
GpioCtrlRegs.GPADIR.bit.GPIO6 = 0; // GPIO6 = 0/1 - input/output
GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Asynch input
//
// GPIO8 - Fault C
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO8
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8
GpioCtrlRegs.GPADIR.bit.GPIO8 = 0; // GPIO8 = 0/1 - input/output
GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0; // Asynch input
//
EDIS;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void GPIO::gpio_hard_fault_read(uint16_t& data)
{
data = (uint16_t)((GpioDataRegs.GPADAT.bit.GPIO8 == 1 ? 0x4 : 0x0) |
(GpioDataRegs.GPADAT.bit.GPIO6 == 1 ? 0x2 : 0x0) |
(GpioDataRegs.GPADAT.bit.GPIO4 == 1 ? 0x1 : 0x0));
//
}//
//
//
// Analog Alarm Current Sensors
void GPIO::gpio_analog_fault_setup()
{
EALLOW;
// GPIO12 - Analog Alarm 21
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0; // GPIO12
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12
GpioCtrlRegs.GPADIR.bit.GPIO12 = 0; // GPIO4 = 0/1 - input/output
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Asynch input
//
// GPIO13 - Analog Alarm 22
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 0; // GPIO13
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pullup on GPIO13
GpioCtrlRegs.GPADIR.bit.GPIO13 = 0; // GPIO13 = 0/1 - input/output
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Asynch input
//
// GPIO20 - Analog Alarm 20
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 0; // GPIO20
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pullup on GPIO20
GpioCtrlRegs.GPADIR.bit.GPIO20 = 0; // GPIO20 = 0/1 - input/output
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Asynch input
//
EDIS;
//
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void GPIO::gpio_analog_fault_read(uint16_t& data)
{
data = (uint16_t)((GpioDataRegs.GPADAT.bit.GPIO12 == 1 ? 0x4 : 0x0) |
(GpioDataRegs.GPADAT.bit.GPIO13 == 1 ? 0x2 : 0x0) |
(GpioDataRegs.GPADAT.bit.GPIO20 == 1 ? 0x1 : 0x0));
//
}//
//
} /* namespace DSP28335 */

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DSP28335/GPIO.h
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/*
* GPIO.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/CPUBase.h"
#ifndef DSP28335_GPIO_H_
#define DSP28335_GPIO_H_
namespace DSP28335
{
typedef void (*pGPIO_FUNCTION)();
class GPIO: public DSP28335::CPUBase
{
public:
GPIO();
//EPWM
static void gpio_epwm_setup();
//
//CAN Inteface
static void gpio_cana_setup();
static void gpio_canb_setup();
//
//SCIA
static void gpio_scia_setup();
//
//RS485 - SCIB external - HMI
static void gpio_scib_setup();
static void gpio_scib_re_de_setup();
static void gpio_scib_re_de_set();
static void gpio_scib_re_de_clear();
//
//RS485 - SCIC internal
static void gpio_scic_setup();
//
//FRAM - SPIA
static void gpio_spia_setup();
static void gpio_spia_write_protect_set();
static void gpio_spia_write_protect_clear();
//
// EQEP
static void gpio_eqep_setup();
//
// XINTF
static void gpio_xintf_16bit_setup();
static void gpio_xintf_32bit_setup();
//
// GPIO
static void gpio_dicrete_outputs_setup();
//
// EXTERNAL ADC
static void ext_adc_start_convertion_setup();
static void set_ext_adc_start_convertion();
static void clear_ext_adc_start_convertion();
//
// Hard Fault
static void gpio_hard_fault_setup();
static void gpio_hard_fault_read(uint16_t& data);
//
// Analog Fault Current Sensors
static void gpio_analog_fault_setup();
static void gpio_analog_fault_read(uint16_t& data);
//
};//class GPIO()
} /* namespace DSP28335 */
#endif /* DSP28335_GPIO_H_ */

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DSP28335/MeasureTimeInterval.cpp
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/*
* MeasureTimeInterval.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/MeasureTimeInterval.h"
namespace DSP28335
{
//Constructor
MeasureTimeInterval::MeasureTimeInterval(CPUTIMER_VARS& CPUTimer):
m_CPUTimer(CPUTimer),
m_time_interval((Uint32)0),
m_time_interval_previous((Uint32)0),
m_magic_number((Uint32)0)
{}//end Constructor
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimeInterval::start(void)
{
m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer
m_CPUTimer.RegsAddr->TCR.bit.TRB = 1; // Reload CPU Timer
m_CPUTimer.RegsAddr->TCR.bit.TSS = 0; // Start CPU Timer
//
}//end
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimeInterval::stop(void)
{
m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer
//
m_time_interval_previous = m_time_interval;
m_time_interval = m_CPUTimer.RegsAddr->PRD.all - m_CPUTimer.RegsAddr->TIM.all - m_magic_number;
//
}//end
// #pragma CODE_SECTION("ramfuncs");
Uint32 MeasureTimeInterval::interval(void)
{
return m_CPUTimer.RegsAddr->PRD.all - m_CPUTimer.RegsAddr->TIM.all - m_magic_number;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimeInterval::reset(void)
{
m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer
m_CPUTimer.RegsAddr->PRD.all = 0xFFFFFFFF;
m_CPUTimer.RegsAddr->TCR.bit.TRB = 1; // Reload CPU Timer
//
}//end
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimeInterval::inc_counter()
{
m_CPUTimer.InterruptCount++;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimeInterval::reset_counter()
{
m_CPUTimer.InterruptCount = (Uint32)0;
//
}//
//
void MeasureTimeInterval::set_magic(const Uint32 magic)
{
m_magic_number = (Uint32)magic;
//
}//end
//
} /* namespace DSP28335 */

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DSP28335/MeasureTimeInterval.h
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/*
* MeasureTimeInterval.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#ifndef DSP28335_TIMEINTERVAL_H_
#define DSP28335_TIMEINTERVAL_H_
namespace DSP28335
{
class MeasureTimeInterval
{
private:
CPUTIMER_VARS& m_CPUTimer;
Uint32 m_time_interval;
Uint32 m_time_interval_previous;
Uint32 m_magic_number;
public:
MeasureTimeInterval(CPUTIMER_VARS& CPUTimer);
public:
void start(void);
void stop(void);
Uint32 interval(void);
void reset(void);
void inc_counter();
void reset_counter();
void set_magic(const Uint32 magic);
//
};//end class MeasureTimeStartStop
} /* namespace DSP28335 */
#endif /* DSP28335_TIMEINTERVAL_H_ */

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DSP28335/MeasureTimePeriod.cpp
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/*
* MeasureTimePeriod.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/MeasureTimePeriod.h"
namespace DSP28335
{
//Constructor
MeasureTimePeriod::MeasureTimePeriod(CPUTIMER_VARS& CPUTimer):
m_CPUTimer(CPUTimer),
m_timer_result((Uint32)0),
m_timer_result_previous((Uint32)0),
m_magic_number((Uint32)0),
_execute(&DSP28335::MeasureTimePeriod::_execute_start)
//
{}//end Constructor
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::execute(void)
{
(this->*_execute)();
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::reset(void)
{
m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer
m_CPUTimer.RegsAddr->PRD.all = 0xFFFFFFFF;
m_CPUTimer.RegsAddr->TCR.bit.TRB = 1; // Reload CPU Timer
//
_execute = &DSP28335::MeasureTimePeriod::_execute_start;
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::inc_counter()
{
m_CPUTimer.InterruptCount++;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::reset_counter()
{
m_CPUTimer.InterruptCount = (Uint32)0;
//
}//
//
void MeasureTimePeriod::set_magic(const Uint32 magic)
{
m_magic_number = (Uint32)magic;
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::_execute_start(void)
{
_execute = &DSP28335::MeasureTimePeriod::_execute_scan;
//
m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer
m_CPUTimer.RegsAddr->TCR.bit.TRB = 1; // Reload CPU Timer
m_CPUTimer.RegsAddr->TCR.bit.TSS = 0; // Start CPU Timer
//
}//end
//
// #pragma CODE_SECTION("ramfuncs");
void MeasureTimePeriod::_execute_scan(void)
{
m_CPUTimer.RegsAddr->TCR.bit.TSS = 1; // Stop CPU Timer
//
m_timer_result_previous = m_timer_result;
m_timer_result = m_CPUTimer.RegsAddr->PRD.all - m_CPUTimer.RegsAddr->TIM.all - m_magic_number;
//
m_CPUTimer.RegsAddr->TCR.bit.TRB = 1; // Reload CPU Timer
m_CPUTimer.RegsAddr->TCR.bit.TSS = 0; // Start CPU Timer
//
}//end
//
} /* namespace DSP28335 */

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DSP28335/MeasureTimePeriod.h
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/*
* MeasureTimePeriod.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#ifndef DSP28335_MEASURETIMEPERIOD_H_
#define DSP28335_MEASURETIMEPERIOD_H_
namespace DSP28335
{
class MeasureTimePeriod
{
private:
CPUTIMER_VARS& m_CPUTimer;
Uint32 m_timer_result;
Uint32 m_timer_result_previous;
Uint32 m_magic_number;
public:
MeasureTimePeriod(CPUTIMER_VARS& pCPUTimer);
void execute(void);
void reset(void);
void inc_counter();
void reset_counter();
void set_magic(const Uint32 magic);
private:
void (MeasureTimePeriod::*_execute)(void);
void _execute_start(void);
void _execute_scan(void);
//
};//end class MeasureTimePeriod
} /* namespace DSP28335 */
#endif /* DSP28335_MEASURETIMEPERIOD_H_ */

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DSP28335/MemoryZone.h
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/*
* MemoryZone.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include <stdint.h>
#ifndef SYSCTRL_MEMORYZONE_H_
#define SYSCTRL_MEMORYZONE_H_
struct ZONE_REGISTER_16_BIT_FIELD
{
uint16_t b0: 1;
uint16_t b1: 1;
uint16_t b2: 1;
uint16_t b3: 1;
uint16_t b4: 1;
uint16_t b5: 1;
uint16_t b6: 1;
uint16_t b7: 1;
uint16_t b8: 1;
uint16_t b9: 1;
uint16_t bA: 1;
uint16_t bB: 1;
uint16_t bC: 1;
uint16_t bD: 1;
uint16_t bE: 1;
uint16_t bF: 1;
};//ZONE_REGISTER_16_BIT_FIELD
struct ZONE_REGISTER_16_BYTE_FIELD
{
uint16_t bt0 :8;
uint16_t bt1 :8;
};//ZONE_REGISTER_16_BYTE_FIELD
union ZONE_REGISTER_16
{
uint16_t u16;
int16_t i16;
ZONE_REGISTER_16_BIT_FIELD bit;
ZONE_REGISTER_16_BYTE_FIELD byte;
};//REGISTER_16
#endif /* SYSCTRL_MEMORYZONE_H_ */

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DSP28335/MemoryZone0.h
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/*
* MemoryZone0.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/MemoryZone.h"
#include <stdint.h>
#ifndef SYSCTRL_MEMORYZONE0_H_
#define SYSCTRL_MEMORYZONE0_H_
struct ZONE0_Bank_H
{
ZONE_REGISTER_16 h0;
ZONE_REGISTER_16 h1;
ZONE_REGISTER_16 h2;
ZONE_REGISTER_16 h3;
ZONE_REGISTER_16 h4;
ZONE_REGISTER_16 h5;
ZONE_REGISTER_16 h6;
ZONE_REGISTER_16 h7;
ZONE_REGISTER_16 h8;
ZONE_REGISTER_16 h9;
ZONE_REGISTER_16 hA;
ZONE_REGISTER_16 hB;
ZONE_REGISTER_16 hC;
ZONE_REGISTER_16 hD;
ZONE_REGISTER_16 hE;
ZONE_REGISTER_16 hF;
};//
struct ZONE0_Bank_HH
{
ZONE0_Bank_H hh0;
ZONE0_Bank_H hh1;
ZONE0_Bank_H hh2;
ZONE0_Bank_H hh3;
ZONE0_Bank_H hh4;
ZONE0_Bank_H hh5;
ZONE0_Bank_H hh6;
ZONE0_Bank_H hh7;
ZONE0_Bank_H hh8;
ZONE0_Bank_H hh9;
ZONE0_Bank_H hhA;
ZONE0_Bank_H hhB;
ZONE0_Bank_H hhC;
ZONE0_Bank_H hhD;
ZONE0_Bank_H hhE;
ZONE0_Bank_H hhF;
};//
struct ZONE0_Bank_HHH
{
ZONE0_Bank_HH hhh0;
ZONE0_Bank_HH hhh1;
ZONE0_Bank_HH hhh2;
ZONE0_Bank_HH hhh3;
ZONE0_Bank_HH hhh4;
ZONE0_Bank_HH hhh5;
ZONE0_Bank_HH hhh6;
ZONE0_Bank_HH hhh7;
ZONE0_Bank_HH hhh8;
ZONE0_Bank_HH hhh9;
ZONE0_Bank_HH hhhA;
ZONE0_Bank_HH hhhB;
ZONE0_Bank_HH hhhC;
ZONE0_Bank_HH hhhD;
ZONE0_Bank_HH hhhE;
ZONE0_Bank_HH hhhF;
};//
struct DATA_ZONE0_STRUCTURE
{
int16_t &cmpr_a;
int16_t &cmpr_b;
int16_t &cmpr_c;
DATA_ZONE0_STRUCTURE(int16_t &cmpa, int16_t &cmpb, int16_t &cmpc):
cmpr_a(cmpa),
cmpr_b(cmpb),
cmpr_c(cmpc)
{}
};//
struct ADC_ACCESS_STRUCTURE
{
int16_t *read_channel_a0;
int16_t *read_channel_a1;
int16_t *read_channel_b0;
int16_t *read_channel_b1;
int16_t *read_channel_c0;
int16_t *read_channel_c1;
};//
#endif /* SYSCTRL_MEMORYZONE0_H_ */

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/*
* MemoryZone7.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/MemoryZone.h"
#include <stdint.h>
#ifndef SYSCTRL_MEMORYZONE7_H_
#define SYSCTRL_MEMORYZONE7_H_
struct ZONE7_Bank_H
{
ZONE_REGISTER_16 h0;
ZONE_REGISTER_16 h1;
ZONE_REGISTER_16 h2;
ZONE_REGISTER_16 h3;
ZONE_REGISTER_16 h4;
ZONE_REGISTER_16 h5;
ZONE_REGISTER_16 h6;
ZONE_REGISTER_16 h7;
ZONE_REGISTER_16 h8;
ZONE_REGISTER_16 h9;
ZONE_REGISTER_16 hA;
ZONE_REGISTER_16 hB;
ZONE_REGISTER_16 hC;
ZONE_REGISTER_16 hD;
ZONE_REGISTER_16 hE;
ZONE_REGISTER_16 hF;
};//
struct ZONE7_Bank_HH
{
ZONE7_Bank_H hh0;
ZONE7_Bank_H hh1;
ZONE7_Bank_H hh2;
ZONE7_Bank_H hh3;
ZONE7_Bank_H hh4;
ZONE7_Bank_H hh5;
ZONE7_Bank_H hh6;
ZONE7_Bank_H hh7;
ZONE7_Bank_H hh8;
ZONE7_Bank_H hh9;
ZONE7_Bank_H hhA;
ZONE7_Bank_H hhB;
ZONE7_Bank_H hhC;
ZONE7_Bank_H hhD;
ZONE7_Bank_H hhE;
ZONE7_Bank_H hhF;
};//
struct ZONE7_Bank_HHH
{
ZONE7_Bank_HH hhh0;
ZONE7_Bank_HH hhh1;
ZONE7_Bank_HH hhh2;
ZONE7_Bank_HH hhh3;
};//
#endif /* SYSCTRL_MEMORYZONE7_H_ */

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/*
* SCIA.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/SCIA.h"
namespace DSP28335
{
//CONSTRUCTOR
SCIA::SCIA(volatile struct SCI_REGS& SciRegs):
DSP28335::SCIBase(SciRegs)
//
{
// set default
settings.config.baudrate = SCIA_BAUDRATE_DEFAULT;
settings.config.parity = SCIA_PARITY_DEFAULT;
settings.config.stopbits = SCIA_STOPBITS_DEFAULT;
settings.config.lenght = SCIA_LENGHT_DEFAULT;
settings.gpio_setup = SCIA_GPIO_SETUP_DEFAULT;
//
}//end CONSTRUCTOR
void SCIA::setup()
{
//
get_default_configuration(settings.config);
_configure(settings.config);
//
_gpio_setup = settings.gpio_setup;
(*_gpio_setup)();
//
}//
//
void SCIA::setup(DSP28335::SCISetup& setup)
{
settings = setup;
_configure(settings.config);
//
_gpio_setup = settings.gpio_setup;
(*_gpio_setup)();
//
}//
//
void SCIA::get_default_configuration(DSP28335::SCIConfiguration& config)
{
config.baudrate = SCIA_BAUDRATE_DEFAULT;
config.parity = SCIA_PARITY_DEFAULT;
config.stopbits = SCIA_STOPBITS_DEFAULT;
config.lenght = SCIA_LENGHT_DEFAULT;
//
}//
//
void SCIA::get_configuration(DSP28335::SCIConfiguration& config)
{
config = settings.config;
//
}//
//
void SCIA::set_configuration(DSP28335::SCIConfiguration& config)
{
settings.config = config;
_configure(settings.config);
//
}//
//
bool SCIA::compare_configuration(DSP28335::SCIConfiguration& config)
{
return (settings.config.baudrate == config.baudrate)
& (settings.config.parity == config.parity)
& (settings.config.stopbits == config.stopbits)
& (settings.config.lenght == config.lenght);
//
}//
//
void SCIA::_configure(DSP28335::SCIConfiguration& config)
{
//
// SCICTL1.5 - Software reset 0/1-reset/active state
SciRegs.SCICTL1.bit.SWRESET = 0x000;
//
// Reset FIFO's
SciRegs.SCIFFTX.all=0x8000;
//
// SCICCR.7 - Number of stop bits
if(config.stopbits == DSP28335::ONE){ SciRegs.SCICCR.bit.STOPBITS = 0x00;}
if(config.stopbits == DSP28335::TWO){ SciRegs.SCICCR.bit.STOPBITS = 0x01;}
//
// SCICCR.5 - Parity enable
// SCICCR.6 - Parity odd/even
if(config.parity == DSP28335::NO){ SciRegs.SCICCR.bit.PARITYENA = 0x00; SciRegs.SCICCR.bit.PARITY = 0x00;}
if(config.parity == DSP28335::ODD){ SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x00;}
if(config.parity == DSP28335::EVEN){ SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x01;}
//
// SCICCR.4 - Loop Back test mode enable
SciRegs.SCICCR.bit.LOOPBKENA = 0x00;
//
// SCICCR.3 - Idle - Address mode protocol
SciRegs.SCICCR.bit.ADDRIDLE_MODE = 0x00;
//
// SCICCR.2-0 - Character-length
if(config.lenght == DSP28335::LEN1){ SciRegs.SCICCR.bit.SCICHAR = 0x00;}
if(config.lenght == DSP28335::LEN2){ SciRegs.SCICCR.bit.SCICHAR = 0x01;}
if(config.lenght == DSP28335::LEN3){ SciRegs.SCICCR.bit.SCICHAR = 0x02;}
if(config.lenght == DSP28335::LEN4){ SciRegs.SCICCR.bit.SCICHAR = 0x03;}
if(config.lenght == DSP28335::LEN5){ SciRegs.SCICCR.bit.SCICHAR = 0x04;}
if(config.lenght == DSP28335::LEN6){ SciRegs.SCICCR.bit.SCICHAR = 0x05;}
if(config.lenght == DSP28335::LEN7){ SciRegs.SCICCR.bit.SCICHAR = 0x06;}
if(config.lenght == DSP28335::LEN8){ SciRegs.SCICCR.bit.SCICHAR = 0x07;}
//
// SCICTL1.6 - Receive error interrupt enable
SciRegs.SCICTL1.bit.RXERRINTENA =0x000;
//
SciRegs.SCICTL1.bit.RXENA =0x001; // Receiver enable
SciRegs.SCICTL1.bit.TXENA =0x001; // Transmitter enable
SciRegs.SCICTL1.bit.SLEEP =0x000; // Sleep 0/1 - disable/enable
SciRegs.SCICTL1.bit.TXWAKE =0x000; // Transmitter wake-up method select
SciRegs.SCICTL2.bit.TXINTENA =0x0001; // SCITXBUF-register interrupt enable
SciRegs.SCICTL2.bit.RXBKINTENA =0x001; // Receiver-buffer/break interrupt enable
// Ideal Baud BRR Actual Baud Error, %
// 2400 1952(07A0h) 2400 0
// 4800 976(03D0h) 4798 -0,04
// 9600 487(01E7h) 9606 0.06
// 19200 243(00F3h) 19211 0.06
// 38400 121(0079h) 38422 0.006
if(config.baudrate == DSP28335::BR2400){ SciRegs.SCIHBAUD = 0x0007; SciRegs.SCILBAUD = 0x00A0;}
if(config.baudrate == DSP28335::BR4800){ SciRegs.SCIHBAUD = 0x0003; SciRegs.SCILBAUD = 0x00D0;}
if(config.baudrate == DSP28335::BR9600){ SciRegs.SCIHBAUD = 0x0001; SciRegs.SCILBAUD = 0x00E7;}
if(config.baudrate == DSP28335::BR19200){ SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x00F3;}
if(config.baudrate == DSP28335::BR38400){ SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x0079;}
// SCICTL1.5 - Relinquish SCI from Reset
SciRegs.SCICTL1.bit.SWRESET =0x001;
//
}//
//
} /* namespace DSP28335 */

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/*
* SCIA.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/SCIBase.h"
#ifndef DSP28335_SCIA_H_
#define DSP28335_SCIA_H_
#ifndef SCIA_BAUDRATE_DEFAULT
#define SCIA_BAUDRATE_DEFAULT (DSP28335::BR9600)
#endif
#ifndef SCIA_PARITY_DEFAULT
#define SCIA_PARITY_DEFAULT (DSP28335::NO)
//#define SCIA_PARITY_DEFAULT (DSP28335::ODD)
//#define SCIA_PARITY_DEFAULT (DSP28335::EVEN)
#endif
#ifndef SCIA_STOPBITS_DEFAULT
#define SCIA_STOPBITS_DEFAULT (DSP28335::ONE)
#endif
#ifndef SCIA_LENGHT_DEFAULT
#define SCIA_LENGHT_DEFAULT (DSP28335::LEN8)
#endif
#ifndef SCIA_GPIO_SETUP_DEFAULT
#define SCIA_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_scia_setup)
#endif
namespace DSP28335
{
class SCIA: public DSP28335::SCIBase
{
public:
SCIA(volatile struct SCI_REGS& SciRegs);
void setup();
void setup(DSP28335::SCISetup& setup);
void get_default_configuration(DSP28335::SCIConfiguration& config);
void get_configuration(DSP28335::SCIConfiguration& config);
void set_configuration(DSP28335::SCIConfiguration& config);
bool compare_configuration(DSP28335::SCIConfiguration& config);
protected:
void _configure(DSP28335::SCIConfiguration& config);
//
};//end class SCIA
} /* namespace DSP28335 */
#endif /* DSP28335_SCIA_H_ */

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/*
* SCIB.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/SCIB.h"
namespace DSP28335
{
//CONSTRUCTOR
SCIB::SCIB(volatile struct SCI_REGS& SciRegs):
DSP28335::SCIBase(SciRegs)
{
// set default
settings.config.baudrate = SCIB_BAUDRATE_DEFAULT;
settings.config.parity = SCIB_PARITY_DEFAULT;
settings.config.stopbits = SCIB_STOPBITS_DEFAULT;
settings.config.lenght = SCIB_LENGHT_DEFAULT;
settings.gpio_setup = SCIB_GPIO_SETUP_DEFAULT;
//
}//CONSTRUCTOR
//
void SCIB::setup()
{
//
get_default_configuration(settings.config);
_configure(settings.config);
//
_gpio_setup = settings.gpio_setup;
(*_gpio_setup)();
//
}//
//
void SCIB::setup(DSP28335::SCISetup& setup)
{
settings = setup;
_configure(settings.config);
_gpio_setup = settings.gpio_setup;
(*_gpio_setup)();
}//
//
void SCIB::get_default_configuration(DSP28335::SCIConfiguration& config)
{
config.baudrate = SCIB_BAUDRATE_DEFAULT;
config.parity = SCIB_PARITY_DEFAULT;
config.stopbits = SCIB_STOPBITS_DEFAULT;
config.lenght = SCIB_LENGHT_DEFAULT;
//
}//
//
void SCIB::get_configuration(DSP28335::SCIConfiguration& config)
{
config = settings.config;
//
}//
//
void SCIB::set_configuration(DSP28335::SCIConfiguration& config)
{
settings.config = config;
_configure(settings.config);
//
}//
//
bool SCIB::compare_configuration(DSP28335::SCIConfiguration& config)
{
return (settings.config.baudrate == config.baudrate)
& (settings.config.parity == config.parity)
& (settings.config.stopbits == config.stopbits)
& (settings.config.lenght == config.lenght);
//
}//
//
void SCIB::_configure(DSP28335::SCIConfiguration& config)
{
//
// SCICTL1.5 - Software reset 0/1-reset/active state
//m_sci_regs.SCICTL1.bit.SWRESET = 0x000;
SciRegs.SCICTL1.bit.SWRESET = 0x000;
//
// Reset FIFO's
SciRegs.SCIFFTX.all=0x8000;
//
// SCICCR.7 - Number of stop bits
switch(config.stopbits)
{
case DSP28335::ONE: { SciRegs.SCICCR.bit.STOPBITS = 0x00; break;}
case DSP28335::TWO: { SciRegs.SCICCR.bit.STOPBITS = 0x01; break;}
default: {break;}
}//switch
//
// SCICCR.5 - Parity enable
// SCICCR.6 - Parity odd/even
switch(config.parity)
{
case DSP28335::NO: {SciRegs.SCICCR.bit.PARITYENA = 0x00; SciRegs.SCICCR.bit.PARITY = 0x00; break;}
case DSP28335::ODD: {SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x00; break;}
case DSP28335::EVEN: {SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x01; break;}
default: {break;}
}//switch
//
// SCICCR.4 - Loop Back test mode enable
SciRegs.SCICCR.bit.LOOPBKENA = 0x00;
//
// SCICCR.3 - Idle - Address mode protocol
SciRegs.SCICCR.bit.ADDRIDLE_MODE = 0x00;
//
// SCICCR.2-0 - Character-length
switch(config.lenght)
{
case DSP28335::LEN1: {SciRegs.SCICCR.bit.SCICHAR = 0x00; break;}
case DSP28335::LEN2: {SciRegs.SCICCR.bit.SCICHAR = 0x01; break;}
case DSP28335::LEN3: {SciRegs.SCICCR.bit.SCICHAR = 0x02; break;}
case DSP28335::LEN4: {SciRegs.SCICCR.bit.SCICHAR = 0x03; break;}
case DSP28335::LEN5: {SciRegs.SCICCR.bit.SCICHAR = 0x04; break;}
case DSP28335::LEN6: {SciRegs.SCICCR.bit.SCICHAR = 0x05; break;}
case DSP28335::LEN7: {SciRegs.SCICCR.bit.SCICHAR = 0x06; break;}
case DSP28335::LEN8: {SciRegs.SCICCR.bit.SCICHAR = 0x07; break;}
default: {break;}
}//switch
//
// SCICTL1.6 - Receive error interrupt enable
SciRegs.SCICTL1.bit.RXERRINTENA =0x000;
//
SciRegs.SCICTL1.bit.RXENA =0x001; // Receiver enable
SciRegs.SCICTL1.bit.TXENA =0x001; // Transmitter enable
SciRegs.SCICTL1.bit.SLEEP =0x000; // Sleep 0/1 - disable/enable
SciRegs.SCICTL1.bit.TXWAKE =0x000; // Transmitter wake-up method select
SciRegs.SCICTL2.bit.TXINTENA =0x000; // SCITXBUF-register interrupt enable
SciRegs.SCICTL2.bit.RXBKINTENA =0x00; // Receiver-buffer/break interrupt enable
// Ideal Baud BRR Actual Baud Error, %
// 2400 1952(07A0h) 2400 0
// 4800 976(03D0h) 4798 -0,04
// 9600 487(01E7h) 9606 0.06
// 19200 243(00F3h) 19211 0.06
// 38400 121(0079h) 38422 0.006
switch(config.baudrate)
{
case DSP28335::BR2400: {SciRegs.SCIHBAUD = 0x0007; SciRegs.SCILBAUD = 0x00A0; break;}
case DSP28335::BR4800: {SciRegs.SCIHBAUD = 0x0003; SciRegs.SCILBAUD = 0x00D0; break;}
case DSP28335::BR9600: {SciRegs.SCIHBAUD = 0x0001; SciRegs.SCILBAUD = 0x00E7; break;}
case DSP28335::BR19200: {SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x00F3; break;}
case DSP28335::BR38400: {SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x0079; break;}
default: {break;}
}//switch
// SCICTL1.5 - Relinquish SCI from Reset
SciRegs.SCICTL1.bit.SWRESET =0x001;
//
}//
//
} /* namespace DSP28335 */

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/*
* SCIB.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/SCIBase.h"
#ifndef DSP28335_SCIB_H_
#define DSP28335_SCIB_H_
#ifndef SCIB_BAUDRATE_DEFAULT
#define SCIB_BAUDRATE_DEFAULT (DSP28335::BR9600)
#endif
#ifndef SCIB_PARITY_DEFAULT
#define SCIB_PARITY_DEFAULT (DSP28335::NO)
//#define SCIB_PARITY_DEFAULT (DSP28335::ODD)
//#define SCIB_PARITY_DEFAULT (DSP28335::EVEN)
#endif
#ifndef SCIB_STOPBITS_DEFAULT
#define SCIB_STOPBITS_DEFAULT (DSP28335::ONE)
#endif
#ifndef SCIB_LENGHT_DEFAULT
#define SCIB_LENGHT_DEFAULT (DSP28335::LEN8)
#endif
#ifndef SCIB_GPIO_SETUP_DEFAULT
#define SCIB_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_scib_setup)
#endif
namespace DSP28335
{
class SCIB: public SCIBase
{
public:
SCIB(volatile struct SCI_REGS& SciRegs);
void setup();
void setup(DSP28335::SCISetup& setup);
void get_default_configuration(DSP28335::SCIConfiguration& config);
void get_configuration(DSP28335::SCIConfiguration& config);
void set_configuration(DSP28335::SCIConfiguration& config);
bool compare_configuration(DSP28335::SCIConfiguration& config);
protected:
void _configure(DSP28335::SCIConfiguration& config);
};//SCIB
} /* namespace DSP28335 */
#endif /* DSP28335_SCIB_H_ */

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/*
* SCIBase.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/SCIBase.h"
namespace DSP28335
{
SCIBase::SCIBase(volatile struct SCI_REGS& SciRegs):
SciRegs(SciRegs),
settings(),
_gpio_setup(0)
//
{}//CONSTRUCTOR
//
} /* namespace DSP28335 */

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/*
* SCIBase.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/GPIO.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef DSP28335_SCIBASE_H_
#define DSP28335_SCIBASE_H_
namespace DSP28335
{
enum SCIBaudRate { BR2400, BR4800, BR9600, BR19200, BR38400};
enum SCIParity {NO, ODD, EVEN};
enum SCIStopBits {ONE, TWO};
enum SCICharLenght { LEN1, LEN2, LEN3, LEN4, LEN5, LEN6, LEN7, LEN8};
struct SCIConfiguration
{
DSP28335::SCIBaudRate baudrate;
DSP28335::SCIParity parity;
DSP28335::SCIStopBits stopbits;
DSP28335::SCICharLenght lenght;
SCIConfiguration():
baudrate(DSP28335::BR9600),
parity(DSP28335::ODD),
stopbits(DSP28335::ONE),
lenght(DSP28335::LEN8)
{}
};//
struct SCISetup
{
SCIConfiguration config;
pGPIO_FUNCTION gpio_setup;
SCISetup():
config(),
gpio_setup(0)
{}
};//
class SCIBase
{
public:
volatile struct SCI_REGS& SciRegs;
protected:
SCISetup settings;
public:
SCIBase(volatile struct SCI_REGS& SciRegs);
virtual void setup() = 0;
//virtual void setup(DSP28335::SCISetup& setup) = 0;
virtual void get_default_configuration(DSP28335::SCIConfiguration& config) = 0;
virtual void get_configuration(DSP28335::SCIConfiguration& config) = 0;
virtual void set_configuration(DSP28335::SCIConfiguration& config) = 0;
virtual bool compare_configuration(DSP28335::SCIConfiguration& config) = 0;
protected:
virtual void _configure(DSP28335::SCIConfiguration& config) = 0;
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_SCIBASE_H_ */

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/*
* SCIC.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/SCIC.h"
namespace DSP28335
{
//CONSTRUCTOR
SCIC::SCIC(volatile struct SCI_REGS& SciRegs):
DSP28335::SCIBase(SciRegs)
{
// set default
settings.config.baudrate = SCIC_BAUDRATE_DEFAULT;
settings.config.parity = SCIC_PARITY_DEFAULT;
settings.config.stopbits = SCIC_STOPBITS_DEFAULT;
settings.config.lenght = SCIC_LENGHT_DEFAULT;
settings.gpio_setup = SCIC_GPIO_SETUP_DEFAULT;
//
}//CONSTRUCTOR
void SCIC::setup()
{
//
get_default_configuration(settings.config);
_configure(settings.config);
//
_gpio_setup = settings.gpio_setup;
(*_gpio_setup)();
//
}//
//
void SCIC::setup(DSP28335::SCISetup& setup)
{
settings = setup;
_configure(settings.config);
//
_gpio_setup = settings.gpio_setup;
(*_gpio_setup)();
//
}//
//
void SCIC::get_default_configuration(DSP28335::SCIConfiguration& config)
{
config.baudrate = SCIC_BAUDRATE_DEFAULT;
config.parity = SCIC_PARITY_DEFAULT;
config.stopbits = SCIC_STOPBITS_DEFAULT;
config.lenght = SCIC_LENGHT_DEFAULT;
//
}//
//
void SCIC::get_configuration(DSP28335::SCIConfiguration& config)
{
config = settings.config;
//
}//
//
void SCIC::set_configuration(DSP28335::SCIConfiguration& config)
{
settings.config = config;
_configure(settings.config);
//
}//
//
bool SCIC::compare_configuration(DSP28335::SCIConfiguration& config)
{
return (settings.config.baudrate == config.baudrate)
& (settings.config.parity == config.parity)
& (settings.config.stopbits == config.stopbits)
& (settings.config.lenght == config.lenght);
//
}//
//
void SCIC::_configure(DSP28335::SCIConfiguration& config)
{
//
// SCICTL1.5 - Software reset 0/1-reset/active state
SciRegs.SCICTL1.bit.SWRESET = 0x000;
//
// Reset FIFO's
SciRegs.SCIFFTX.all=0x8000;
//
// SCICCR.7 - Number of stop bits
if(config.stopbits == DSP28335::ONE){ SciRegs.SCICCR.bit.STOPBITS = 0x00;}
if(config.stopbits == DSP28335::TWO){ SciRegs.SCICCR.bit.STOPBITS = 0x01;}
//
// SCICCR.5 - Parity enable
// SCICCR.6 - Parity odd/even
if(config.parity == DSP28335::NO){ SciRegs.SCICCR.bit.PARITYENA = 0x00; SciRegs.SCICCR.bit.PARITY = 0x00;}
if(config.parity == DSP28335::ODD){ SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x00;}
if(config.parity == DSP28335::EVEN){ SciRegs.SCICCR.bit.PARITYENA = 0x01; SciRegs.SCICCR.bit.PARITY = 0x01;}
//
// SCICCR.4 - Loop Back test mode enable
SciRegs.SCICCR.bit.LOOPBKENA = 0x00;
//
// SCICCR.3 - Idle - Address mode protocol
SciRegs.SCICCR.bit.ADDRIDLE_MODE = 0x00;
//
// SCICCR.2-0 - Character-length
if(config.lenght == DSP28335::LEN1){ SciRegs.SCICCR.bit.SCICHAR = 0x00;}
if(config.lenght == DSP28335::LEN2){ SciRegs.SCICCR.bit.SCICHAR = 0x01;}
if(config.lenght == DSP28335::LEN3){ SciRegs.SCICCR.bit.SCICHAR = 0x02;}
if(config.lenght == DSP28335::LEN4){ SciRegs.SCICCR.bit.SCICHAR = 0x03;}
if(config.lenght == DSP28335::LEN5){ SciRegs.SCICCR.bit.SCICHAR = 0x04;}
if(config.lenght == DSP28335::LEN6){ SciRegs.SCICCR.bit.SCICHAR = 0x05;}
if(config.lenght == DSP28335::LEN7){ SciRegs.SCICCR.bit.SCICHAR = 0x06;}
if(config.lenght == DSP28335::LEN8){ SciRegs.SCICCR.bit.SCICHAR = 0x07;}
//
// SCICTL1.6 - Receive error interrupt enable
SciRegs.SCICTL1.bit.RXERRINTENA =0x000;
//
SciRegs.SCICTL1.bit.RXENA =0x001; // Receiver enable
SciRegs.SCICTL1.bit.TXENA =0x001; // Transmitter enable
SciRegs.SCICTL1.bit.SLEEP =0x000; // Sleep 0/1 - disable/enable
SciRegs.SCICTL1.bit.TXWAKE =0x000; // Transmitter wake-up method select
SciRegs.SCICTL2.bit.TXINTENA =0x000; // SCITXBUF-register interrupt enable
SciRegs.SCICTL2.bit.RXBKINTENA =0x00; // Receiver-buffer/break interrupt enable
// Ideal Baud BRR Actual Baud Error, %
// 2400 1952(07A0h) 2400 0
// 4800 976(03D0h) 4798 -0,04
// 9600 487(01E7h) 9606 0.06
// 19200 243(00F3h) 19211 0.06
// 38400 121(0079h) 38422 0.006
if(config.baudrate == DSP28335::BR2400){ SciRegs.SCIHBAUD = 0x0007; SciRegs.SCILBAUD = 0x00A0;}
if(config.baudrate == DSP28335::BR4800){ SciRegs.SCIHBAUD = 0x0003; SciRegs.SCILBAUD = 0x00D0;}
if(config.baudrate == DSP28335::BR9600){ SciRegs.SCIHBAUD = 0x0001; SciRegs.SCILBAUD = 0x00E7;}
if(config.baudrate == DSP28335::BR19200){ SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x00F3;}
if(config.baudrate == DSP28335::BR38400){ SciRegs.SCIHBAUD = 0x0000; SciRegs.SCILBAUD = 0x0079;}
// SCICTL1.5 - Relinquish SCI from Reset
SciRegs.SCICTL1.bit.SWRESET =0x001;
//
}//
//
} /* namespace DSP28335 */

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/*
* SCIC.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/SCIBase.h"
#ifndef DSP28335_SCIC_H_
#define DSP28335_SCIC_H_
#ifndef SCIC_BAUDRATE_DEFAULT
#define SCIC_BAUDRATE_DEFAULT (DSP28335::BR9600)
#endif
#ifndef SCIC_PARITY_DEFAULT
#define SCIC_PARITY_DEFAULT (DSP28335::NO)
//#define SCIC_PARITY_DEFAULT (DSP28335::ODD)
//#define SCIC_PARITY_DEFAULT (DSP28335::EVEN)
#endif
#ifndef SCIC_STOPBITS_DEFAULT
#define SCIC_STOPBITS_DEFAULT (DSP28335::ONE)
#endif
#ifndef SCIC_LENGHT_DEFAULT
#define SCIC_LENGHT_DEFAULT (DSP28335::LEN8)
#endif
#ifndef SCIC_GPIO_SETUP_DEFAULT
#define SCIC_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_scic_setup)
#endif
namespace DSP28335
{
class SCIC: public SCIBase
{
public:
SCIC(volatile struct SCI_REGS& SciRegs);
void setup();
void setup(DSP28335::SCISetup& setup);
void get_default_configuration(DSP28335::SCIConfiguration& config);
void get_configuration(DSP28335::SCIConfiguration& config);
void set_configuration(DSP28335::SCIConfiguration& config);
bool compare_configuration(DSP28335::SCIConfiguration& config);
protected:
void _configure(DSP28335::SCIConfiguration& config);
};
} /* namespace DSP28335 */
#endif /* DSP28335_SCIC_H_ */

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/*
* SPIA.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/SPIA.h"
namespace DSP28335
{
//CONSTRUCTOR
SPIA::SPIA():
SPIBase(),
m_fifo_tx_status(0),
m_data_tx_len(0),
m_data_tx_counter(0),
m_fifo_tx(),
m_fifo_rx(),
_gpio_setup(SPIA_GPIO_SETUP_DEFAULT)
{}//CONSTRUCTOR
void SPIA::setup()
{
SpiaRegs.SPICCR.bit.SPISWRESET = 0; // Software Reset SPI
SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // Master
// FRAM MODE 0 - CLKPOLARITY = 0, CLK_PHASE = 0
//SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // Normal Clock Phase
//SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; // Shift Clock Polarity
// FRAM MODE 3 - CLKPOLARITY = 1, CLK_PHASE = 0
SpiaRegs.SPICTL.bit.CLK_PHASE = 0; // Normal Clock Phase
SpiaRegs.SPICCR.bit.CLKPOLARITY = 1; // Shift Clock Polarity
SpiaRegs.SPICCR.bit.SPILBK = 0; // Loopback
SpiaRegs.SPIBRR = 36; // Baud Rate = LSPCLK/(36+1) = 37.5MHz/(36+1) = 1MHz
SpiaRegs.SPICCR.bit.SPICHAR = 7; // 8-bit word
SpiaRegs.SPISTS.all = 0; // Clear OVERRUN_FLAG, INT_FLAG, BUFFULL_FLAG
// FIFO SPI
SpiaRegs.SPIFFTX.bit.SPIRST = 0; // Software reset FIFO SPI
SpiaRegs.SPIFFTX.bit.SPIFFENA = 1; // Enable SPI FIFO
SpiaRegs.SPIFFTX.bit.TXFIFO = 1; // Release TX FIFO from Reset
SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1; // TXFIFO Interrupt Clear
SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 1; // Receive FIFO Overflow Clear
SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1; // Receive FIFO Interrupt Clear
SpiaRegs.SPIFFTX.bit.TXFFIENA = 1; // TX FIFO Interrupt Enable
//SpiaRegs.SPIFFRX.bit.RXFFIENA = 1; // RX FIFO Interrupt Enable
SpiaRegs.SPIFFTX.bit.SPIRST = 1; // Release SPI FIFO
SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1; // Re-enable receive FIFO operation
SpiaRegs.SPICCR.bit.SPISWRESET = 1; // Release SPI
(*_gpio_setup)();
//
}//
//
void SPIA::setup(DSP28335::SPISetup& setup)
{
_gpio_setup = setup.gpio_setup;
(*_gpio_setup)();
//
}//
//
void SPIA::get_default_configuration(DSP28335::SPIConfiguration& config)
{
//
}//
//
void SPIA::get_configuration(DSP28335::SPIConfiguration& config)
{
//
}//
//
void SPIA::set_configuration(DSP28335::SPIConfiguration& config)
{
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void SPIA::clear_tx_interrupt()
{
// Interrupt acknowledge SPITXINTA
SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void SPIA::write(Uint16 data, Uint16 addr)
{
m_fifo_tx[0] = FRAM_OPCODE_WREN;
m_fifo_tx[1] = FRAM_OPCODE_WRITE;
m_fifo_tx[2] = addr & 0xff00;
m_fifo_tx[3] = (addr & 0x00ff) << 8;
m_fifo_tx[4] = data & 0xff00;
m_fifo_tx[5] = (data & 0x00ff) << 8;
m_fifo_tx[6] = 0;
m_fifo_tx[7] = 0;
m_fifo_tx[8] = 0;
m_fifo_tx[9] = 0;
m_fifo_tx[10] = 0;
m_fifo_tx[11] = 0;
m_fifo_tx[12] = 0;
m_fifo_tx[13] = 0;
m_fifo_tx[14] = 0;
m_fifo_tx[15] = 0;
//
m_data_tx_len = 6;
SpiaRegs.SPIFFTX.bit.TXFIFO = 0;
for(m_data_tx_counter = 0; m_data_tx_counter < m_data_tx_len; m_data_tx_counter++)
{
SpiaRegs.SPITXBUF = m_fifo_tx[m_data_tx_counter];
//
}//for
SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void SPIA::erase(Uint16 addr)
{
m_fifo_tx[0] = FRAM_OPCODE_WREN;
m_fifo_tx[1] = FRAM_OPCODE_WRITE;
m_fifo_tx[2] = addr & 0xff00;
m_fifo_tx[3] = (addr & 0x00ff) << 8;
m_fifo_tx[4] = FRAM_OPCODE_ERASE;
m_fifo_tx[5] = FRAM_OPCODE_ERASE;
m_fifo_tx[6] = 0;
m_fifo_tx[7] = 0;
m_fifo_tx[8] = 0;
m_fifo_tx[9] = 0;
m_fifo_tx[10] = 0;
m_fifo_tx[11] = 0;
m_fifo_tx[12] = 0;
m_fifo_tx[13] = 0;
m_fifo_tx[14] = 0;
m_fifo_tx[15] = 0;
//
m_data_tx_len = 6;
SpiaRegs.SPIFFTX.bit.TXFIFO = 0;
for(m_data_tx_counter = 0; m_data_tx_counter < m_data_tx_len; m_data_tx_counter++)
{
SpiaRegs.SPITXBUF = m_fifo_tx[m_data_tx_counter];
//
}//for
SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void SPIA::read(Uint16 addr)
{
m_fifo_tx[0] = FRAM_OPCODE_READ;
m_fifo_tx[1] = addr & 0xff00;
m_fifo_tx[2] = (addr & 0x00ff) << 8;
m_fifo_tx[3] = FRAM_OPCODE_DUMMY;
m_fifo_tx[4] = FRAM_OPCODE_DUMMY;
m_fifo_tx[5] = 0;
m_fifo_tx[6] = 0;
m_fifo_tx[7] = 0;
m_fifo_tx[8] = 0;
m_fifo_tx[9] = 0;
m_fifo_tx[10] = 0;
m_fifo_tx[11] = 0;
m_fifo_tx[12] = 0;
m_fifo_tx[13] = 0;
m_fifo_tx[14] = 0;
m_fifo_tx[15] = 0;
m_data_tx_len = 5;
SpiaRegs.SPIFFTX.bit.TXFIFO = 0;
for(m_data_tx_counter = 0; m_data_tx_counter < m_data_tx_len; m_data_tx_counter++)
{
SpiaRegs.SPITXBUF = m_fifo_tx[m_data_tx_counter];
m_fifo_tx[m_data_tx_counter] = 0;
//
}//for
SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
Uint16 SPIA::get_read_data()
{
m_fifo_rx[0] = SpiaRegs.SPIRXBUF;
m_fifo_rx[1] = SpiaRegs.SPIRXBUF;
m_fifo_rx[2] = SpiaRegs.SPIRXBUF;
m_fifo_rx[3] = SpiaRegs.SPIRXBUF;
m_fifo_rx[4] = SpiaRegs.SPIRXBUF;
m_fifo_rx[5] = 0;
m_fifo_rx[6] = 0;
m_fifo_rx[7] = 0;
m_fifo_rx[8] = 0;
m_fifo_rx[9] = 0;
m_fifo_rx[10] = 0;
m_fifo_rx[11] = 0;
m_fifo_rx[12] = 0;
m_fifo_rx[13] = 0;
m_fifo_rx[14] = 0;
m_fifo_rx[15] = 0;
//
return (Uint16)((m_fifo_rx[3] << 8) | (m_fifo_rx[4] & 0x00ff));
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
Uint16 SPIA::get_fifo_tx_status()
{
return m_fifo_tx_status = (Uint16)SpiaRegs.SPIFFTX.bit.TXFFST;
//
}//
//
void SPIA::_configure(DSP28335::SPIConfiguration& config)
{
//
}//
//
} /* namespace DSP28335 */

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/*
* SPIA.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/SPIBase.h"
#ifndef DSP28335_SPIA_H_
#define DSP28335_SPIA_H_
#ifndef SPIA_GPIO_SETUP_DEFAULT_DEFINES
#define SPIA_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_spia_setup)
#define SPIA_GPIO_SETUP_DEFAULT_DEFINES
#endif
#ifndef FRAM_OPCODE_WREN_DEFINES
#define FRAM_OPCODE_WREN (uint16_t)0x0600
#define FRAM_OPCODE_WREN_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRDI_DEFINES
#define FRAM_OPCODE_WRDI (uint16_t)0x0400
#define FRAM_OPCODE_WRDI_DEFINES
#endif
//
#ifndef FRAM_OPCODE_RDSR_DEFINES
#define FRAM_OPCODE_RDSR (uint16_t)0x0500
#define FRAM_OPCODE_RDSR_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRSR_DEFINES
#define FRAM_OPCODE_WRSR (uint16_t)0x0100
#define FRAM_OPCODE_WRSR_DEFINES
#endif
//
#ifndef FRAM_OPCODE_READ_DEFINES
#define FRAM_OPCODE_READ (uint16_t)0x0300
#define FRAM_OPCODE_READ_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRITE_DEFINES
#define FRAM_OPCODE_WRITE (uint16_t)0x0200
#define FRAM_OPCODE_WRITE_DEFINES
#endif
//
#ifndef FRAM_OPCODE_DUMMY_DEFINES
#define FRAM_OPCODE_DUMMY (uint16_t)0x5500
#define FRAM_OPCODE_DUMMY_DEFINES
#endif
//
#ifndef FRAM_OPCODE_ERASE_DEFINES
#define FRAM_OPCODE_ERASE (uint16_t)0xFF00
#define FRAM_OPCODE_ERASE_DEFINES
#endif
//
namespace DSP28335
{
class SPIA: public SPIBase
{
public:
enum mode_t {UNDEFINED=0, CONFIGURATE=1, OPERATIONAL=2};
private:
Uint16 m_fifo_tx_status;
Uint16 m_data_tx_len;
Uint16 m_data_tx_counter;
private:
Uint16 m_fifo_tx[16];
Uint16 m_fifo_rx[16];
public:
SPIA();
public:
void clear_tx_interrupt();
public:
void setup();
void setup(DSP28335::SPISetup& setup);
void get_default_configuration(DSP28335::SPIConfiguration& config);
void get_configuration(DSP28335::SPIConfiguration& config);
void set_configuration(DSP28335::SPIConfiguration& config);
public:
void write(Uint16 data, Uint16 addr);
void erase(Uint16 addr);
void read(Uint16 addr);
Uint16 get_read_data();
Uint16 get_fifo_tx_status();
private:
void _configure(DSP28335::SPIConfiguration& config);
void (*_gpio_setup)();
};
} /* namespace DSP28335 */
#endif /* DSP28335_SPIA_H_ */

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/*
* SPIBase.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/SPIBase.h"
namespace DSP28335
{
//CONSTRUCTOR
SPIBase::SPIBase()
{}//CONSTRUCTOR
} /* namespace DSP28335 */

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/*
* SPIBase.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/GPIO.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef DSP28335_SPIBASE_H_
#define DSP28335_SPIBASE_H_
namespace DSP28335
{
struct SPIConfiguration
{
SPIConfiguration(){}
};//
struct SPISetup
{
pGPIO_FUNCTION gpio_setup;
SPISetup():
gpio_setup(&DSP28335::GPIO::gpio_spia_setup)
{}
};//SPISetup
class SPIBase
{
public:
SPIBase();
public:
virtual void setup() = 0;
virtual void setup(DSP28335::SPISetup& setup) = 0;
virtual void get_default_configuration(DSP28335::SPIConfiguration& config) = 0;
virtual void get_configuration(DSP28335::SPIConfiguration& config) = 0;
virtual void set_configuration(DSP28335::SPIConfiguration& config) = 0;
protected:
virtual void _configure(DSP28335::SPIConfiguration& config) = 0;
};
} /* namespace DSP28335 */
#endif /* DSP28335_SPIBASE_H_ */

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/*
* XINTF.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/XINTF.h"
namespace DSP28335
{
//CONSTRUCTOR
XINTF::XINTF():
CPUBase(),
_gpio_setup(&DSP28335::GPIO::gpio_xintf_16bit_setup)
{}//CONSTRUCTOR
void XINTF::setup(DSP28335::XINTFSetup& setup)
{
if(m_mode == DSP28335::XINTF::UNDEFINED)
{
//
// This shows how to write to the XINTF registers. The
// values used here are the default state after reset.
// Different hardware will require a different configuration.
//
//
// Any changes to XINTF timing should only be made by code
// running outside of the XINTF.
//
//
// All Zones
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
//
//struct XINTCNF2_BITS { // bits description
// Uint16 WRBUFF:2; // 1:0 Write buffer depth
// Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
// Uint16 CLKOFF:1; // 3 Disable XCLKOUT
// Uint16 rsvd1:2; // 5:4 reserved
// Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
// Uint16 rsvd2:1; // 8 reserved
// Uint16 HOLD:1; // 9 Hold enable/disable
// Uint16 HOLDS:1; // 10 Current state of HOLDn input
// Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
// Uint16 rsvd3:4; // 15:12 reserved
// Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
// Uint16 rsvd4:13; // 31:19 reserved
//};
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
//
// No write buffering
//
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
//
// XCLKOUT is enabled
//
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
//
// XCLKOUT = XTIMCLK/2
//
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
//
// WLEVEL
//
XintfRegs.XINTCNF2.bit.WLEVEL = 0;
//
// HOLD
//
XintfRegs.XINTCNF2.bit.HOLD = 0;
//
// HOLDS
//
XintfRegs.XINTCNF2.bit.HOLDS = 1;
//
// HOLDAS
//
XintfRegs.XINTCNF2.bit.HOLDAS = 1;
//
// Zone 0
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
//
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
XintfRegs.XTIMING0.bit.XWRACTIVE = 5; // default 7;
XintfRegs.XTIMING0.bit.XWRTRAIL = 1; // default 3;
//
// Zone read timing
//
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE = 5; // default 7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 1; // default 3;
//
// double all Zone read/write lead/active/trail timing
//
XintfRegs.XTIMING0.bit.X2TIMING = 1;
//
// Zone will sample XREADY signal
//
XintfRegs.XTIMING0.bit.USEREADY = 1;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
//
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
//
XintfRegs.XTIMING0.bit.XSIZE = 3;
//
// Zone 6
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
//
XintfRegs.XTIMING6.bit.XWRLEAD = 3;
XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
//
// Zone read timing
//
XintfRegs.XTIMING6.bit.XRDLEAD = 3;
XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
//
// double all Zone read/write lead/active/trail timing
//
XintfRegs.XTIMING6.bit.X2TIMING = 1;
//
// Zone will sample XREADY signal
//
XintfRegs.XTIMING6.bit.USEREADY = 1;
XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
//
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
//
XintfRegs.XTIMING6.bit.XSIZE = 3;
//
// Zone 7
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
//
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
//
// Zone read timing
//
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
//
// double all Zone read/write lead/active/trail timing
//
XintfRegs.XTIMING7.bit.X2TIMING = 1;
//
// Zone will sample XREADY signal
//
XintfRegs.XTIMING7.bit.USEREADY = 1;
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
//
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
//
XintfRegs.XTIMING7.bit.XSIZE = 3;
//
// Bank switching
// Assume Zone 7 is slow, so add additional BCYC cycles
// when ever switching from Zone 7 to another Zone.
// This will help avoid bus contention.
//
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;
EDIS;
//
// Force a pipeline flush to ensure that the write to the last register
// configured occurs before returning.
//
asm(" RPT #7 || NOP");
if(setup.gpio_setup != 0)
{
_gpio_setup = setup.gpio_setup;
//
(*_gpio_setup)();
//
m_mode = DSP28335::XINTF::OPERATIONAL;
m_status = true;
//
}//if
//
}//if
//
}//
//
} /* namespace DSP28335 */

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DSP28335/XINTF.h
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/*
* XINTF.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "F28335/DSP28x_Project.h"
#include "DSP28335/GPIO.h"
#include "DSP28335/CPUBase.h"
#ifndef DSP28335_XINTF_H_
#define DSP28335_XINTF_H_
namespace DSP28335
{
struct XINTFSetup
{
pGPIO_FUNCTION gpio_setup;
XINTFSetup():
gpio_setup(&DSP28335::GPIO::gpio_xintf_16bit_setup)
{}
};//
class XINTF: public CPUBase
{
public:
XINTF();
void setup(DSP28335::XINTFSetup& setup);
private:
void (*_gpio_setup)();
};//
} /* namespace DSP28335 */
#endif /* DSP28335_XINTF_H_ */

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F28335/DSP2833x_Adc.c
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//###########################################################################
//
// FILE: DSP2833x_Adc.c
//
// TITLE: DSP2833x ADC Initialization & Support Functions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
//
// Included Files
//
#include "F28335/DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "F28335/DSP2833x_Examples.h" // DSP2833x Examples Include File
//
// Defines
//
#define ADC_usDELAY 5000L
//
// InitAdc - This function initializes ADC to a known state.
//
void
InitAdc(void)
{
//extern void DSP28x_usDelay(Uint32 Count);
extern void DelayUs(Uint16);
//
// *IMPORTANT*
// The ADC_cal function, which copies the ADC calibration values from
// TI reserved OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs
// automatically in the Boot ROM. If the boot ROM code is bypassed during
// the debug process, the following function MUST be called for the ADC to
// function according to specification. The clocks to the ADC MUST be
// enabled before calling this function. See the device data manual and/or
// the ADC Reference Manual for more information.
//
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
ADC_cal();
EDIS;
//
// To powerup the ADC the ADCENCLK bit should be set first to enable
// clocks, followed by powering up the bandgap, reference circuitry, and
// ADC core. Before the first conversion is performed a 5ms delay must be
// observed after power up to give all analog circuits time to power up
// and settle
//
//
// Please note that for the delay function below to operate correctly the
// CPU_RATE define statement in the DSP2833x_Examples.h file must
// contain the correct CPU clock period in nanoseconds.
//
AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits
DELAY_US(5000); // Delay before converting ADC channels
//
}
//
// End of file
//

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F28335/DSP2833x_Adc.h
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//###########################################################################
//
// FILE: DSP2833x_Adc.h
//
// TITLE: DSP2833x Device ADC Register Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_ADC_H
#define DSP2833x_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
//
// ADC Individual Register Bit Definitions:
//
struct ADCTRL1_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
Uint16 SEQ_OVRD:1; // 5 Sequencer override
Uint16 CONT_RUN:1; // 6 Continuous run
Uint16 CPS:1; // 7 ADC core clock pre-scalar
Uint16 ACQ_PS:4; // 11:8 Acquisition window size
Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
Uint16 RESET:1; // 14 ADC reset
Uint16 rsvd2:1; // 15 reserved
};
union ADCTRL1_REG {
Uint16 all;
struct ADCTRL1_BITS bit;
};
struct ADCTRL2_BITS { // bits description
Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2
Uint16 rsvd1:1; // 1 reserved
Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode
Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable
Uint16 rsvd2:1; // 4 reserved
Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2
Uint16 RST_SEQ2:1; // 6 Reset SEQ2
Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1
Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1
Uint16 rsvd3:1; // 9 reserved
Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode
Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable
Uint16 rsvd4:1; // 12 reserved
Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1
Uint16 RST_SEQ1:1; // 14 Restart sequencer 1
Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable
};
union ADCTRL2_REG {
Uint16 all;
struct ADCTRL2_BITS bit;
};
struct ADCASEQSR_BITS { // bits description
Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state
Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state
Uint16 rsvd1:1; // 7 reserved
Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status
Uint16 rsvd2:4; // 15:12 reserved
};
union ADCASEQSR_REG {
Uint16 all;
struct ADCASEQSR_BITS bit;
};
struct ADCMAXCONV_BITS { // bits description
Uint16 MAX_CONV1:4; // 3:0 Max number of conversions
Uint16 MAX_CONV2:3; // 6:4 Max number of conversions
Uint16 rsvd1:9; // 15:7 reserved
};
union ADCMAXCONV_REG {
Uint16 all;
struct ADCMAXCONV_BITS bit;
};
struct ADCCHSELSEQ1_BITS { // bits description
Uint16 CONV00:4; // 3:0 Conversion selection 00
Uint16 CONV01:4; // 7:4 Conversion selection 01
Uint16 CONV02:4; // 11:8 Conversion selection 02
Uint16 CONV03:4; // 15:12 Conversion selection 03
};
union ADCCHSELSEQ1_REG{
Uint16 all;
struct ADCCHSELSEQ1_BITS bit;
};
struct ADCCHSELSEQ2_BITS { // bits description
Uint16 CONV04:4; // 3:0 Conversion selection 04
Uint16 CONV05:4; // 7:4 Conversion selection 05
Uint16 CONV06:4; // 11:8 Conversion selection 06
Uint16 CONV07:4; // 15:12 Conversion selection 07
};
union ADCCHSELSEQ2_REG{
Uint16 all;
struct ADCCHSELSEQ2_BITS bit;
};
struct ADCCHSELSEQ3_BITS { // bits description
Uint16 CONV08:4; // 3:0 Conversion selection 08
Uint16 CONV09:4; // 7:4 Conversion selection 09
Uint16 CONV10:4; // 11:8 Conversion selection 10
Uint16 CONV11:4; // 15:12 Conversion selection 11
};
union ADCCHSELSEQ3_REG{
Uint16 all;
struct ADCCHSELSEQ3_BITS bit;
};
struct ADCCHSELSEQ4_BITS { // bits description
Uint16 CONV12:4; // 3:0 Conversion selection 12
Uint16 CONV13:4; // 7:4 Conversion selection 13
Uint16 CONV14:4; // 11:8 Conversion selection 14
Uint16 CONV15:4; // 15:12 Conversion selection 15
};
union ADCCHSELSEQ4_REG {
Uint16 all;
struct ADCCHSELSEQ4_BITS bit;
};
struct ADCTRL3_BITS { // bits description
Uint16 SMODE_SEL:1; // 0 Sampling mode select
Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider
Uint16 ADCPWDN:1; // 5 ADC powerdown
Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down
Uint16 rsvd1:8; // 15:8 reserved
};
union ADCTRL3_REG {
Uint16 all;
struct ADCTRL3_BITS bit;
};
struct ADCST_BITS { // bits description
Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag
Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag
Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status
Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status
Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear
Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear
Uint16 EOS_BUF1:1; // 6 End of sequence buffer1
Uint16 EOS_BUF2:1; // 7 End of sequence buffer2
Uint16 rsvd1:8; // 15:8 reserved
};
union ADCST_REG {
Uint16 all;
struct ADCST_BITS bit;
};
struct ADCREFSEL_BITS { // bits description
Uint16 rsvd1:14; // 13:0 reserved
Uint16 REF_SEL:2; // 15:14 Reference select
};
union ADCREFSEL_REG {
Uint16 all;
struct ADCREFSEL_BITS bit;
};
struct ADCOFFTRIM_BITS{ // bits description
int16 OFFSET_TRIM:9; // 8:0 Offset Trim
Uint16 rsvd1:7; // 15:9 reserved
};
union ADCOFFTRIM_REG{
Uint16 all;
struct ADCOFFTRIM_BITS bit;
};
struct ADC_REGS {
union ADCTRL1_REG ADCTRL1; //ADC Control 1
union ADCTRL2_REG ADCTRL2; //ADC Control 2
union ADCMAXCONV_REG ADCMAXCONV; //Max conversions
union ADCCHSELSEQ1_REG ADCCHSELSEQ1; //Channel select sequencing control 1
union ADCCHSELSEQ2_REG ADCCHSELSEQ2; //Channel select sequencing control 2
union ADCCHSELSEQ3_REG ADCCHSELSEQ3; //Channel select sequencing control 3
union ADCCHSELSEQ4_REG ADCCHSELSEQ4; //Channel select sequencing control 4
union ADCASEQSR_REG ADCASEQSR; //Autosequence status register
Uint16 ADCRESULT0; //Conversion Result Buffer 0
Uint16 ADCRESULT1; //Conversion Result Buffer 1
Uint16 ADCRESULT2; //Conversion Result Buffer 2
Uint16 ADCRESULT3; //Conversion Result Buffer 3
Uint16 ADCRESULT4; //Conversion Result Buffer 4
Uint16 ADCRESULT5; //Conversion Result Buffer 5
Uint16 ADCRESULT6; //Conversion Result Buffer 6
Uint16 ADCRESULT7; //Conversion Result Buffer 7
Uint16 ADCRESULT8; //Conversion Result Buffer 8
Uint16 ADCRESULT9; //Conversion Result Buffer 9
Uint16 ADCRESULT10; //Conversion Result Buffer 10
Uint16 ADCRESULT11; //Conversion Result Buffer 11
Uint16 ADCRESULT12; //Conversion Result Buffer 12
Uint16 ADCRESULT13; //Conversion Result Buffer 13
Uint16 ADCRESULT14; //Conversion Result Buffer 14
Uint16 ADCRESULT15; //Conversion Result Buffer 15
union ADCTRL3_REG ADCTRL3; //ADC Control 3
union ADCST_REG ADCST; //ADC Status Register
Uint16 rsvd1;
Uint16 rsvd2;
union ADCREFSEL_REG ADCREFSEL; //Reference Select Register
union ADCOFFTRIM_REG ADCOFFTRIM; //Offset Trim Register
};
struct ADC_RESULT_MIRROR_REGS
{
Uint16 ADCRESULT0; // Conversion Result Buffer 0
Uint16 ADCRESULT1; // Conversion Result Buffer 1
Uint16 ADCRESULT2; // Conversion Result Buffer 2
Uint16 ADCRESULT3; // Conversion Result Buffer 3
Uint16 ADCRESULT4; // Conversion Result Buffer 4
Uint16 ADCRESULT5; // Conversion Result Buffer 5
Uint16 ADCRESULT6; // Conversion Result Buffer 6
Uint16 ADCRESULT7; // Conversion Result Buffer 7
Uint16 ADCRESULT8; // Conversion Result Buffer 8
Uint16 ADCRESULT9; // Conversion Result Buffer 9
Uint16 ADCRESULT10; // Conversion Result Buffer 10
Uint16 ADCRESULT11; // Conversion Result Buffer 11
Uint16 ADCRESULT12; // Conversion Result Buffer 12
Uint16 ADCRESULT13; // Conversion Result Buffer 13
Uint16 ADCRESULT14; // Conversion Result Buffer 14
Uint16 ADCRESULT15; // Conversion Result Buffer 15
};
//
// ADC External References & Function Declarations:
//
extern volatile struct ADC_REGS AdcRegs;
extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_ADC_H definition
//
// End of file
//

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F28335/DSP2833x_CpuTimers.h
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//###########################################################################
//
// FILE: DSP2833x_CpuTimers.h
//
// TITLE: DSP2833x CPU 32-bit Timers Register Definitions.
//
// NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and
// other realtime operating systems.
//
// Do not use these two timers in your application if you ever plan
// on integrating DSP-BIOS or another realtime OS.
//
// For this reason, comment out the code to manipulate these two
// timers if using DSP-BIOS or another realtime OS.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_CPU_TIMERS_H
#define DSP2833x_CPU_TIMERS_H
#ifdef __cplusplus
extern "C" {
#endif
//
// CPU Timer Register Bit Definitions
//
//
// TCR: Control register bit definitions
//
struct TCR_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 TSS:1; // 4 Timer Start/Stop
Uint16 TRB:1; // 5 Timer reload
Uint16 rsvd2:4; // 9:6 reserved
Uint16 SOFT:1; // 10 Emulation modes
Uint16 FREE:1; // 11
Uint16 rsvd3:2; // 12:13 reserved
Uint16 TIE:1; // 14 Output enable
Uint16 TIF:1; // 15 Interrupt flag
};
union TCR_REG {
Uint16 all;
struct TCR_BITS bit;
};
//
// TPR: Pre-scale low bit definitions
//
struct TPR_BITS { // bits description
Uint16 TDDR:8; // 7:0 Divide-down low
Uint16 PSC:8; // 15:8 Prescale counter low
};
union TPR_REG {
Uint16 all;
struct TPR_BITS bit;
};
//
// TPRH: Pre-scale high bit definitions
//
struct TPRH_BITS { // bits description
Uint16 TDDRH:8; // 7:0 Divide-down high
Uint16 PSCH:8; // 15:8 Prescale counter high
};
union TPRH_REG {
Uint16 all;
struct TPRH_BITS bit;
};
//
// TIM, TIMH: Timer register definitions
//
struct TIM_REG {
Uint16 LSW;
Uint16 MSW;
};
union TIM_GROUP {
Uint32 all;
struct TIM_REG half;
};
//
// PRD, PRDH: Period register definitions
//
struct PRD_REG {
Uint16 LSW;
Uint16 MSW;
};
union PRD_GROUP {
Uint32 all;
struct PRD_REG half;
};
//
// CPU Timer Register File
//
struct CPUTIMER_REGS {
union TIM_GROUP TIM; // Timer counter register
union PRD_GROUP PRD; // Period register
union TCR_REG TCR; // Timer control register
Uint16 rsvd1; // reserved
union TPR_REG TPR; // Timer pre-scale low
union TPRH_REG TPRH; // Timer pre-scale high
};
//
// CPU Timer Support Variables
//
struct CPUTIMER_VARS {
volatile struct CPUTIMER_REGS *RegsAddr;
Uint32 InterruptCount;
float CPUFreqInMHz;
float PeriodInUSec;
};
//
// Function prototypes and external definitions
//
void InitCpuTimers(void);
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period);
extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
extern struct CPUTIMER_VARS CpuTimer0;
//
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS.
// Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS
//
extern volatile struct CPUTIMER_REGS CpuTimer1Regs;
extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
extern struct CPUTIMER_VARS CpuTimer1;
extern struct CPUTIMER_VARS CpuTimer2;
//
// Defines for useful Timer Operations:
//
//
// Start Timer
//
#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0
//
// Stop Timer
//
#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1
//
// Reload Timer With period Value
//
#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1
//
// Read 32-Bit Timer Value
//
#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all
//
// Read 32-Bit Period Value
//
#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all
//
// CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS
// Do not use these two timers if you ever plan on integrating
// DSP-BIOS or another realtime OS.
//
// For this reason, comment out the code to manipulate these two timers
// if using DSP-BIOS or another realtime OS.
//
//
// Start Timer
//
#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0
#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0
//
// Stop Timer
//
#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1
#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1
//
// Reload Timer With period Value
//
#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1
#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1
//
// Read 32-Bit Timer Value
//
#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all
#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all
//
// Read 32-Bit Period Value
//
#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all
#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_CPU_TIMERS_H definition
//
// End of file
//

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F28335/DSP2833x_DMA.h
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//###########################################################################
//
// FILE: DSP2833x_DMA.h
//
// TITLE: DSP2833x DMA Module Register Bit Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_DMA_H
#define DSP2833x_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Channel MODE register bit definitions
//
struct MODE_BITS { // bits description
Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select Bits (R/W):
// 0 no interrupt
// 1 SEQ1INT & ADCSYNC
// 2 SEQ2INT
// 3 XINT1
// 4 XINT2
// 5 XINT3
// 6 XINT4
// 7 XINT5
// 8 XINT6
// 9 XINT7
// 10 XINT13
// 11 TINT0
// 12 TINT1
// 13 TINT2
// 14 MXEVTA & MXSYNCA
// 15 MREVTA & MRSYNCA
// 16 MXEVTB & MXSYNCB
// 17 MREVTB & MRSYNCB
// 18 ePWM1SOCA
// 19 ePWM1SOCB
// 20 ePWM2SOCA
// 21 ePWM2SOCB
// 22 ePWM3SOCA
// 23 ePWM3SOCB
// 24 ePWM4SOCA
// 25 ePWM4SOCB
// 26 ePWM5SOCA
// 27 ePWM5SOCB
// 28 ePWM6SOCA
// 29 ePWM6SOCB
// 30:31 no interrupt
Uint16 rsvd1:2; // 6:5 (R=0:0)
Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable (R/W):
// 0 overflow interrupt disabled
// 1 overflow interrupt enabled
Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable Bit (R/W):
// 0 peripheral interrupt disabled
// 1 peripheral interrupt enabled
Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode Bit (R/W):
// 0 generate interrupt at beginning of new
// transfer
// 1 generate interrupt at end of transfer
Uint16 ONESHOT:1; // 10 One Shot Mode Bit (R/W):
// 0 only interrupt event triggers single
// burst transfer
// 1 first interrupt triggers burst,
// continue until transfer count is zero
Uint16 CONTINUOUS:1;// 11 Continous Mode Bit (R/W):
// 0 stop when transfer count is zero
// 1 re-initialize when transfer count is
// zero
Uint16 SYNCE:1; // 12 Sync Enable Bit (R/W):
// 0 ignore selected interrupt sync signal
// 1 enable selected interrupt sync signal
Uint16 SYNCSEL:1; // 13 Sync Select Bit (R/W):
// 0 sync signal controls source wrap
// counter
// 1 sync signal controls destination wrap
// counter
Uint16 DATASIZE:1; // 14 Data Size Mode Bit (R/W):
// 0 16-bit data transfer size
// 1 32-bit data transfer size
Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit (R/W):
// 0 channel interrupt disabled
// 1 channel interrupt enabled
};
union MODE_REG {
Uint16 all;
struct MODE_BITS bit;
};
//
// Channel CONTROL register bit definitions
//
struct CONTROL_BITS { // bits description
Uint16 RUN:1; // 0 Run Bit (R=0/W=1)
Uint16 HALT:1; // 1 Halt Bit (R=0/W=1)
Uint16 SOFTRESET:1; // 2 Soft Reset Bit (R=0/W=1)
Uint16 PERINTFRC:1; // 3 Interrupt Force Bit (R=0/W=1)
Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit (R=0/W=1)
Uint16 SYNCFRC:1; // 5 Sync Force Bit (R=0/W=1)
Uint16 SYNCCLR:1; // 6 Sync Clear Bit (R=0/W=1)
Uint16 ERRCLR:1; // 7 Error Clear Bit (R=0/W=1)
Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit (R):
// 0 no interrupt pending
// 1 interrupt pending
Uint16 SYNCFLG:1; // 9 Sync Flag Bit (R):
// 0 no sync pending
// 1 sync pending
Uint16 SYNCERR:1; // 10 Sync Error Flag Bit (R):
// 0 no sync error
// 1 sync error detected
Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit (R):
// 0 no transfer in progress or pending
// 1 transfer in progress or pending
Uint16 BURSTSTS:1; // 12 Burst Status Bit (R):
// 0 no burst in progress or pending
// 1 burst in progress or pending
Uint16 RUNSTS:1; // 13 Run Status Bit (R):
// 0 channel not running or halted
// 1 channel running
Uint16 OVRFLG:1; // 14 Overflow Flag Bit(R)
// 0 no overflow event
// 1 overflow event
Uint16 rsvd1:1; // 15 (R=0)
};
union CONTROL_REG {
Uint16 all;
struct CONTROL_BITS bit;
};
//
// DMACTRL register bit definitions
//
struct DMACTRL_BITS { // bits description
Uint16 HARDRESET:1; // 0 Hard Reset Bit (R=0/W=1)
Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit (R=0/W=1)
Uint16 rsvd1:14; // 15:2 (R=0:0)
};
union DMACTRL_REG {
Uint16 all;
struct DMACTRL_BITS bit;
};
//
// DEBUGCTRL register bit definitions
//
struct DEBUGCTRL_BITS { // bits description
Uint16 rsvd1:15; // 14:0 (R=0:0)
Uint16 FREE:1; // 15 Debug Mode Bit (R/W):
// 0 halt after current read-write operation
// 1 continue running
};
union DEBUGCTRL_REG {
Uint16 all;
struct DEBUGCTRL_BITS bit;
};
//
// PRIORITYCTRL1 register bit definitions
//
struct PRIORITYCTRL1_BITS { // bits description
Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit (R/W):
// 0 same priority as all other channels
// 1 highest priority channel
Uint16 rsvd1:15; // 15:1 (R=0:0)
};
union PRIORITYCTRL1_REG {
Uint16 all;
struct PRIORITYCTRL1_BITS bit;
};
//
// PRIORITYSTAT register bit definitions:
//
struct PRIORITYSTAT_BITS { // bits description
Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits (R):
// 0,0,0 no channel active
// 0,0,1 Ch1 channel active
// 0,1,0 Ch2 channel active
// 0,1,1 Ch3 channel active
// 1,0,0 Ch4 channel active
// 1,0,1 Ch5 channel active
// 1,1,0 Ch6 channel active
Uint16 rsvd1:1; // 3 (R=0)
Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits (R):
// 0,0,0 no channel active & interrupted by Ch1
// 0,0,1 cannot occur
// 0,1,0 Ch2 was active and interrupted by Ch1
// 0,1,1 Ch3 was active and interrupted by Ch1
// 1,0,0 Ch4 was active and interrupted by Ch1
// 1,0,1 Ch5 was active and interrupted by Ch1
// 1,1,0 Ch6 was active and interrupted by Ch1
Uint16 rsvd2:9; // 15:7 (R=0:0)
};
union PRIORITYSTAT_REG {
Uint16 all;
struct PRIORITYSTAT_BITS bit;
};
//
// Burst Size
//
struct BURST_SIZE_BITS { // bits description
Uint16 BURSTSIZE:5; // 4:0 Burst transfer size
Uint16 rsvd1:11; // 15:5 reserved
};
union BURST_SIZE_REG {
Uint16 all;
struct BURST_SIZE_BITS bit;
};
//
// Burst Count
//
struct BURST_COUNT_BITS { // bits description
Uint16 BURSTCOUNT:5; // 4:0 Burst transfer size
Uint16 rsvd1:11; // 15:5 reserved
};
union BURST_COUNT_REG {
Uint16 all;
struct BURST_COUNT_BITS bit;
};
//
// DMA Channel Registers:
//
struct CH_REGS {
union MODE_REG MODE; // Mode Register
union CONTROL_REG CONTROL; // Control Register
union BURST_SIZE_REG BURST_SIZE; // Burst Size Register
union BURST_COUNT_REG BURST_COUNT; // Burst Count Register
//
// Source Burst Step Register
//
int16 SRC_BURST_STEP;
//
// Destination Burst Step Register
//
int16 DST_BURST_STEP;
Uint16 TRANSFER_SIZE; // Transfer Size Register
Uint16 TRANSFER_COUNT; // Transfer Count Register
//
// Source Transfer Step Register
//
int16 SRC_TRANSFER_STEP;
//
// Destination Transfer Step Register
//
int16 DST_TRANSFER_STEP;
Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register
Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register
int16 SRC_WRAP_STEP; // Source Wrap Step Register
//
// Destination Wrap Size Register
//
Uint16 DST_WRAP_SIZE;
//
// Destination Wrap Count Register
//
Uint16 DST_WRAP_COUNT;
//
// Destination Wrap Step Register
//
int16 DST_WRAP_STEP;
//
// Source Begin Address Shadow Register
//
Uint32 SRC_BEG_ADDR_SHADOW;
//
// Source Address Shadow Register
//
Uint32 SRC_ADDR_SHADOW;
//
// Source Begin Address Active Register
//
Uint32 SRC_BEG_ADDR_ACTIVE;
//
// Source Address Active Register
//
Uint32 SRC_ADDR_ACTIVE;
//
// Destination Begin Address Shadow Register
//
Uint32 DST_BEG_ADDR_SHADOW;
//
// Destination Address Shadow Register
//
Uint32 DST_ADDR_SHADOW;
//
// Destination Begin Address Active Register
//
Uint32 DST_BEG_ADDR_ACTIVE;
//
// Destination Address Active Register
//
Uint32 DST_ADDR_ACTIVE;
};
//
// DMA Registers
//
struct DMA_REGS {
union DMACTRL_REG DMACTRL; // DMA Control Register
union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register
Uint16 rsvd0; // reserved
Uint16 rsvd1; //
union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register
Uint16 rsvd2; //
union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register
Uint16 rsvd3[25]; //
struct CH_REGS CH1; // DMA Channel 1 Registers
struct CH_REGS CH2; // DMA Channel 2 Registers
struct CH_REGS CH3; // DMA Channel 3 Registers
struct CH_REGS CH4; // DMA Channel 4 Registers
struct CH_REGS CH5; // DMA Channel 5 Registers
struct CH_REGS CH6; // DMA Channel 6 Registers
};
//
// External References & Function Declarations
//
extern volatile struct DMA_REGS DmaRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DMA_H definition
//
// End of file
//

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//###########################################################################
//
// FILE: DSP2833x_DefaultIsr.h
//
// TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_DEFAULT_ISR_H
#define DSP2833x_DEFAULT_ISR_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Default Interrupt Service Routine Declarations:
//
// The following function prototypes are for the
// default ISR routines used with the default PIE vector table.
// This default vector table is found in the DSP2833x_PieVect.h
// file.
//
//
// Non-Peripheral Interrupts
//
interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1
interrupt void INT14_ISR(void); // CPU-Timer2
interrupt void DATALOG_ISR(void); // Datalogging interrupt
interrupt void RTOSINT_ISR(void); // RTOS interrupt
interrupt void EMUINT_ISR(void); // Emulation interrupt
interrupt void NMI_ISR(void); // Non-maskable interrupt
interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP
interrupt void USER1_ISR(void); // User Defined trap 1
interrupt void USER2_ISR(void); // User Defined trap 2
interrupt void USER3_ISR(void); // User Defined trap 3
interrupt void USER4_ISR(void); // User Defined trap 4
interrupt void USER5_ISR(void); // User Defined trap 5
interrupt void USER6_ISR(void); // User Defined trap 6
interrupt void USER7_ISR(void); // User Defined trap 7
interrupt void USER8_ISR(void); // User Defined trap 8
interrupt void USER9_ISR(void); // User Defined trap 9
interrupt void USER10_ISR(void); // User Defined trap 10
interrupt void USER11_ISR(void); // User Defined trap 11
interrupt void USER12_ISR(void); // User Defined trap 12
//
// Group 1 PIE Interrupt Service Routines
//
interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR
interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR
interrupt void XINT1_ISR(void); // External interrupt 1
interrupt void XINT2_ISR(void); // External interrupt 2
interrupt void ADCINT_ISR(void); // ADC
interrupt void TINT0_ISR(void); // Timer 0
interrupt void WAKEINT_ISR(void); // WD
//
// Group 2 PIE Interrupt Service Routines
//
interrupt void EPWM1_TZINT_ISR(void); // EPWM-1
interrupt void EPWM2_TZINT_ISR(void); // EPWM-2
interrupt void EPWM3_TZINT_ISR(void); // EPWM-3
interrupt void EPWM4_TZINT_ISR(void); // EPWM-4
interrupt void EPWM5_TZINT_ISR(void); // EPWM-5
interrupt void EPWM6_TZINT_ISR(void); // EPWM-6
//
// Group 3 PIE Interrupt Service Routines
//
interrupt void EPWM1_INT_ISR(void); // EPWM-1
interrupt void EPWM2_INT_ISR(void); // EPWM-2
interrupt void EPWM3_INT_ISR(void); // EPWM-3
interrupt void EPWM4_INT_ISR(void); // EPWM-4
interrupt void EPWM5_INT_ISR(void); // EPWM-5
interrupt void EPWM6_INT_ISR(void); // EPWM-6
//
// Group 4 PIE Interrupt Service Routines
//
interrupt void ECAP1_INT_ISR(void); // ECAP-1
interrupt void ECAP2_INT_ISR(void); // ECAP-2
interrupt void ECAP3_INT_ISR(void); // ECAP-3
interrupt void ECAP4_INT_ISR(void); // ECAP-4
interrupt void ECAP5_INT_ISR(void); // ECAP-5
interrupt void ECAP6_INT_ISR(void); // ECAP-6
//
// Group 5 PIE Interrupt Service Routines
//
interrupt void EQEP1_INT_ISR(void); // EQEP-1
interrupt void EQEP2_INT_ISR(void); // EQEP-2
//
// Group 6 PIE Interrupt Service Routines
//
interrupt void SPIRXINTA_ISR(void); // SPI-A
interrupt void SPITXINTA_ISR(void); // SPI-A
interrupt void MRINTA_ISR(void); // McBSP-A
interrupt void MXINTA_ISR(void); // McBSP-A
interrupt void MRINTB_ISR(void); // McBSP-B
interrupt void MXINTB_ISR(void); // McBSP-B
//
// Group 7 PIE Interrupt Service Routines
//
interrupt void DINTCH1_ISR(void); // DMA-Channel 1
interrupt void DINTCH2_ISR(void); // DMA-Channel 2
interrupt void DINTCH3_ISR(void); // DMA-Channel 3
interrupt void DINTCH4_ISR(void); // DMA-Channel 4
interrupt void DINTCH5_ISR(void); // DMA-Channel 5
interrupt void DINTCH6_ISR(void); // DMA-Channel 6
//
// Group 8 PIE Interrupt Service Routines
//
interrupt void I2CINT1A_ISR(void); // I2C-A
interrupt void I2CINT2A_ISR(void); // I2C-A
interrupt void SCIRXINTC_ISR(void); // SCI-C
interrupt void SCITXINTC_ISR(void); // SCI-C
//
// Group 9 PIE Interrupt Service Routines
//
interrupt void SCIRXINTA_ISR(void); // SCI-A
interrupt void SCITXINTA_ISR(void); // SCI-A
interrupt void SCIRXINTB_ISR(void); // SCI-B
interrupt void SCITXINTB_ISR(void); // SCI-B
interrupt void ECAN0INTA_ISR(void); // eCAN-A
interrupt void ECAN1INTA_ISR(void); // eCAN-A
interrupt void ECAN0INTB_ISR(void); // eCAN-B
interrupt void ECAN1INTB_ISR(void); // eCAN-B
//
// Group 10 PIE Interrupt Service Routines
//
//
// Group 11 PIE Interrupt Service Routines
//
//
// Group 12 PIE Interrupt Service Routines
//
interrupt void XINT3_ISR(void); // External interrupt 3
interrupt void XINT4_ISR(void); // External interrupt 4
interrupt void XINT5_ISR(void); // External interrupt 5
interrupt void XINT6_ISR(void); // External interrupt 6
interrupt void XINT7_ISR(void); // External interrupt 7
interrupt void LVF_ISR(void); // Latched overflow flag
interrupt void LUF_ISR(void); // Latched underflow flag
//
// Catch-all for Reserved Locations For testing purposes
//
interrupt void PIE_RESERVED(void); // Reserved for test
interrupt void rsvd_ISR(void); // for test
interrupt void INT_NOTUSED_ISR(void); // for unused interrupts
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DEFAULT_ISR_H definition
//
// End of file
//

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F28335/DSP2833x_DevEmu.h
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//###########################################################################
//
// FILE: DSP2833x_DevEmu.h
//
// TITLE: DSP2833x Device Emulation Register Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_DEV_EMU_H
#define DSP2833x_DEV_EMU_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Device Emulation Register Bit Definitions:
//
//
// Device Configuration Register Bit Definitions
//
struct DEVICECNF_BITS { // bits description
Uint16 rsvd1:3; // 2:0 reserved
Uint16 VMAPS:1; // 3 VMAP Status
Uint16 rsvd2:1; // 4 reserved
Uint16 XRSn:1; // 5 XRSn Signal Status
Uint16 rsvd3:10; // 15:6
Uint16 rsvd4:3; // 18:16
Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection
Uint16 rsvd5:7; // 26:20 reserved
Uint16 TRSTN:1; // 27 Status of TRSTn signal
Uint16 rsvd6:4; // 31:28 reserved
};
union DEVICECNF_REG {
Uint32 all;
struct DEVICECNF_BITS bit;
};
//
// CLASSID
//
struct CLASSID_BITS { // bits description
Uint16 CLASSNO:8; // 7:0 Class Number
Uint16 PARTTYPE:8; // 15:8 Part Type
};
union CLASSID_REG {
Uint16 all;
struct CLASSID_BITS bit;
};
struct DEV_EMU_REGS {
union DEVICECNF_REG DEVICECNF; // device configuration
union CLASSID_REG CLASSID; // Class ID
Uint16 REVID; // Device ID
Uint16 PROTSTART; // Write-Read protection start
Uint16 PROTRANGE; // Write-Read protection range
Uint16 rsvd2[202];
};
//
// PARTID
//
struct PARTID_BITS { // bits description
Uint16 PARTNO:8; // 7:0 Part Number
Uint16 PARTTYPE:8; // 15:8 Part Type
};
union PARTID_REG {
Uint16 all;
struct PARTID_BITS bit;
};
struct PARTID_REGS {
union PARTID_REG PARTID; // Part ID
};
//
// Device Emulation Register References & Function Declarations
//
extern volatile struct DEV_EMU_REGS DevEmuRegs;
extern volatile struct PARTID_REGS PartIdRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DEV_EMU_H definition
//
// End of file
//

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F28335/DSP2833x_Device.h
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//###########################################################################
//
// FILE: DSP2833x_Device.h
//
// TITLE: DSP2833x Device Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_DEVICE_H
#define DSP2833x_DEVICE_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Defines
//
#define TARGET 1
//
// User To Select Target Device
//
#define DSP28_28335 TARGET // Selects '28335/'28235
#define DSP28_28334 0 // Selects '28334/'28234
#define DSP28_28333 0 // Selects '28333/'
#define DSP28_28332 0 // Selects '28332/'28232
//
// Common CPU Definitions
//
extern cregister volatile unsigned int IFR;
extern cregister volatile unsigned int IER;
#define EINT asm(" clrc INTM")
#define DINT asm(" setc INTM")
#define ERTM asm(" clrc DBGM")
#define DRTM asm(" setc DBGM")
#define EALLOW asm(" EALLOW")
#define EDIS asm(" EDIS")
#define ESTOP0 asm(" ESTOP0")
#define M_INT1 0x0001
#define M_INT2 0x0002
#define M_INT3 0x0004
#define M_INT4 0x0008
#define M_INT5 0x0010
#define M_INT6 0x0020
#define M_INT7 0x0040
#define M_INT8 0x0080
#define M_INT9 0x0100
#define M_INT10 0x0200
#define M_INT11 0x0400
#define M_INT12 0x0800
#define M_INT13 0x1000
#define M_INT14 0x2000
#define M_DLOG 0x4000
#define M_RTOS 0x8000
#define BIT0 0x0001
#define BIT1 0x0002
#define BIT2 0x0004
#define BIT3 0x0008
#define BIT4 0x0010
#define BIT5 0x0020
#define BIT6 0x0040
#define BIT7 0x0080
#define BIT8 0x0100
#define BIT9 0x0200
#define BIT10 0x0400
#define BIT11 0x0800
#define BIT12 0x1000
#define BIT13 0x2000
#define BIT14 0x4000
#define BIT15 0x8000
//
// For Portability, User Is Recommended To Use Following Data Type Size
// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
//
#ifndef DSP28_DATA_TYPES
#define DSP28_DATA_TYPES
typedef int int16;
typedef long int32;
typedef long long int64;
typedef unsigned int Uint16;
typedef unsigned long Uint32;
typedef unsigned long long Uint64;
typedef float float32;
typedef long double float64;
#endif
//
// Included Peripheral Header Files
//
#include "F28335/DSP2833x_Adc.h" // ADC Registers
#include "F28335/DSP2833x_DevEmu.h" // Device Emulation Registers
#include "F28335/DSP2833x_CpuTimers.h" // 32-bit CPU Timers
#include "F28335/DSP2833x_ECan.h" // Enhanced eCAN Registers
#include "F28335/DSP2833x_ECap.h" // Enhanced Capture
#include "F28335/DSP2833x_DMA.h" // DMA Registers
#include "F28335/DSP2833x_EPwm.h" // Enhanced PWM
#include "F28335/DSP2833x_EQep.h" // Enhanced QEP
#include "F28335/DSP2833x_Gpio.h" // General Purpose I/O Registers
#include "F28335/DSP2833x_I2c.h" // I2C Registers
#include "F28335/DSP2833x_Mcbsp.h" // McBSP
#include "F28335/DSP2833x_PieCtrl.h" // PIE Control Registers
#include "F28335/DSP2833x_PieVect.h" // PIE Vector Table
#include "F28335/DSP2833x_Spi.h" // SPI Registers
#include "F28335/DSP2833x_Sci.h" // SCI Registers
#include "F28335/DSP2833x_SysCtrl.h" // System Control/Power Modes
#include "F28335/DSP2833x_XIntrupt.h" // External Interrupts
#include "F28335/DSP2833x_Xintf.h" // XINTF External Interface
#if DSP28_28335 || DSP28_28333
#define DSP28_EPWM1 1
#define DSP28_EPWM2 1
#define DSP28_EPWM3 1
#define DSP28_EPWM4 1
#define DSP28_EPWM5 1
#define DSP28_EPWM6 1
#define DSP28_ECAP1 1
#define DSP28_ECAP2 1
#define DSP28_ECAP3 1
#define DSP28_ECAP4 1
#define DSP28_ECAP5 1
#define DSP28_ECAP6 1
#define DSP28_EQEP1 1
#define DSP28_EQEP2 1
#define DSP28_ECANA 1
#define DSP28_ECANB 1
#define DSP28_MCBSPA 1
#define DSP28_MCBSPB 1
#define DSP28_SPIA 1
#define DSP28_SCIA 1
#define DSP28_SCIB 1
#define DSP28_SCIC 1
#define DSP28_I2CA 1
#endif // end DSP28_28335 || DSP28_28333
#if DSP28_28334
#define DSP28_EPWM1 1
#define DSP28_EPWM2 1
#define DSP28_EPWM3 1
#define DSP28_EPWM4 1
#define DSP28_EPWM5 1
#define DSP28_EPWM6 1
#define DSP28_ECAP1 1
#define DSP28_ECAP2 1
#define DSP28_ECAP3 1
#define DSP28_ECAP4 1
#define DSP28_ECAP5 0
#define DSP28_ECAP6 0
#define DSP28_EQEP1 1
#define DSP28_EQEP2 1
#define DSP28_ECANA 1
#define DSP28_ECANB 1
#define DSP28_MCBSPA 1
#define DSP28_MCBSPB 1
#define DSP28_SPIA 1
#define DSP28_SCIA 1
#define DSP28_SCIB 1
#define DSP28_SCIC 1
#define DSP28_I2CA 1
#endif // end DSP28_28334
#if DSP28_28332
#define DSP28_EPWM1 1
#define DSP28_EPWM2 1
#define DSP28_EPWM3 1
#define DSP28_EPWM4 1
#define DSP28_EPWM5 1
#define DSP28_EPWM6 1
#define DSP28_ECAP1 1
#define DSP28_ECAP2 1
#define DSP28_ECAP3 1
#define DSP28_ECAP4 1
#define DSP28_ECAP5 0
#define DSP28_ECAP6 0
#define DSP28_EQEP1 1
#define DSP28_EQEP2 1
#define DSP28_ECANA 1
#define DSP28_ECANB 1
#define DSP28_MCBSPA 1
#define DSP28_MCBSPB 0
#define DSP28_SPIA 1
#define DSP28_SCIA 1
#define DSP28_SCIB 1
#define DSP28_SCIC 0
#define DSP28_I2CA 1
#endif // end DSP28_28332
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_DEVICE_H definition
//
// End of file
//

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F28335/DSP2833x_Dma_defines.h
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//###########################################################################
//
// FILE: DSP2833x_Dma_defines.h
//
// TITLE: #defines used in DMA examples
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_DMA_DEFINES_H
#define DSP2833x_DMA_DEFINES_H
#ifdef __cplusplus
extern "C" {
#endif
//
// MODE
//
// PERINTSEL bits
//
#define DMA_SEQ1INT 1
#define DMA_SEQ2INT 2
#define DMA_XINT1 3
#define DMA_XINT2 4
#define DMA_XINT3 5
#define DMA_XINT4 6
#define DMA_XINT5 7
#define DMA_XINT6 8
#define DMA_XINT7 9
#define DMA_XINT13 10
#define DMA_TINT0 11
#define DMA_TINT1 12
#define DMA_TINT2 13
#define DMA_MXEVTA 14
#define DMA_MREVTA 15
#define DMA_MXREVTB 16
#define DMA_MREVTB 17
//
// OVERINTE bit
//
#define OVRFLOW_DISABLE 0x0
#define OVEFLOW_ENABLE 0x1
//
// PERINTE bit
//
#define PERINT_DISABLE 0x0
#define PERINT_ENABLE 0x1
//
// CHINTMODE bits
//
#define CHINT_BEGIN 0x0
#define CHINT_END 0x1
//
// ONESHOT bits
//
#define ONESHOT_DISABLE 0x0
#define ONESHOT_ENABLE 0x1
//
// CONTINOUS bit
//
#define CONT_DISABLE 0x0
#define CONT_ENABLE 0x1
//
// SYNCE bit
//
#define SYNC_DISABLE 0x0
#define SYNC_ENABLE 0x1
//
// SYNCSEL bit
//
#define SYNC_SRC 0x0
#define SYNC_DST 0x1
//
// DATASIZE bit
//
#define SIXTEEN_BIT 0x0
#define THIRTYTWO_BIT 0x1
//
// CHINTE bit
//
#define CHINT_DISABLE 0x0
#define CHINT_ENABLE 0x1
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_EPWM_DEFINES_H
//
// End of file
//

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F28335/DSP2833x_ECan.h
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F28335/DSP2833x_ECap.h
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//###########################################################################
//
// FILE: DSP2833x_ECap.h
//
// TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_ECAP_H
#define DSP2833x_ECAP_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Capture control register 1 bit definitions
//
struct ECCTL1_BITS { // bits description
Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select
Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1
Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select
Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2
Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select
Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3
Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select
Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4
Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap
// Event
Uint16 PRESCALE:5; // 13:9 Event Filter prescale select
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union ECCTL1_REG {
Uint16 all;
struct ECCTL1_BITS bit;
};
//
// In V1.1 the STOPVALUE bit field was changed to
// STOP_WRAP. This correlated to a silicon change from
// F2833x Rev 0 to Rev A.
//
//
// Capture control register 2 bit definitions
//
struct ECCTL2_BITS { // bits description
Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot
Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous
Uint16 REARM:1; // 3 One-shot re-arm
Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop
Uint16 SYNCI_EN:1; // 5 Counter sync-in select
Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode
Uint16 SWSYNC:1; // 8 SW forced counter sync
Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select
Uint16 APWMPOL:1; // 10 APWM output polarity select
Uint16 rsvd1:5; // 15:11
};
union ECCTL2_REG {
Uint16 all;
struct ECCTL2_BITS bit;
};
//
// ECAP interrupt enable register bit definitions
//
struct ECEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable
Uint16 rsvd2:8; // 15:8 reserved
};
union ECEINT_REG {
Uint16 all;
struct ECEINT_BITS bit;
};
//
// ECAP interrupt flag register bit definitions
//
struct ECFLG_BITS { // bits description
Uint16 INT:1; // 0 Global Flag
Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag
Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag
Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag
Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag
Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag
Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag
Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag
Uint16 rsvd2:8; // 15:8 reserved
};
union ECFLG_REG {
Uint16 all;
struct ECFLG_BITS bit;
};
struct ECAP_REGS {
Uint32 TSCTR; // Time stamp counter
Uint32 CTRPHS; // Counter phase
Uint32 CAP1; // Capture 1
Uint32 CAP2; // Capture 2
Uint32 CAP3; // Capture 3
Uint32 CAP4; // Capture 4
Uint16 rsvd1[8]; // reserved
union ECCTL1_REG ECCTL1; // Capture Control Reg 1
union ECCTL2_REG ECCTL2; // Capture Control Reg 2
union ECEINT_REG ECEINT; // ECAP interrupt enable
union ECFLG_REG ECFLG; // ECAP interrupt flags
union ECFLG_REG ECCLR; // ECAP interrupt clear
union ECEINT_REG ECFRC; // ECAP interrupt force
Uint16 rsvd2[6]; // reserved
};
//
// GPI/O External References & Function Declarations
//
extern volatile struct ECAP_REGS ECap1Regs;
extern volatile struct ECAP_REGS ECap2Regs;
extern volatile struct ECAP_REGS ECap3Regs;
extern volatile struct ECAP_REGS ECap4Regs;
extern volatile struct ECAP_REGS ECap5Regs;
extern volatile struct ECAP_REGS ECap6Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_ECAP_H definition
//
// End of file
//

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//###########################################################################
//
// FILE: DSP2833x_EPwm.h
//
// TITLE: DSP2833x Enhanced PWM Module Register Bit Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_EPWM_H
#define DSP2833x_EPWM_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Time base control register bit definitions
//
struct TBCTL_BITS { // bits description
Uint16 CTRMODE:2; // 1:0 Counter Mode
Uint16 PHSEN:1; // 2 Phase load enable
Uint16 PRDLD:1; // 3 Active period load
Uint16 SYNCOSEL:2; // 5:4 Sync output select
Uint16 SWFSYNC:1; // 6 Software force sync pulse
Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale
Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale
Uint16 PHSDIR:1; // 13 Phase Direction
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union TBCTL_REG {
Uint16 all;
struct TBCTL_BITS bit;
};
//
// Time base status register bit definitions
//
struct TBSTS_BITS { // bits description
Uint16 CTRDIR:1; // 0 Counter direction status
Uint16 SYNCI:1; // 1 External input sync status
Uint16 CTRMAX:1; // 2 Counter max latched status
Uint16 rsvd1:13; // 15:3 reserved
};
union TBSTS_REG {
Uint16 all;
struct TBSTS_BITS bit;
};
//
// Compare control register bit definitions
//
struct CMPCTL_BITS { // bits description
Uint16 LOADAMODE:2; // 0:1 Active compare A
Uint16 LOADBMODE:2; // 3:2 Active compare B
Uint16 SHDWAMODE:1; // 4 Compare A block operating mode
Uint16 rsvd1:1; // 5 reserved
Uint16 SHDWBMODE:1; // 6 Compare B block operating mode
Uint16 rsvd2:1; // 7 reserved
Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status
Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status
Uint16 rsvd3:6; // 15:10 reserved
};
union CMPCTL_REG {
Uint16 all;
struct CMPCTL_BITS bit;
};
//
// Action qualifier register bit definitions
//
struct AQCTL_BITS { // bits description
Uint16 ZRO:2; // 1:0 Action Counter = Zero
Uint16 PRD:2; // 3:2 Action Counter = Period
Uint16 CAU:2; // 5:4 Action Counter = Compare A up
Uint16 CAD:2; // 7:6 Action Counter = Compare A down
Uint16 CBU:2; // 9:8 Action Counter = Compare B up
Uint16 CBD:2; // 11:10 Action Counter = Compare B down
Uint16 rsvd:4; // 15:12 reserved
};
union AQCTL_REG {
Uint16 all;
struct AQCTL_BITS bit;
};
//
// Action qualifier SW force register bit definitions
//
struct AQSFRC_BITS { // bits description
Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked
Uint16 OTSFA:1; // 2 One-time SW Force A output
Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked
Uint16 OTSFB:1; // 5 One-time SW Force A output
Uint16 RLDCSF:2; // 7:6 Reload from Shadow options
Uint16 rsvd1:8; // 15:8 reserved
};
union AQSFRC_REG {
Uint16 all;
struct AQSFRC_BITS bit;
};
//
// Action qualifier continuous SW force register bit definitions
//
struct AQCSFRC_BITS { // bits description
Uint16 CSFA:2; // 1:0 Continuous Software Force on output A
Uint16 CSFB:2; // 3:2 Continuous Software Force on output B
Uint16 rsvd1:12; // 15:4 reserved
};
union AQCSFRC_REG {
Uint16 all;
struct AQCSFRC_BITS bit;
};
//
// As of version 1.1
// Changed the MODE bit-field to OUT_MODE
// Added the bit-field IN_MODE
// This corresponds to changes in silicon as of F2833x devices
// Rev A silicon.
//
//
// Dead-band generator control register bit definitions
//
struct DBCTL_BITS { // bits description
Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control
Uint16 POLSEL:2; // 3:2 Polarity Select Control
Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control
Uint16 rsvd1:10; // 15:4 reserved
};
union DBCTL_REG {
Uint16 all;
struct DBCTL_BITS bit;
};
//
// Trip zone select register bit definitions
//
struct TZSEL_BITS { // bits description
Uint16 CBC1:1; // 0 TZ1 CBC select
Uint16 CBC2:1; // 1 TZ2 CBC select
Uint16 CBC3:1; // 2 TZ3 CBC select
Uint16 CBC4:1; // 3 TZ4 CBC select
Uint16 CBC5:1; // 4 TZ5 CBC select
Uint16 CBC6:1; // 5 TZ6 CBC select
Uint16 rsvd1:2; // 7:6 reserved
Uint16 OSHT1:1; // 8 One-shot TZ1 select
Uint16 OSHT2:1; // 9 One-shot TZ2 select
Uint16 OSHT3:1; // 10 One-shot TZ3 select
Uint16 OSHT4:1; // 11 One-shot TZ4 select
Uint16 OSHT5:1; // 12 One-shot TZ5 select
Uint16 OSHT6:1; // 13 One-shot TZ6 select
Uint16 rsvd2:2; // 15:14 reserved
};
union TZSEL_REG {
Uint16 all;
struct TZSEL_BITS bit;
};
//
// Trip zone control register bit definitions
//
struct TZCTL_BITS { // bits description
Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA
Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB
Uint16 rsvd:12; // 15:4 reserved
};
union TZCTL_REG {
Uint16 all;
struct TZCTL_BITS bit;
};
//
// Trip zone control register bit definitions
//
struct TZEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable
Uint16 OST:1; // 2 Trip Zones One Shot Int Enable
Uint16 rsvd2:13; // 15:3 reserved
};
union TZEINT_REG {
Uint16 all;
struct TZEINT_BITS bit;
};
//
// Trip zone flag register bit definitions
//
struct TZFLG_BITS { // bits description
Uint16 INT:1; // 0 Global status
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 rsvd2:13; // 15:3 reserved
};
union TZFLG_REG {
Uint16 all;
struct TZFLG_BITS bit;
};
//
// Trip zone flag clear register bit definitions
//
struct TZCLR_BITS { // bits description
Uint16 INT:1; // 0 Global status
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 rsvd2:13; // 15:3 reserved
};
union TZCLR_REG {
Uint16 all;
struct TZCLR_BITS bit;
};
//
// Trip zone flag force register bit definitions
//
struct TZFRC_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int
Uint16 OST:1; // 2 Trip Zones One Shot Int
Uint16 rsvd2:13; // 15:3 reserved
};
union TZFRC_REG {
Uint16 all;
struct TZFRC_BITS bit;
};
//
// Event trigger select register bit definitions
//
struct ETSEL_BITS { // bits description
Uint16 INTSEL:3; // 2:0 EPWMxINTn Select
Uint16 INTEN:1; // 3 EPWMxINTn Enable
Uint16 rsvd1:4; // 7:4 reserved
Uint16 SOCASEL:3; // 10:8 Start of conversion A Select
Uint16 SOCAEN:1; // 11 Start of conversion A Enable
Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select
Uint16 SOCBEN:1; // 15 Start of conversion B Enable
};
union ETSEL_REG {
Uint16 all;
struct ETSEL_BITS bit;
};
//
// Event trigger pre-scale register bit definitions
//
struct ETPS_BITS { // bits description
Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select
Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register
Uint16 rsvd1:4; // 7:4 reserved
Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select
Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register
Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select
Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register
};
union ETPS_REG {
Uint16 all;
struct ETPS_BITS bit;
};
//
// Event trigger Flag register bit definitions
//
struct ETFLG_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Flag
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Flag
Uint16 SOCB:1; // 3 EPWMxSOCB Flag
Uint16 rsvd2:12; // 15:4 reserved
};
union ETFLG_REG {
Uint16 all;
struct ETFLG_BITS bit;
};
//
// Event trigger Clear register bit definitions
//
struct ETCLR_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Clear
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Clear
Uint16 SOCB:1; // 3 EPWMxSOCB Clear
Uint16 rsvd2:12; // 15:4 reserved
};
union ETCLR_REG {
Uint16 all;
struct ETCLR_BITS bit;
};
//
// Event trigger Force register bit definitions
//
struct ETFRC_BITS { // bits description
Uint16 INT:1; // 0 EPWMxINTn Force
Uint16 rsvd1:1; // 1 reserved
Uint16 SOCA:1; // 2 EPWMxSOCA Force
Uint16 SOCB:1; // 3 EPWMxSOCB Force
Uint16 rsvd2:12; // 15:4 reserved
};
union ETFRC_REG {
Uint16 all;
struct ETFRC_BITS bit;
};
//
// PWM chopper control register bit definitions
//
struct PCCTL_BITS { // bits description
Uint16 CHPEN:1; // 0 PWM chopping enable
Uint16 OSHTWTH:4; // 4:1 One-shot pulse width
Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency
Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle
Uint16 rsvd1:5; // 15:11 reserved
};
union PCCTL_REG {
Uint16 all;
struct PCCTL_BITS bit;
};
struct HRCNFG_BITS { // bits description
Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits
Uint16 CTLMODE:1; // 2 Control mode Select Bit
Uint16 HRLOAD:1; // 3 Shadow mode Select Bit
Uint16 rsvd1:12; // 15:4 reserved
};
union HRCNFG_REG {
Uint16 all;
struct HRCNFG_BITS bit;
};
struct TBPHS_HRPWM_REG { //bits description
Uint16 TBPHSHR; //15:0 Extension register for HRPWM Phase(8 bits)
Uint16 TBPHS; //31:16 Phase offset register
};
union TBPHS_HRPWM_GROUP {
Uint32 all;
struct TBPHS_HRPWM_REG half;
};
struct CMPA_HRPWM_REG { // bits description
Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits)
Uint16 CMPA; // 31:16 Compare A reg
};
union CMPA_HRPWM_GROUP {
Uint32 all;
struct CMPA_HRPWM_REG half;
};
struct EPWM_REGS {
union TBCTL_REG TBCTL; //
union TBSTS_REG TBSTS; //
union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR
Uint16 TBCTR; // Counter
Uint16 TBPRD; // Period register set
Uint16 rsvd1; //
union CMPCTL_REG CMPCTL; // Compare control
union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR
Uint16 CMPB; // Compare B reg
union AQCTL_REG AQCTLA; // Action qual output A
union AQCTL_REG AQCTLB; // Action qual output B
union AQSFRC_REG AQSFRC; // Action qual SW force
union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force
union DBCTL_REG DBCTL; // Dead-band control
Uint16 DBRED; // Dead-band rising edge delay
Uint16 DBFED; // Dead-band falling edge delay
union TZSEL_REG TZSEL; // Trip zone select
Uint16 rsvd2;
union TZCTL_REG TZCTL; // Trip zone control
union TZEINT_REG TZEINT; // Trip zone interrupt enable
union TZFLG_REG TZFLG; // Trip zone interrupt flags
union TZCLR_REG TZCLR; // Trip zone clear
union TZFRC_REG TZFRC; // Trip zone force interrupt
union ETSEL_REG ETSEL; // Event trigger selection
union ETPS_REG ETPS; // Event trigger pre-scaler
union ETFLG_REG ETFLG; // Event trigger flags
union ETCLR_REG ETCLR; // Event trigger clear
union ETFRC_REG ETFRC; // Event trigger force
union PCCTL_REG PCCTL; // PWM chopper control
Uint16 rsvd3; //
union HRCNFG_REG HRCNFG; // HRPWM Config Reg
};
//
// External References & Function Declarations
//
extern volatile struct EPWM_REGS EPwm1Regs;
extern volatile struct EPWM_REGS EPwm2Regs;
extern volatile struct EPWM_REGS EPwm3Regs;
extern volatile struct EPWM_REGS EPwm4Regs;
extern volatile struct EPWM_REGS EPwm5Regs;
extern volatile struct EPWM_REGS EPwm6Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EPWM_H definition
//
// End of file
//

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F28335/DSP2833x_EPwm_defines.h
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//###########################################################################
//
// FILE: DSP2833x_EPwm_defines.h
//
// TITLE: #defines used in ePWM examples examples
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_EPWM_DEFINES_H
#define DSP2833x_EPWM_DEFINES_H
#ifdef __cplusplus
extern "C" {
#endif
//
// TBCTL (Time-Base Control)
//
// CTRMODE bits
//
#define TB_COUNT_UP 0x0
#define TB_COUNT_DOWN 0x1
#define TB_COUNT_UPDOWN 0x2
#define TB_FREEZE 0x3
//
// PHSEN bit
//
#define TB_DISABLE 0x0
#define TB_ENABLE 0x1
//
// PRDLD bit
//
#define TB_SHADOW 0x0
#define TB_IMMEDIATE 0x1
//
// SYNCOSEL bits
//
#define TB_SYNC_IN 0x0
#define TB_CTR_ZERO 0x1
#define TB_CTR_CMPB 0x2
#define TB_SYNC_DISABLE 0x3
//
// HSPCLKDIV and CLKDIV bits
//
#define TB_DIV1 0x0
#define TB_DIV2 0x1
#define TB_DIV4 0x2
//
// PHSDIR bit
//
#define TB_DOWN 0x0
#define TB_UP 0x1
//
// CMPCTL (Compare Control)
//
// LOADAMODE and LOADBMODE bits
//
#define CC_CTR_ZERO 0x0
#define CC_CTR_PRD 0x1
#define CC_CTR_ZERO_PRD 0x2
#define CC_LD_DISABLE 0x3
//
// SHDWAMODE and SHDWBMODE bits
//
#define CC_SHADOW 0x0
#define CC_IMMEDIATE 0x1
//
// AQCTLA and AQCTLB (Action Qualifier Control)
//
// ZRO, PRD, CAU, CAD, CBU, CBD bits
//
#define AQ_NO_ACTION 0x0
#define AQ_CLEAR 0x1
#define AQ_SET 0x2
#define AQ_TOGGLE 0x3
//
// DBCTL (Dead-Band Control)
//
// OUT MODE bits
//
#define DB_DISABLE 0x0
#define DBB_ENABLE 0x1
#define DBA_ENABLE 0x2
#define DB_FULL_ENABLE 0x3
//
// POLSEL bits
//
#define DB_ACTV_HI 0x0
#define DB_ACTV_LOC 0x1
#define DB_ACTV_HIC 0x2
#define DB_ACTV_LO 0x3
//
// IN MODE
//
#define DBA_ALL 0x0
#define DBB_RED_DBA_FED 0x1
#define DBA_RED_DBB_FED 0x2
#define DBB_ALL 0x3
//
// CHPCTL (chopper control)
//
// CHPEN bit
//
#define CHP_DISABLE 0x0
#define CHP_ENABLE 0x1
//
// CHPFREQ bits
//
#define CHP_DIV1 0x0
#define CHP_DIV2 0x1
#define CHP_DIV3 0x2
#define CHP_DIV4 0x3
#define CHP_DIV5 0x4
#define CHP_DIV6 0x5
#define CHP_DIV7 0x6
#define CHP_DIV8 0x7
//
// CHPDUTY bits
//
#define CHP1_8TH 0x0
#define CHP2_8TH 0x1
#define CHP3_8TH 0x2
#define CHP4_8TH 0x3
#define CHP5_8TH 0x4
#define CHP6_8TH 0x5
#define CHP7_8TH 0x6
//
// TZSEL (Trip Zone Select)
//
// CBCn and OSHTn bits
//
#define TZ_DISABLE 0x0
#define TZ_ENABLE 0x1
//
// TZCTL (Trip Zone Control)
//
// TZA and TZB bits
//
#define TZ_HIZ 0x0
#define TZ_FORCE_HI 0x1
#define TZ_FORCE_LO 0x2
#define TZ_NO_CHANGE 0x3
//
// ETSEL (Event Trigger Select)
//
#define ET_CTR_ZERO 0x1
#define ET_CTR_PRD 0x2
#define ET_CTRU_CMPA 0x4
#define ET_CTRD_CMPA 0x5
#define ET_CTRU_CMPB 0x6
#define ET_CTRD_CMPB 0x7
//
// ETPS (Event Trigger Pre-scale)
//
// INTPRD, SOCAPRD, SOCBPRD bits
//
#define ET_DISABLE 0x0
#define ET_1ST 0x1
#define ET_2ND 0x2
#define ET_3RD 0x3
//
// HRPWM (High Resolution PWM)
//
// HRCNFG
//
#define HR_Disable 0x0
#define HR_REP 0x1
#define HR_FEP 0x2
#define HR_BEP 0x3
#define HR_CMP 0x0
#define HR_PHS 0x1
#define HR_CTR_ZERO 0x0
#define HR_CTR_PRD 0x1
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_EPWM_DEFINES_H
//
// End of file
//

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F28335/DSP2833x_EQep.h
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//###########################################################################
//
// FILE: DSP2833x_EQep.h
//
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
// Register Bit Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_EQEP_H
#define DSP2833x_EQEP_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Capture decoder control register bit definitions
//
struct QDECCTL_BITS { // bits description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 QSP:1; // 5 QEPS input polarity
Uint16 QIP:1; // 6 QEPI input polarity
Uint16 QBP:1; // 7 QEPB input polarity
Uint16 QAP:1; // 8 QEPA input polarity
Uint16 IGATE:1; // 9 Index pulse gating option
Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter
Uint16 XCR:1; // 11 External clock rate
Uint16 SPSEL:1; // 12 Sync output pin select
Uint16 SOEN:1; // 13 Enable position compare sync
Uint16 QSRC:2; // 15:14 Position counter source
};
union QDECCTL_REG {
Uint16 all;
struct QDECCTL_BITS bit;
};
//
// QEP control register bit definitions
//
struct QEPCTL_BITS { // bits description
Uint16 WDE:1; // 0 QEP watchdog enable
Uint16 UTE:1; // 1 QEP unit timer enable
Uint16 QCLM:1; // 2 QEP capture latch mode
Uint16 QPEN:1; // 3 Quadrature position counter enable
Uint16 IEL:2; // 5:4 Index event latch
Uint16 SEL:1; // 6 Strobe event latch
Uint16 SWI:1; // 7 Software init position counter
Uint16 IEI:2; // 9:8 Index event init of position count
Uint16 SEI:2; // 11:10 Strobe event init
Uint16 PCRM:2; // 13:12 Position counter reset
Uint16 FREE_SOFT:2; // 15:14 Emulation mode
};
union QEPCTL_REG {
Uint16 all;
struct QEPCTL_BITS bit;
};
//
// Quadrature capture control register bit definitions
//
struct QCAPCTL_BITS { // bits description
Uint16 UPPS:4; // 3:0 Unit position pre-scale
Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale
Uint16 rsvd1:8; // 14:7 reserved
Uint16 CEN:1; // 15 Enable QEP capture
};
union QCAPCTL_REG {
Uint16 all;
struct QCAPCTL_BITS bit;
};
//
// Position compare control register bit definitions
//
struct QPOSCTL_BITS { // bits description
Uint16 PCSPW:12; // 11:0 Position compare sync pulse width
Uint16 PCE:1; // 12 Position compare enable/disable
Uint16 PCPOL:1; // 13 Polarity of sync output
Uint16 PCLOAD:1; // 14 Position compare of shadow load
Uint16 PCSHDW:1; // 15 Position compare shadow enable
};
union QPOSCTL_REG {
Uint16 all;
struct QPOSCTL_BITS bit;
};
//
// QEP interrupt control register bit definitions
//
struct QEINT_BITS { // bits description
Uint16 rsvd1:1; // 0 reserved
Uint16 PCE:1; // 1 Position counter error
Uint16 QPE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QEINT_REG {
Uint16 all;
struct QEINT_BITS bit;
};
//
// QEP interrupt status register bit definitions
//
struct QFLG_BITS { // bits description
Uint16 INT:1; // 0 Global interrupt
Uint16 PCE:1; // 1 Position counter error
Uint16 PHE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QFLG_REG {
Uint16 all;
struct QFLG_BITS bit;
};
//
// QEP interrupt force register bit definitions
//
struct QFRC_BITS { // bits description
Uint16 reserved:1; // 0 Reserved
Uint16 PCE:1; // 1 Position counter error
Uint16 PHE:1; // 2 Quadrature phase error
Uint16 QDC:1; // 3 Quadrature dir change
Uint16 WTO:1; // 4 Watchdog timeout
Uint16 PCU:1; // 5 Position counter underflow
Uint16 PCO:1; // 6 Position counter overflow
Uint16 PCR:1; // 7 Position compare ready
Uint16 PCM:1; // 8 Position compare match
Uint16 SEL:1; // 9 Strobe event latch
Uint16 IEL:1; // 10 Event latch
Uint16 UTO:1; // 11 Unit timeout
Uint16 rsvd2:4; // 15:12 reserved
};
union QFRC_REG {
Uint16 all;
struct QFRC_BITS bit;
};
//
// V1.1 Added UPEVNT (bit 7) This reflects changes
// made as of F2833x Rev A devices
//
//
// QEP status register bit definitions
//
struct QEPSTS_BITS { // bits description
Uint16 PCEF:1; // 0 Position counter error
Uint16 FIMF:1; // 1 First index marker
Uint16 CDEF:1; // 2 Capture direction error
Uint16 COEF:1; // 3 Capture overflow error
Uint16 QDLF:1; // 4 QEP direction latch
Uint16 QDF:1; // 5 Quadrature direction
Uint16 FIDF:1; // 6 Direction on first index marker
Uint16 UPEVNT:1; // 7 Unit position event flag
Uint16 rsvd1:8; // 15:8 reserved
};
union QEPSTS_REG {
Uint16 all;
struct QEPSTS_BITS bit;
};
struct EQEP_REGS {
Uint32 QPOSCNT; // Position counter
Uint32 QPOSINIT; // Position counter init
Uint32 QPOSMAX; // Maximum position count
Uint32 QPOSCMP; // Position compare
Uint32 QPOSILAT; // Index position latch
Uint32 QPOSSLAT; // Strobe position latch
Uint32 QPOSLAT; // Position latch
Uint32 QUTMR; // Unit timer
Uint32 QUPRD; // Unit period
Uint16 QWDTMR; // QEP watchdog timer
Uint16 QWDPRD; // QEP watchdog period
union QDECCTL_REG QDECCTL; // Quadrature decoder control
union QEPCTL_REG QEPCTL; // QEP control
union QCAPCTL_REG QCAPCTL; // Quadrature capture control
union QPOSCTL_REG QPOSCTL; // Position compare control
union QEINT_REG QEINT; // QEP interrupt control
union QFLG_REG QFLG; // QEP interrupt flag
union QFLG_REG QCLR; // QEP interrupt clear
union QFRC_REG QFRC; // QEP interrupt force
union QEPSTS_REG QEPSTS; // QEP status
Uint16 QCTMR; // QEP capture timer
Uint16 QCPRD; // QEP capture period
Uint16 QCTMRLAT; // QEP capture latch
Uint16 QCPRDLAT; // QEP capture period latch
Uint16 rsvd1[30]; // reserved
};
//
// GPI/O External References & Function Declarations
//
extern volatile struct EQEP_REGS EQep1Regs;
extern volatile struct EQEP_REGS EQep2Regs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EQEP_H definition
//
// End of file
//

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//###########################################################################
//
// FILE: DSP2833x_Examples.h
//
// TITLE: DSP2833x Device Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_EXAMPLES_H
#define DSP2833x_EXAMPLES_H
#ifdef __cplusplus
extern "C" {
#endif
//
// Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
//
//#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT
//#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT
#define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT
//#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT
#define DSP28_PLLCR 10
//#define DSP28_PLLCR 9
//#define DSP28_PLLCR 8
//#define DSP28_PLLCR 7
//#define DSP28_PLLCR 6
//#define DSP28_PLLCR 5
//#define DSP28_PLLCR 4
//#define DSP28_PLLCR 3
//#define DSP28_PLLCR 2
//#define DSP28_PLLCR 1
//#define DSP28_PLLCR 0 // PLL is bypassed in this mode
//
// Specify the clock rate of the CPU (SYSCLKOUT) in nS.
//
// Take into account the input clock frequency and the PLL multiplier
// selected in step 1.
//
// Use one of the values provided, or define your own.
// The trailing L is required tells the compiler to treat
// the number as a 64-bit value.
//
// Only one statement should be uncommented.
//
// Example 1:150 MHz devices:
// CLKIN is a 30MHz crystal.
//
// In step 1 the user specified PLLCR = 0xA for a
// 150Mhz CPU clock (SYSCLKOUT = 150MHz).
//
// In this case, the CPU_RATE will be 6.667L
// Uncomment the line: #define CPU_RATE 6.667L
//
// Example 2: 100 MHz devices:
// CLKIN is a 20MHz crystal.
//
// In step 1 the user specified PLLCR = 0xA for a
// 100Mhz CPU clock (SYSCLKOUT = 100MHz).
//
// In this case, the CPU_RATE will be 10.000L
// Uncomment the line: #define CPU_RATE 10.000L
//
#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
//
// Target device (in DSP2833x_Device.h) determines CPU frequency
// (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz
// (for 28332 and 28333). User does not have to change anything here.
//
#if DSP28_28332 || DSP28_28333 // 28332 and 28333 devices only
#define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq)
#define CPU_FRQ_150MHZ 0
#else
#define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334
#define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT
#endif
//
// Include Example Header Files
//
//
// Prototypes for global functions within the .c files.
//
#include "F28335/DSP2833x_GlobalPrototypes.h"
#include "F28335/DSP2833x_EPwm_defines.h" // Macros used for PWM examples.
#include "F28335/DSP2833x_Dma_defines.h" // Macros used for DMA examples.
#include "F28335/DSP2833x_I2c_defines.h" // Macros used for I2C examples.
#define PARTNO_28335 0xEF
#define PARTNO_28334 0xEE
#define PARTNO_28333 0xEA
#define PARTNO_28332 0xED
#define PARTNO_28235 0xE8
#define PARTNO_28234 0xE7
#define PARTNO_28232 0xE6
//
// Include files not used with DSP/BIOS
//
#ifndef DSP28_BIOS
#include "F28335/DSP2833x_DefaultIsr.h"
#endif
//
// DO NOT MODIFY THIS LINE.
//
#define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / \
(long double)CPU_RATE) - 9.0L) / 5.0L)
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_EXAMPLES_H definition
//
// End of file
//

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//###########################################################################
//
// FILE: DSP2833x_GlobalPrototypes.h
//
// TITLE: Global prototypes for DSP2833x Examples
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_GLOBALPROTOTYPES_H
#define DSP2833x_GLOBALPROTOTYPES_H
#ifdef __cplusplus
extern "C" {
#endif
//
// shared global function prototypes
//
extern void InitAdc(void);
extern void DMAInitialize(void);
//
// DMA Channel 1
//
extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH1(void);
//
// DMA Channel 2
//
extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH2(void);
//
// DMA Channel 3
//
extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH3(void);
//
// DMA Channel 4
//
extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH4(void);
//
// DMA Channel 5
//
extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH5(void);
//
// DMA Channel 6
//
extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,
volatile Uint16 *DMA_Source);
extern void DMACH6BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep);
extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep);
extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize,
int16 deswstep);
extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot,
Uint16 cont, Uint16 synce, Uint16 syncsel,
Uint16 ovrinte, Uint16 datasize, Uint16 chintmode,
Uint16 chinte);
extern void StartDMACH6(void);
extern void InitPeripherals(void);
#if DSP28_ECANA
extern void InitECan(void);
extern void InitECana(void);
extern void InitECanGpio(void);
extern void InitECanaGpio(void);
#endif // endif DSP28_ECANA
#if DSP28_ECANB
extern void InitECanb(void);
extern void InitECanbGpio(void);
#endif // endif DSP28_ECANB
extern void InitECap(void);
extern void InitECapGpio(void);
extern void InitECap1Gpio(void);
extern void InitECap2Gpio(void);
#if DSP28_ECAP3
extern void InitECap3Gpio(void);
#endif // endif DSP28_ECAP3
#if DSP28_ECAP4
extern void InitECap4Gpio(void);
#endif // endif DSP28_ECAP4
#if DSP28_ECAP5
extern void InitECap5Gpio(void);
#endif // endif DSP28_ECAP5
#if DSP28_ECAP6
extern void InitECap6Gpio(void);
#endif // endif DSP28_ECAP6
extern void InitEPwm(void);
extern void InitEPwmGpio(void);
extern void InitEPwm1Gpio(void);
extern void InitEPwm2Gpio(void);
extern void InitEPwm3Gpio(void);
#if DSP28_EPWM4
extern void InitEPwm4Gpio(void);
#endif // endif DSP28_EPWM4
#if DSP28_EPWM5
extern void InitEPwm5Gpio(void);
#endif // endif DSP28_EPWM5
#if DSP28_EPWM6
extern void InitEPwm6Gpio(void);
#endif // endif DSP28_EPWM6
#if DSP28_EQEP1
extern void InitEQep(void);
extern void InitEQepGpio(void);
extern void InitEQep1Gpio(void);
#endif // if DSP28_EQEP1
#if DSP28_EQEP2
extern void InitEQep2Gpio(void);
#endif // endif DSP28_EQEP2
extern void InitGpio(void);
extern void InitI2CGpio(void);
extern void InitMcbsp(void);
extern void InitMcbspa(void);
extern void delay_loop(void);
extern void InitMcbspaGpio(void);
extern void InitMcbspa8bit(void);
extern void InitMcbspa12bit(void);
extern void InitMcbspa16bit(void);
extern void InitMcbspa20bit(void);
extern void InitMcbspa24bit(void);
extern void InitMcbspa32bit(void);
#if DSP28_MCBSPB
extern void InitMcbspb(void);
extern void InitMcbspbGpio(void);
extern void InitMcbspb8bit(void);
extern void InitMcbspb12bit(void);
extern void InitMcbspb16bit(void);
extern void InitMcbspb20bit(void);
extern void InitMcbspb24bit(void);
extern void InitMcbspb32bit(void);
#endif // endif DSP28_MCBSPB
extern void InitPieCtrl(void);
extern void InitPieVectTable(void);
extern void InitSci(void);
extern void InitSciGpio(void);
extern void InitSciaGpio(void);
#if DSP28_SCIB
extern void InitScibGpio(void);
#endif // endif DSP28_SCIB
#if DSP28_SCIC
extern void InitScicGpio(void);
#endif
extern void InitSpi(void);
extern void InitSpiGpio(void);
extern void InitSpiaGpio(void);
extern void InitSysCtrl(void);
extern void InitTzGpio(void);
extern void InitXIntrupt(void);
extern void XintfInit(void);
extern void InitXintf16Gpio();
extern void InitXintf32Gpio();
extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
extern void InitPeripheralClocks(void);
extern void EnableInterrupts(void);
extern void DSP28x_usDelay(Uint32 Count);
extern void ADC_cal (void);
#define KickDog ServiceDog // For compatiblity with previous versions
extern void ServiceDog(void);
extern void DisableDog(void);
extern Uint16 CsmUnlock(void);
//
// DSP28_DBGIER.asm
//
extern void SetDBGIER(Uint16 dbgier);
//
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
//
extern void InitFlash(void);
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
//
// External symbols created by the linker cmd file
// DSP28 examples will use these to relocate code from one LOAD location
// in either Flash or XINTF to a different RUN location in internal
// RAM
//
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;
extern Uint16 RamfuncsLoadSize;
extern Uint16 XintffuncsLoadStart;
extern Uint16 XintffuncsLoadEnd;
extern Uint16 XintffuncsRunStart;
extern Uint16 XintffuncsLoadSize;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // - end of DSP2833x_GLOBALPROTOTYPES_H
//
// End of file
//

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//###########################################################################
//
// FILE: DSP2833x_Gpio.h
//
// TITLE: DSP2833x General Purpose I/O Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_GPIO_H
#define DSP2833x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
//
// GPIO A control register bit definitions
//
struct GPACTRL_BITS { // bits description
Uint16 QUALPRD0:8; // 7:0 Qual period
Uint16 QUALPRD1:8; // 15:8 Qual period
Uint16 QUALPRD2:8; // 23:16 Qual period
Uint16 QUALPRD3:8; // 31:24 Qual period
};
union GPACTRL_REG {
Uint32 all;
struct GPACTRL_BITS bit;
};
//
// GPIO B control register bit definitions
//
struct GPBCTRL_BITS { // bits description
Uint16 QUALPRD0:8; // 7:0 Qual period
Uint16 QUALPRD1:8; // 15:8 Qual period
Uint16 QUALPRD2:8; // 23:16 Qual period
Uint16 QUALPRD3:8; // 31:24
};
union GPBCTRL_REG {
Uint32 all;
struct GPBCTRL_BITS bit;
};
//
// GPIO A Qual/MUX select register bit definitions
//
struct GPA1_BITS { // bits description
Uint16 GPIO0:2; // 1:0 GPIO0
Uint16 GPIO1:2; // 3:2 GPIO1
Uint16 GPIO2:2; // 5:4 GPIO2
Uint16 GPIO3:2; // 7:6 GPIO3
Uint16 GPIO4:2; // 9:8 GPIO4
Uint16 GPIO5:2; // 11:10 GPIO5
Uint16 GPIO6:2; // 13:12 GPIO6
Uint16 GPIO7:2; // 15:14 GPIO7
Uint16 GPIO8:2; // 17:16 GPIO8
Uint16 GPIO9:2; // 19:18 GPIO9
Uint16 GPIO10:2; // 21:20 GPIO10
Uint16 GPIO11:2; // 23:22 GPIO11
Uint16 GPIO12:2; // 25:24 GPIO12
Uint16 GPIO13:2; // 27:26 GPIO13
Uint16 GPIO14:2; // 29:28 GPIO14
Uint16 GPIO15:2; // 31:30 GPIO15
};
struct GPA2_BITS { // bits description
Uint16 GPIO16:2; // 1:0 GPIO16
Uint16 GPIO17:2; // 3:2 GPIO17
Uint16 GPIO18:2; // 5:4 GPIO18
Uint16 GPIO19:2; // 7:6 GPIO19
Uint16 GPIO20:2; // 9:8 GPIO20
Uint16 GPIO21:2; // 11:10 GPIO21
Uint16 GPIO22:2; // 13:12 GPIO22
Uint16 GPIO23:2; // 15:14 GPIO23
Uint16 GPIO24:2; // 17:16 GPIO24
Uint16 GPIO25:2; // 19:18 GPIO25
Uint16 GPIO26:2; // 21:20 GPIO26
Uint16 GPIO27:2; // 23:22 GPIO27
Uint16 GPIO28:2; // 25:24 GPIO28
Uint16 GPIO29:2; // 27:26 GPIO29
Uint16 GPIO30:2; // 29:28 GPIO30
Uint16 GPIO31:2; // 31:30 GPIO31
};
struct GPB1_BITS { // bits description
Uint16 GPIO32:2; // 1:0 GPIO32
Uint16 GPIO33:2; // 3:2 GPIO33
Uint16 GPIO34:2; // 5:4 GPIO34
Uint16 GPIO35:2; // 7:6 GPIO35
Uint16 GPIO36:2; // 9:8 GPIO36
Uint16 GPIO37:2; // 11:10 GPIO37
Uint16 GPIO38:2; // 13:12 GPIO38
Uint16 GPIO39:2; // 15:14 GPIO39
Uint16 GPIO40:2; // 17:16 GPIO40
Uint16 GPIO41:2; // 19:16 GPIO41
Uint16 GPIO42:2; // 21:20 GPIO42
Uint16 GPIO43:2; // 23:22 GPIO43
Uint16 GPIO44:2; // 25:24 GPIO44
Uint16 GPIO45:2; // 27:26 GPIO45
Uint16 GPIO46:2; // 29:28 GPIO46
Uint16 GPIO47:2; // 31:30 GPIO47
};
struct GPB2_BITS { // bits description
Uint16 GPIO48:2; // 1:0 GPIO48
Uint16 GPIO49:2; // 3:2 GPIO49
Uint16 GPIO50:2; // 5:4 GPIO50
Uint16 GPIO51:2; // 7:6 GPIO51
Uint16 GPIO52:2; // 9:8 GPIO52
Uint16 GPIO53:2; // 11:10 GPIO53
Uint16 GPIO54:2; // 13:12 GPIO54
Uint16 GPIO55:2; // 15:14 GPIO55
Uint16 GPIO56:2; // 17:16 GPIO56
Uint16 GPIO57:2; // 19:18 GPIO57
Uint16 GPIO58:2; // 21:20 GPIO58
Uint16 GPIO59:2; // 23:22 GPIO59
Uint16 GPIO60:2; // 25:24 GPIO60
Uint16 GPIO61:2; // 27:26 GPIO61
Uint16 GPIO62:2; // 29:28 GPIO62
Uint16 GPIO63:2; // 31:30 GPIO63
};
struct GPC1_BITS { // bits description
Uint16 GPIO64:2; // 1:0 GPIO64
Uint16 GPIO65:2; // 3:2 GPIO65
Uint16 GPIO66:2; // 5:4 GPIO66
Uint16 GPIO67:2; // 7:6 GPIO67
Uint16 GPIO68:2; // 9:8 GPIO68
Uint16 GPIO69:2; // 11:10 GPIO69
Uint16 GPIO70:2; // 13:12 GPIO70
Uint16 GPIO71:2; // 15:14 GPIO71
Uint16 GPIO72:2; // 17:16 GPIO72
Uint16 GPIO73:2; // 19:18 GPIO73
Uint16 GPIO74:2; // 21:20 GPIO74
Uint16 GPIO75:2; // 23:22 GPIO75
Uint16 GPIO76:2; // 25:24 GPIO76
Uint16 GPIO77:2; // 27:26 GPIO77
Uint16 GPIO78:2; // 29:28 GPIO78
Uint16 GPIO79:2; // 31:30 GPIO79
};
struct GPC2_BITS { // bits description
Uint16 GPIO80:2; // 1:0 GPIO80
Uint16 GPIO81:2; // 3:2 GPIO81
Uint16 GPIO82:2; // 5:4 GPIO82
Uint16 GPIO83:2; // 7:6 GPIO83
Uint16 GPIO84:2; // 9:8 GPIO84
Uint16 GPIO85:2; // 11:10 GPIO85
Uint16 GPIO86:2; // 13:12 GPIO86
Uint16 GPIO87:2; // 15:14 GPIO87
Uint16 rsvd:16; // 31:16 reserved
};
union GPA1_REG {
Uint32 all;
struct GPA1_BITS bit;
};
union GPA2_REG {
Uint32 all;
struct GPA2_BITS bit;
};
union GPB1_REG {
Uint32 all;
struct GPB1_BITS bit;
};
union GPB2_REG {
Uint32 all;
struct GPB2_BITS bit;
};
union GPC1_REG {
Uint32 all;
struct GPC1_BITS bit;
};
union GPC2_REG {
Uint32 all;
struct GPC2_BITS bit;
};
//
// GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions
//
struct GPADAT_BITS { // bits description
Uint16 GPIO0:1; // 0 GPIO0
Uint16 GPIO1:1; // 1 GPIO1
Uint16 GPIO2:1; // 2 GPIO2
Uint16 GPIO3:1; // 3 GPIO3
Uint16 GPIO4:1; // 4 GPIO4
Uint16 GPIO5:1; // 5 GPIO5
Uint16 GPIO6:1; // 6 GPIO6
Uint16 GPIO7:1; // 7 GPIO7
Uint16 GPIO8:1; // 8 GPIO8
Uint16 GPIO9:1; // 9 GPIO9
Uint16 GPIO10:1; // 10 GPIO10
Uint16 GPIO11:1; // 11 GPIO11
Uint16 GPIO12:1; // 12 GPIO12
Uint16 GPIO13:1; // 13 GPIO13
Uint16 GPIO14:1; // 14 GPIO14
Uint16 GPIO15:1; // 15 GPIO15
Uint16 GPIO16:1; // 16 GPIO16
Uint16 GPIO17:1; // 17 GPIO17
Uint16 GPIO18:1; // 18 GPIO18
Uint16 GPIO19:1; // 19 GPIO19
Uint16 GPIO20:1; // 20 GPIO20
Uint16 GPIO21:1; // 21 GPIO21
Uint16 GPIO22:1; // 22 GPIO22
Uint16 GPIO23:1; // 23 GPIO23
Uint16 GPIO24:1; // 24 GPIO24
Uint16 GPIO25:1; // 25 GPIO25
Uint16 GPIO26:1; // 26 GPIO26
Uint16 GPIO27:1; // 27 GPIO27
Uint16 GPIO28:1; // 28 GPIO28
Uint16 GPIO29:1; // 29 GPIO29
Uint16 GPIO30:1; // 30 GPIO30
Uint16 GPIO31:1; // 31 GPIO31
};
struct GPBDAT_BITS { // bits description
Uint16 GPIO32:1; // 0 GPIO32
Uint16 GPIO33:1; // 1 GPIO33
Uint16 GPIO34:1; // 2 GPIO34
Uint16 GPIO35:1; // 3 GPIO35
Uint16 GPIO36:1; // 4 GPIO36
Uint16 GPIO37:1; // 5 GPIO37
Uint16 GPIO38:1; // 6 GPIO38
Uint16 GPIO39:1; // 7 GPIO39
Uint16 GPIO40:1; // 8 GPIO40
Uint16 GPIO41:1; // 9 GPIO41
Uint16 GPIO42:1; // 10 GPIO42
Uint16 GPIO43:1; // 11 GPIO43
Uint16 GPIO44:1; // 12 GPIO44
Uint16 GPIO45:1; // 13 GPIO45
Uint16 GPIO46:1; // 14 GPIO46
Uint16 GPIO47:1; // 15 GPIO47
Uint16 GPIO48:1; // 16 GPIO48
Uint16 GPIO49:1; // 17 GPIO49
Uint16 GPIO50:1; // 18 GPIO50
Uint16 GPIO51:1; // 19 GPIO51
Uint16 GPIO52:1; // 20 GPIO52
Uint16 GPIO53:1; // 21 GPIO53
Uint16 GPIO54:1; // 22 GPIO54
Uint16 GPIO55:1; // 23 GPIO55
Uint16 GPIO56:1; // 24 GPIO56
Uint16 GPIO57:1; // 25 GPIO57
Uint16 GPIO58:1; // 26 GPIO58
Uint16 GPIO59:1; // 27 GPIO59
Uint16 GPIO60:1; // 28 GPIO60
Uint16 GPIO61:1; // 29 GPIO61
Uint16 GPIO62:1; // 30 GPIO62
Uint16 GPIO63:1; // 31 GPIO63
};
struct GPCDAT_BITS { // bits description
Uint16 GPIO64:1; // 0 GPIO64
Uint16 GPIO65:1; // 1 GPIO65
Uint16 GPIO66:1; // 2 GPIO66
Uint16 GPIO67:1; // 3 GPIO67
Uint16 GPIO68:1; // 4 GPIO68
Uint16 GPIO69:1; // 5 GPIO69
Uint16 GPIO70:1; // 6 GPIO70
Uint16 GPIO71:1; // 7 GPIO71
Uint16 GPIO72:1; // 8 GPIO72
Uint16 GPIO73:1; // 9 GPIO73
Uint16 GPIO74:1; // 10 GPIO74
Uint16 GPIO75:1; // 11 GPIO75
Uint16 GPIO76:1; // 12 GPIO76
Uint16 GPIO77:1; // 13 GPIO77
Uint16 GPIO78:1; // 14 GPIO78
Uint16 GPIO79:1; // 15 GPIO79
Uint16 GPIO80:1; // 16 GPIO80
Uint16 GPIO81:1; // 17 GPIO81
Uint16 GPIO82:1; // 18 GPIO82
Uint16 GPIO83:1; // 19 GPIO83
Uint16 GPIO84:1; // 20 GPIO84
Uint16 GPIO85:1; // 21 GPIO85
Uint16 GPIO86:1; // 22 GPIO86
Uint16 GPIO87:1; // 23 GPIO87
Uint16 rsvd1:8; // 31:24 reserved
};
union GPADAT_REG {
Uint32 all;
struct GPADAT_BITS bit;
};
union GPBDAT_REG {
Uint32 all;
struct GPBDAT_BITS bit;
};
union GPCDAT_REG {
Uint32 all;
struct GPCDAT_BITS bit;
};
//
// GPIO Xint1/XINT2/XNMI select register bit definitions
//
struct GPIOXINT_BITS { // bits description
Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source
Uint16 rsvd1:11; // 15:5 reserved
};
union GPIOXINT_REG {
Uint16 all;
struct GPIOXINT_BITS bit;
};
struct GPIO_CTRL_REGS {
union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31)
//
// GPIO A Qualifier Select 1 Register (GPIO0 to 15)
//
union GPA1_REG GPAQSEL1;
//
// GPIO A Qualifier Select 2 Register (GPIO16 to 31)
//
union GPA2_REG GPAQSEL2;
//
// GPIO A Mux 1 Register (GPIO0 to 15)
//
union GPA1_REG GPAMUX1;
//
// GPIO A Mux 2 Register (GPIO16 to 31)
//
union GPA2_REG GPAMUX2;
union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31)
//
// GPIO A Pull Up Disable Register (GPIO0 to 31)
//
union GPADAT_REG GPAPUD;
Uint32 rsvd1;
union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63)
//
// GPIO B Qualifier Select 1 Register (GPIO32 to 47)
//
union GPB1_REG GPBQSEL1;
//
// GPIO B Qualifier Select 2 Register (GPIO48 to 63)
//
union GPB2_REG GPBQSEL2;
union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47)
union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63)
union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63)
//
// GPIO B Pull Up Disable Register (GPIO32 to 63)
//
union GPBDAT_REG GPBPUD;
Uint16 rsvd2[8];
union GPC1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79)
union GPC2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95)
union GPCDAT_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95)
//
// GPIO C Pull Up Disable Register (GPIO64 to 95)
//
union GPCDAT_REG GPCPUD;
};
struct GPIO_DATA_REGS {
union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31)
//
// GPIO Data Set Register (GPIO0 to 31)
//
union GPADAT_REG GPASET;
//
// GPIO Data Clear Register (GPIO0 to 31)
//
union GPADAT_REG GPACLEAR;
//
// GPIO Data Toggle Register (GPIO0 to 31)
//
union GPADAT_REG GPATOGGLE;
union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63)
//
// GPIO Data Set Register (GPIO32 to 63)
//
union GPBDAT_REG GPBSET;
//
// GPIO Data Clear Register (GPIO32 to 63)
//
union GPBDAT_REG GPBCLEAR;
//
// GPIO Data Toggle Register (GPIO32 to 63)
//
union GPBDAT_REG GPBTOGGLE;
union GPCDAT_REG GPCDAT; // GPIO Data Register (GPIO64 to 95)
union GPCDAT_REG GPCSET; // GPIO Data Set Register (GPIO64 to 95)
//
// GPIO Data Clear Register (GPIO64 to 95)
//
union GPCDAT_REG GPCCLEAR;
//
// GPIO Data Toggle Register (GPIO64 to 95)
//
union GPCDAT_REG GPCTOGGLE;
Uint16 rsvd1[8];
};
struct GPIO_INT_REGS {
union GPIOXINT_REG GPIOXINT1SEL; //XINT1 GPIO Input Selection
union GPIOXINT_REG GPIOXINT2SEL; //XINT2 GPIO Input Selection
union GPIOXINT_REG GPIOXNMISEL; //XNMI_Xint13 GPIO Input Selection
union GPIOXINT_REG GPIOXINT3SEL; //XINT3 GPIO Input Selection
union GPIOXINT_REG GPIOXINT4SEL; //XINT4 GPIO Input Selection
union GPIOXINT_REG GPIOXINT5SEL; //XINT5 GPIO Input Selection
union GPIOXINT_REG GPIOXINT6SEL; //XINT6 GPIO Input Selection
union GPIOXINT_REG GPIOXINT7SEL; //XINT7 GPIO Input Selection
union GPADAT_REG GPIOLPMSEL; //Low power modes GP I/O input select
};
//
// GPI/O External References & Function Declarations
//
extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
extern volatile struct GPIO_DATA_REGS GpioDataRegs;
extern volatile struct GPIO_INT_REGS GpioIntRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_GPIO_H definition
//
// End of file
//

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F28335/DSP2833x_I2c.h
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//###########################################################################
//
// FILE: DSP2833x_I2c.h
//
// TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module
// Register Bit Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_I2C_H
#define DSP2833x_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
//
// I2C interrupt vector register bit definitions
//
struct I2CISRC_BITS { // bits description
Uint16 INTCODE:3; // 2:0 Interrupt code
Uint16 rsvd1:13; // 15:3 reserved
};
union I2CISRC_REG {
Uint16 all;
struct I2CISRC_BITS bit;
};
//
// I2C interrupt mask register bit definitions
//
struct I2CIER_BITS { // bits description
Uint16 ARBL:1; // 0 Arbitration lost interrupt
Uint16 NACK:1; // 1 No ack interrupt
Uint16 ARDY:1; // 2 Register access ready interrupt
Uint16 RRDY:1; // 3 Recieve data ready interrupt
Uint16 XRDY:1; // 4 Transmit data ready interrupt
Uint16 SCD:1; // 5 Stop condition detection
Uint16 AAS:1; // 6 Address as slave
Uint16 rsvd:9; // 15:7 reserved
};
union I2CIER_REG {
Uint16 all;
struct I2CIER_BITS bit;
};
//
// I2C status register bit definitions
//
struct I2CSTR_BITS { // bits description
Uint16 ARBL:1; // 0 Arbitration lost interrupt
Uint16 NACK:1; // 1 No ack interrupt
Uint16 ARDY:1; // 2 Register access ready interrupt
Uint16 RRDY:1; // 3 Recieve data ready interrupt
Uint16 XRDY:1; // 4 Transmit data ready interrupt
Uint16 SCD:1; // 5 Stop condition detection
Uint16 rsvd1:2; // 7:6 reserved
Uint16 AD0:1; // 8 Address Zero
Uint16 AAS:1; // 9 Address as slave
Uint16 XSMT:1; // 10 XMIT shift empty
Uint16 RSFULL:1; // 11 Recieve shift full
Uint16 BB:1; // 12 Bus busy
Uint16 NACKSNT:1; // 13 A no ack sent
Uint16 SDIR:1; // 14 Slave direction
Uint16 rsvd2:1; // 15 reserved
};
union I2CSTR_REG {
Uint16 all;
struct I2CSTR_BITS bit;
};
//
// I2C mode control register bit definitions
//
struct I2CMDR_BITS { // bits description
Uint16 BC:3; // 2:0 Bit count
Uint16 FDF:1; // 3 Free data format
Uint16 STB:1; // 4 Start byte
Uint16 IRS:1; // 5 I2C Reset not
Uint16 DLB:1; // 6 Digital loopback
Uint16 RM:1; // 7 Repeat mode
Uint16 XA:1; // 8 Expand address
Uint16 TRX:1; // 9 Transmitter/reciever
Uint16 MST:1; // 10 Master/slave
Uint16 STP:1; // 11 Stop condition
Uint16 rsvd1:1; // 12 reserved
Uint16 STT:1; // 13 Start condition
Uint16 FREE:1; // 14 Emulation mode
Uint16 NACKMOD:1; // 15 No Ack mode
};
union I2CMDR_REG {
Uint16 all;
struct I2CMDR_BITS bit;
};
//
// I2C extended mode control register bit definitions
//
struct I2CEMDR_BITS { // bits description
Uint16 BCM:1; // 0 Backward compatibility mode
Uint16 rsvd:15; // 15 reserved
};
union I2CEMDR_REG {
Uint16 all;
struct I2CEMDR_BITS bit;
};
//
// I2C pre-scaler register bit definitions
//
struct I2CPSC_BITS { // bits description
Uint16 IPSC:8; // 7:0 pre-scaler
Uint16 rsvd1:8; // 15:8 reserved
};
union I2CPSC_REG {
Uint16 all;
struct I2CPSC_BITS bit;
};
//
// TX FIFO control register bit definitions
//
struct I2CFFTX_BITS { // bits description
Uint16 TXFFIL:5; // 4:0 FIFO interrupt level
Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable
Uint16 TXFFINTCLR:1; // 6 FIFO clear
Uint16 TXFFINT:1; // 7 FIFO interrupt flag
Uint16 TXFFST:5; // 12:8 FIFO level status
Uint16 TXFFRST:1; // 13 FIFO reset
Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs
Uint16 rsvd1:1; // 15 reserved
};
union I2CFFTX_REG {
Uint16 all;
struct I2CFFTX_BITS bit;
};
//
// RX FIFO control register bit definitions
//
struct I2CFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 FIFO interrupt level
Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable
Uint16 RXFFINTCLR:1; // 6 FIFO clear
Uint16 RXFFINT:1; // 7 FIFO interrupt flag
Uint16 RXFFST:5; // 12:8 FIFO level
Uint16 RXFFRST:1; // 13 FIFO reset
Uint16 rsvd1:2; // 15:14 reserved
};
union I2CFFRX_REG {
Uint16 all;
struct I2CFFRX_BITS bit;
};
struct I2C_REGS {
Uint16 I2COAR; // Own address register
union I2CIER_REG I2CIER; // Interrupt enable
union I2CSTR_REG I2CSTR; // Interrupt status
Uint16 I2CCLKL; // Clock divider low
Uint16 I2CCLKH; // Clock divider high
Uint16 I2CCNT; // Data count
Uint16 I2CDRR; // Data recieve
Uint16 I2CSAR; // Slave address
Uint16 I2CDXR; // Data transmit
union I2CMDR_REG I2CMDR; // Mode
union I2CISRC_REG I2CISRC; // Interrupt source
union I2CEMDR_REG I2CEMDR; // Extended Mode
union I2CPSC_REG I2CPSC; // Pre-scaler
Uint16 rsvd2[19]; // reserved
union I2CFFTX_REG I2CFFTX; // Transmit FIFO
union I2CFFRX_REG I2CFFRX; // Recieve FIFO
};
//
// External References & Function Declarations
//
extern volatile struct I2C_REGS I2caRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_I2C_H definition
//
// End of file
//

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F28335/DSP2833x_I2c_defines.h
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//###########################################################################
//
// FILE: DSP2833x_I2cExample.h
//
// TITLE: 2833x I2C Example Code Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_I2C_DEFINES_H
#define DSP2833x_I2C_DEFINES_H
//
// Defines
//
//
// Error Messages
//
#define I2C_ERROR 0xFFFF
#define I2C_ARB_LOST_ERROR 0x0001
#define I2C_NACK_ERROR 0x0002
#define I2C_BUS_BUSY_ERROR 0x1000
#define I2C_STP_NOT_READY_ERROR 0x5555
#define I2C_NO_FLAGS 0xAAAA
#define I2C_SUCCESS 0x0000
//
// Clear Status Flags
//
#define I2C_CLR_AL_BIT 0x0001
#define I2C_CLR_NACK_BIT 0x0002
#define I2C_CLR_ARDY_BIT 0x0004
#define I2C_CLR_RRDY_BIT 0x0008
#define I2C_CLR_SCD_BIT 0x0020
//
// Interrupt Source Messages
//
#define I2C_NO_ISRC 0x0000
#define I2C_ARB_ISRC 0x0001
#define I2C_NACK_ISRC 0x0002
#define I2C_ARDY_ISRC 0x0003
#define I2C_RX_ISRC 0x0004
#define I2C_TX_ISRC 0x0005
#define I2C_SCD_ISRC 0x0006
#define I2C_AAS_ISRC 0x0007
//
// I2CMSG structure defines
//
#define I2C_NO_STOP 0
#define I2C_YES_STOP 1
#define I2C_RECEIVE 0
#define I2C_TRANSMIT 1
#define I2C_MAX_BUFFER_SIZE 16
//
// I2C Slave State defines
//
#define I2C_NOTSLAVE 0
#define I2C_ADDR_AS_SLAVE 1
#define I2C_ST_MSG_READY 2
//
// I2C Slave Receiver messages defines
//
#define I2C_SND_MSG1 1
#define I2C_SND_MSG2 2
//
// I2C State defines
//
#define I2C_IDLE 0
#define I2C_SLAVE_RECEIVER 1
#define I2C_SLAVE_TRANSMITTER 2
#define I2C_MASTER_RECEIVER 3
#define I2C_MASTER_TRANSMITTER 4
//
// I2C Message Commands for I2CMSG struct
//
#define I2C_MSGSTAT_INACTIVE 0x0000
#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010
#define I2C_MSGSTAT_WRITE_BUSY 0x0011
#define I2C_MSGSTAT_SEND_NOSTOP 0x0020
#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021
#define I2C_MSGSTAT_RESTART 0x0022
#define I2C_MSGSTAT_READ_BUSY 0x0023
//
// Generic defines
//
#define I2C_TRUE 1
#define I2C_FALSE 0
#define I2C_YES 1
#define I2C_NO 0
#define I2C_DUMMY_BYTE 0
//
// Structures
//
//
// I2C Message Structure
//
struct I2CMSG
{
Uint16 MsgStatus; // Word stating what state msg is in:
// I2C_MSGCMD_INACTIVE = do not send msg
// I2C_MSGCMD_BUSY = msg start has been sent,
// awaiting stop
// I2C_MSGCMD_SEND_WITHSTOP = command to send
// master trans msg complete with a stop bit
// I2C_MSGCMD_SEND_NOSTOP = command to send
// master trans msg without the stop bit
// I2C_MSGCMD_RESTART = command to send a restart
// as a master receiver with a stop bit
Uint16 SlaveAddress; // I2C address of slave msg is intended for
Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer)
//
// EEPROM address of data associated with msg (high byte)
//
Uint16 MemoryHighAddr;
//
// EEPROM address of data associated with msg (low byte)
//
Uint16 MemoryLowAddr;
//
// Array holding msg data - max that MAX_BUFFER_SIZE can be is 16 due to
// the FIFO's
Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE];
};
#endif // end of DSP2833x_I2C_DEFINES_H definition
//
// End of file
//

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F28335/DSP2833x_Mcbsp.h
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//###########################################################################
//
// FILE: DSP2833x_Mcbsp.h
//
// TITLE: DSP2833x Device McBSP Register Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_MCBSP_H
#define DSP2833x_MCBSP_H
#ifdef __cplusplus
extern "C" {
#endif
//
// McBSP Individual Register Bit Definitions
//
//
// McBSP DRR2 register bit definitions
//
struct DRR2_BITS { // bit description
Uint16 HWLB:8; // 16:23 High word low byte
Uint16 HWHB:8; // 24:31 High word high byte
};
union DRR2_REG {
Uint16 all;
struct DRR2_BITS bit;
};
//
// McBSP DRR1 register bit definitions
//
struct DRR1_BITS { // bit description
Uint16 LWLB:8; // 16:23 Low word low byte
Uint16 LWHB:8; // 24:31 low word high byte
};
union DRR1_REG {
Uint16 all;
struct DRR1_BITS bit;
};
//
// McBSP DXR2 register bit definitions
//
struct DXR2_BITS { // bit description
Uint16 HWLB:8; // 16:23 High word low byte
Uint16 HWHB:8; // 24:31 High word high byte
};
union DXR2_REG {
Uint16 all;
struct DXR2_BITS bit;
};
//
// McBSP DXR1 register bit definitions
//
struct DXR1_BITS { // bit description
Uint16 LWLB:8; // 16:23 Low word low byte
Uint16 LWHB:8; // 24:31 low word high byte
};
union DXR1_REG {
Uint16 all;
struct DXR1_BITS bit;
};
//
// SPCR2 control register bit definitions
//
struct SPCR2_BITS { // bit description
Uint16 XRST:1; // 0 transmit reset
Uint16 XRDY:1; // 1 transmit ready
Uint16 XEMPTY:1; // 2 Transmit empty
Uint16 XSYNCERR:1; // 3 Transmit syn errorINT flag
Uint16 XINTM:2; // 5:4 Transmit interrupt types
Uint16 GRST:1; // 6 CLKG reset
Uint16 FRST:1; // 7 Frame sync reset
Uint16 SOFT:1; // 8 SOFT bit
Uint16 FREE:1; // 9 FREE bit
Uint16 rsvd:6; // 15:10 reserved
};
union SPCR2_REG {
Uint16 all;
struct SPCR2_BITS bit;
};
//
// SPCR1 control register bit definitions
//
struct SPCR1_BITS { // bit description
Uint16 RRST:1; // 0 Receive reset
Uint16 RRDY:1; // 1 Receive ready
Uint16 RFULL:1; // 2 Receive full
Uint16 RSYNCERR:1; // 7 Receive syn error
Uint16 RINTM:2; // 5:4 Receive interrupt types
Uint16 rsvd1:1; // 6 reserved
Uint16 DXENA:1; // 7 DX hi-z enable
Uint16 rsvd2:3; // 10:8 reserved
Uint16 CLKSTP:2; // 12:11 CLKSTOP mode bit
Uint16 RJUST:2; // 13:14 Right justified
Uint16 DLB:1; // 15 Digital loop back
};
union SPCR1_REG {
Uint16 all;
struct SPCR1_BITS bit;
};
//
// RCR2 control register bit definitions
//
struct RCR2_BITS { // bit description
Uint16 RDATDLY:2; // 1:0 Receive data delay
Uint16 RFIG:1; // 2 Receive frame sync ignore
Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects
Uint16 RWDLEN2:3; // 7:5 Receive word length
Uint16 RFRLEN2:7; // 14:8 Receive Frame sync
Uint16 RPHASE:1; // 15 Receive Phase
};
union RCR2_REG {
Uint16 all;
struct RCR2_BITS bit;
};
//
// RCR1 control register bit definitions
//
struct RCR1_BITS { // bit description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 RWDLEN1:3; // 7:5 Receive word length
Uint16 RFRLEN1:7; // 14:8 Receive frame length
Uint16 rsvd2:1; // 15 reserved
};
union RCR1_REG {
Uint16 all;
struct RCR1_BITS bit;
};
//
// XCR2 control register bit definitions
//
struct XCR2_BITS { // bit description
Uint16 XDATDLY:2; // 1:0 Transmit data delay
Uint16 XFIG:1; // 2 Transmit frame sync ignore
Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects
Uint16 XWDLEN2:3; // 7:5 Transmit word length
Uint16 XFRLEN2:7; // 14:8 Transmit Frame sync
Uint16 XPHASE:1; // 15 Transmit Phase
};
union XCR2_REG {
Uint16 all;
struct XCR2_BITS bit;
};
//
// XCR1 control register bit definitions
//
struct XCR1_BITS { // bit description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 XWDLEN1:3; // 7:5 Transmit word length
Uint16 XFRLEN1:7; // 14:8 Transmit frame length
Uint16 rsvd2:1; // 15 reserved
};
union XCR1_REG {
Uint16 all;
struct XCR1_BITS bit;
};
//
// SRGR2 Sample rate generator control register bit definitions
//
struct SRGR2_BITS { // bit description
Uint16 FPER:12; // 11:0 Frame period
Uint16 FSGM:1; // 12 Frame sync generator mode
Uint16 CLKSM:1; // 13 Sample rate generator mode
Uint16 rsvd:1; // 14 reserved
Uint16 GSYNC:1; // 15 CLKG sync
};
union SRGR2_REG {
Uint16 all;
struct SRGR2_BITS bit;
};
//
// SRGR1 control register bit definitions
//
struct SRGR1_BITS { // bit description
Uint16 CLKGDV:8; // 7:0 CLKG divider
Uint16 FWID:8; // 15:8 Frame width
};
union SRGR1_REG {
Uint16 all;
struct SRGR1_BITS bit;
};
//
// MCR2 Multichannel control register bit definitions
//
struct MCR2_BITS { // bit description
Uint16 XMCM:2; // 1:0 Transmit multichannel mode
Uint16 XCBLK:3; // 2:4 Transmit current block
Uint16 XPABLK:2; // 5:6 Transmit partition A Block
Uint16 XPBBLK:2; // 7:8 Transmit partition B Block
Uint16 XMCME:1; // 9 Transmit multi-channel enhance mode
Uint16 rsvd:6; // 15:10 reserved
};
union MCR2_REG {
Uint16 all;
struct MCR2_BITS bit;
};
//
// MCR1 Multichannel control register bit definitions
//
struct MCR1_BITS { // bit description
Uint16 RMCM:1; // 0 Receive multichannel mode
Uint16 rsvd:1; // 1 reserved
Uint16 RCBLK:3; // 4:2 Receive current block
Uint16 RPABLK:2; // 6:5 Receive partition A Block
Uint16 RPBBLK:2; // 7:8 Receive partition B Block
Uint16 RMCME:1; // 9 Receive multi-channel enhance mode
Uint16 rsvd1:6; // 15:10 reserved
};
union MCR1_REG {
Uint16 all;
struct MCR1_BITS bit;
};
//
// RCERA control register bit definitions
//
struct RCERA_BITS { // bit description
Uint16 RCEA0:1; // 0 Receive Channel enable bit
Uint16 RCEA1:1; // 1 Receive Channel enable bit
Uint16 RCEA2:1; // 2 Receive Channel enable bit
Uint16 RCEA3:1; // 3 Receive Channel enable bit
Uint16 RCEA4:1; // 4 Receive Channel enable bit
Uint16 RCEA5:1; // 5 Receive Channel enable bit
Uint16 RCEA6:1; // 6 Receive Channel enable bit
Uint16 RCEA7:1; // 7 Receive Channel enable bit
Uint16 RCEA8:1; // 8 Receive Channel enable bit
Uint16 RCEA9:1; // 9 Receive Channel enable bit
Uint16 RCEA10:1; // 10 Receive Channel enable bit
Uint16 RCEA11:1; // 11 Receive Channel enable bit
Uint16 RCEA12:1; // 12 Receive Channel enable bit
Uint16 RCEA13:1; // 13 Receive Channel enable bit
Uint16 RCEA14:1; // 14 Receive Channel enable bit
Uint16 RCEA15:1; // 15 Receive Channel enable bit
};
union RCERA_REG {
Uint16 all;
struct RCERA_BITS bit;
};
//
// RCERB control register bit definitions
//
struct RCERB_BITS { // bit description
Uint16 RCEB0:1; // 0 Receive Channel enable bit
Uint16 RCEB1:1; // 1 Receive Channel enable bit
Uint16 RCEB2:1; // 2 Receive Channel enable bit
Uint16 RCEB3:1; // 3 Receive Channel enable bit
Uint16 RCEB4:1; // 4 Receive Channel enable bit
Uint16 RCEB5:1; // 5 Receive Channel enable bit
Uint16 RCEB6:1; // 6 Receive Channel enable bit
Uint16 RCEB7:1; // 7 Receive Channel enable bit
Uint16 RCEB8:1; // 8 Receive Channel enable bit
Uint16 RCEB9:1; // 9 Receive Channel enable bit
Uint16 RCEB10:1; // 10 Receive Channel enable bit
Uint16 RCEB11:1; // 11 Receive Channel enable bit
Uint16 RCEB12:1; // 12 Receive Channel enable bit
Uint16 RCEB13:1; // 13 Receive Channel enable bit
Uint16 RCEB14:1; // 14 Receive Channel enable bit
Uint16 RCEB15:1; // 15 Receive Channel enable bit
};
union RCERB_REG {
Uint16 all;
struct RCERB_BITS bit;
};
//
// XCERA control register bit definitions
//
struct XCERA_BITS { // bit description
Uint16 XCERA0:1; // 0 Receive Channel enable bit
Uint16 XCERA1:1; // 1 Receive Channel enable bit
Uint16 XCERA2:1; // 2 Receive Channel enable bit
Uint16 XCERA3:1; // 3 Receive Channel enable bit
Uint16 XCERA4:1; // 4 Receive Channel enable bit
Uint16 XCERA5:1; // 5 Receive Channel enable bit
Uint16 XCERA6:1; // 6 Receive Channel enable bit
Uint16 XCERA7:1; // 7 Receive Channel enable bit
Uint16 XCERA8:1; // 8 Receive Channel enable bit
Uint16 XCERA9:1; // 9 Receive Channel enable bit
Uint16 XCERA10:1; // 10 Receive Channel enable bit
Uint16 XCERA11:1; // 11 Receive Channel enable bit
Uint16 XCERA12:1; // 12 Receive Channel enable bit
Uint16 XCERA13:1; // 13 Receive Channel enable bit
Uint16 XCERA14:1; // 14 Receive Channel enable bit
Uint16 XCERA15:1; // 15 Receive Channel enable bit
};
union XCERA_REG {
Uint16 all;
struct XCERA_BITS bit;
};
//
// XCERB control register bit definitions
//
struct XCERB_BITS { // bit description
Uint16 XCERB0:1; // 0 Receive Channel enable bit
Uint16 XCERB1:1; // 1 Receive Channel enable bit
Uint16 XCERB2:1; // 2 Receive Channel enable bit
Uint16 XCERB3:1; // 3 Receive Channel enable bit
Uint16 XCERB4:1; // 4 Receive Channel enable bit
Uint16 XCERB5:1; // 5 Receive Channel enable bit
Uint16 XCERB6:1; // 6 Receive Channel enable bit
Uint16 XCERB7:1; // 7 Receive Channel enable bit
Uint16 XCERB8:1; // 8 Receive Channel enable bit
Uint16 XCERB9:1; // 9 Receive Channel enable bit
Uint16 XCERB10:1; // 10 Receive Channel enable bit
Uint16 XCERB11:1; // 11 Receive Channel enable bit
Uint16 XCERB12:1; // 12 Receive Channel enable bit
Uint16 XCERB13:1; // 13 Receive Channel enable bit
Uint16 XCERB14:1; // 14 Receive Channel enable bit
Uint16 XCERB15:1; // 15 Receive Channel enable bit
};
union XCERB_REG {
Uint16 all;
struct XCERB_BITS bit;
};
//
// PCR control register bit definitions
//
struct PCR_BITS { // bit description
Uint16 CLKRP:1; // 0 Receive Clock polarity
Uint16 CLKXP:1; // 1 Transmit clock polarity
Uint16 FSRP:1; // 2 Receive Frame synchronization polarity
Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity
Uint16 DR_STAT:1; // 4 DR pin status - reserved for this McBSP
Uint16 DX_STAT:1; // 5 DX pin status - reserved for this McBSP
Uint16 CLKS_STAT:1; // 6 CLKS pin status - reserved for 28x -McBSP
Uint16 SCLKME:1; // 7 Enhanced sample clock mode selection bit.
Uint16 CLKRM:1; // 8 Receiver Clock Mode
Uint16 CLKXM:1; // 9 Transmitter Clock Mode.
Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode
Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode
Uint16 RIOEN:1; // 12 General Purpose I/O Mode - reserved in
// this 28x-McBSP
Uint16 XIOEN:1; // 13 General Purpose I/O Mode - reserved in
// this 28x-McBSP
Uint16 IDEL_EN:1; // 14 reserved in this 28x-McBSP
Uint16 rsvd:1 ; // 15 reserved
};
union PCR_REG {
Uint16 all;
struct PCR_BITS bit;
};
//
// RCERC control register bit definitions
//
struct RCERC_BITS { // bit description
Uint16 RCEC0:1; // 0 Receive Channel enable bit
Uint16 RCEC1:1; // 1 Receive Channel enable bit
Uint16 RCEC2:1; // 2 Receive Channel enable bit
Uint16 RCEC3:1; // 3 Receive Channel enable bit
Uint16 RCEC4:1; // 4 Receive Channel enable bit
Uint16 RCEC5:1; // 5 Receive Channel enable bit
Uint16 RCEC6:1; // 6 Receive Channel enable bit
Uint16 RCEC7:1; // 7 Receive Channel enable bit
Uint16 RCEC8:1; // 8 Receive Channel enable bit
Uint16 RCEC9:1; // 9 Receive Channel enable bit
Uint16 RCEC10:1; // 10 Receive Channel enable bit
Uint16 RCEC11:1; // 11 Receive Channel enable bit
Uint16 RCEC12:1; // 12 Receive Channel enable bit
Uint16 RCEC13:1; // 13 Receive Channel enable bit
Uint16 RCEC14:1; // 14 Receive Channel enable bit
Uint16 RCEC15:1; // 15 Receive Channel enable bit
};
union RCERC_REG {
Uint16 all;
struct RCERC_BITS bit;
};
//
// RCERD control register bit definitions
//
struct RCERD_BITS { // bit description
Uint16 RCED0:1; // 0 Receive Channel enable bit
Uint16 RCED1:1; // 1 Receive Channel enable bit
Uint16 RCED2:1; // 2 Receive Channel enable bit
Uint16 RCED3:1; // 3 Receive Channel enable bit
Uint16 RCED4:1; // 4 Receive Channel enable bit
Uint16 RCED5:1; // 5 Receive Channel enable bit
Uint16 RCED6:1; // 6 Receive Channel enable bit
Uint16 RCED7:1; // 7 Receive Channel enable bit
Uint16 RCED8:1; // 8 Receive Channel enable bit
Uint16 RCED9:1; // 9 Receive Channel enable bit
Uint16 RCED10:1; // 10 Receive Channel enable bit
Uint16 RCED11:1; // 11 Receive Channel enable bit
Uint16 RCED12:1; // 12 Receive Channel enable bit
Uint16 RCED13:1; // 13 Receive Channel enable bit
Uint16 RCED14:1; // 14 Receive Channel enable bit
Uint16 RCED15:1; // 15 Receive Channel enable bit
};
union RCERD_REG {
Uint16 all;
struct RCERD_BITS bit;
};
//
// XCERC control register bit definitions
//
struct XCERC_BITS { // bit description
Uint16 XCERC0:1; // 0 Receive Channel enable bit
Uint16 XCERC1:1; // 1 Receive Channel enable bit
Uint16 XCERC2:1; // 2 Receive Channel enable bit
Uint16 XCERC3:1; // 3 Receive Channel enable bit
Uint16 XCERC4:1; // 4 Receive Channel enable bit
Uint16 XCERC5:1; // 5 Receive Channel enable bit
Uint16 XCERC6:1; // 6 Receive Channel enable bit
Uint16 XCERC7:1; // 7 Receive Channel enable bit
Uint16 XCERC8:1; // 8 Receive Channel enable bit
Uint16 XCERC9:1; // 9 Receive Channel enable bit
Uint16 XCERC10:1; // 10 Receive Channel enable bit
Uint16 XCERC11:1; // 11 Receive Channel enable bit
Uint16 XCERC12:1; // 12 Receive Channel enable bit
Uint16 XCERC13:1; // 13 Receive Channel enable bit
Uint16 XCERC14:1; // 14 Receive Channel enable bit
Uint16 XCERC15:1; // 15 Receive Channel enable bit
};
union XCERC_REG {
Uint16 all;
struct XCERC_BITS bit;
};
//
// XCERD control register bit definitions
//
struct XCERD_BITS { // bit description
Uint16 XCERD0:1; // 0 Receive Channel enable bit
Uint16 XCERD1:1; // 1 Receive Channel enable bit
Uint16 XCERD2:1; // 2 Receive Channel enable bit
Uint16 XCERD3:1; // 3 Receive Channel enable bit
Uint16 XCERD4:1; // 4 Receive Channel enable bit
Uint16 XCERD5:1; // 5 Receive Channel enable bit
Uint16 XCERD6:1; // 6 Receive Channel enable bit
Uint16 XCERD7:1; // 7 Receive Channel enable bit
Uint16 XCERD8:1; // 8 Receive Channel enable bit
Uint16 XCERD9:1; // 9 Receive Channel enable bit
Uint16 XCERD10:1; // 10 Receive Channel enable bit
Uint16 XCERD11:1; // 11 Receive Channel enable bit
Uint16 XCERD12:1; // 12 Receive Channel enable bit
Uint16 XCERD13:1; // 13 Receive Channel enable bit
Uint16 XCERD14:1; // 14 Receive Channel enable bit
Uint16 XCERD15:1; // 15 Receive Channel enable bit
};
union XCERD_REG {
Uint16 all;
struct XCERD_BITS bit;
};
//
// RCERE control register bit definitions
//
struct RCERE_BITS { // bit description
Uint16 RCEE0:1; // 0 Receive Channel enable bit
Uint16 RCEE1:1; // 1 Receive Channel enable bit
Uint16 RCEE2:1; // 2 Receive Channel enable bit
Uint16 RCEE3:1; // 3 Receive Channel enable bit
Uint16 RCEE4:1; // 4 Receive Channel enable bit
Uint16 RCEE5:1; // 5 Receive Channel enable bit
Uint16 RCEE6:1; // 6 Receive Channel enable bit
Uint16 RCEE7:1; // 7 Receive Channel enable bit
Uint16 RCEE8:1; // 8 Receive Channel enable bit
Uint16 RCEE9:1; // 9 Receive Channel enable bit
Uint16 RCEE10:1; // 10 Receive Channel enable bit
Uint16 RCEE11:1; // 11 Receive Channel enable bit
Uint16 RCEE12:1; // 12 Receive Channel enable bit
Uint16 RCEE13:1; // 13 Receive Channel enable bit
Uint16 RCEE14:1; // 14 Receive Channel enable bit
Uint16 RCEE15:1; // 15 Receive Channel enable bit
};
union RCERE_REG {
Uint16 all;
struct RCERE_BITS bit;
};
//
// RCERF control register bit definitions
//
struct RCERF_BITS { // bit description
Uint16 RCEF0:1; // 0 Receive Channel enable bit
Uint16 RCEF1:1; // 1 Receive Channel enable bit
Uint16 RCEF2:1; // 2 Receive Channel enable bit
Uint16 RCEF3:1; // 3 Receive Channel enable bit
Uint16 RCEF4:1; // 4 Receive Channel enable bit
Uint16 RCEF5:1; // 5 Receive Channel enable bit
Uint16 RCEF6:1; // 6 Receive Channel enable bit
Uint16 RCEF7:1; // 7 Receive Channel enable bit
Uint16 RCEF8:1; // 8 Receive Channel enable bit
Uint16 RCEF9:1; // 9 Receive Channel enable bit
Uint16 RCEF10:1; // 10 Receive Channel enable bit
Uint16 RCEF11:1; // 11 Receive Channel enable bit
Uint16 RCEF12:1; // 12 Receive Channel enable bit
Uint16 RCEF13:1; // 13 Receive Channel enable bit
Uint16 RCEF14:1; // 14 Receive Channel enable bit
Uint16 RCEF15:1; // 15 Receive Channel enable bit
};
union RCERF_REG {
Uint16 all;
struct RCERF_BITS bit;
};
// XCERE control register bit definitions:
struct XCERE_BITS { // bit description
Uint16 XCERE0:1; // 0 Receive Channel enable bit
Uint16 XCERE1:1; // 1 Receive Channel enable bit
Uint16 XCERE2:1; // 2 Receive Channel enable bit
Uint16 XCERE3:1; // 3 Receive Channel enable bit
Uint16 XCERE4:1; // 4 Receive Channel enable bit
Uint16 XCERE5:1; // 5 Receive Channel enable bit
Uint16 XCERE6:1; // 6 Receive Channel enable bit
Uint16 XCERE7:1; // 7 Receive Channel enable bit
Uint16 XCERE8:1; // 8 Receive Channel enable bit
Uint16 XCERE9:1; // 9 Receive Channel enable bit
Uint16 XCERE10:1; // 10 Receive Channel enable bit
Uint16 XCERE11:1; // 11 Receive Channel enable bit
Uint16 XCERE12:1; // 12 Receive Channel enable bit
Uint16 XCERE13:1; // 13 Receive Channel enable bit
Uint16 XCERE14:1; // 14 Receive Channel enable bit
Uint16 XCERE15:1; // 15 Receive Channel enable bit
};
union XCERE_REG {
Uint16 all;
struct XCERE_BITS bit;
};
//
// XCERF control register bit definitions
//
struct XCERF_BITS { // bit description
Uint16 XCERF0:1; // 0 Receive Channel enable bit
Uint16 XCERF1:1; // 1 Receive Channel enable bit
Uint16 XCERF2:1; // 2 Receive Channel enable bit
Uint16 XCERF3:1; // 3 Receive Channel enable bit
Uint16 XCERF4:1; // 4 Receive Channel enable bit
Uint16 XCERF5:1; // 5 Receive Channel enable bit
Uint16 XCERF6:1; // 6 Receive Channel enable bit
Uint16 XCERF7:1; // 7 Receive Channel enable bit
Uint16 XCERF8:1; // 8 Receive Channel enable bit
Uint16 XCERF9:1; // 9 Receive Channel enable bit
Uint16 XCERF10:1; // 10 Receive Channel enable bit
Uint16 XCERF11:1; // 11 Receive Channel enable bit
Uint16 XCERF12:1; // 12 Receive Channel enable bit
Uint16 XCERF13:1; // 13 Receive Channel enable bit
Uint16 XCERF14:1; // 14 Receive Channel enable bit
Uint16 XCERF15:1; // 15 Receive Channel enable bit
};
union XCERF_REG {
Uint16 all;
struct XCERF_BITS bit;
};
//
// RCERG control register bit definitions
//
struct RCERG_BITS { // bit description
Uint16 RCEG0:1; // 0 Receive Channel enable bit
Uint16 RCEG1:1; // 1 Receive Channel enable bit
Uint16 RCEG2:1; // 2 Receive Channel enable bit
Uint16 RCEG3:1; // 3 Receive Channel enable bit
Uint16 RCEG4:1; // 4 Receive Channel enable bit
Uint16 RCEG5:1; // 5 Receive Channel enable bit
Uint16 RCEG6:1; // 6 Receive Channel enable bit
Uint16 RCEG7:1; // 7 Receive Channel enable bit
Uint16 RCEG8:1; // 8 Receive Channel enable bit
Uint16 RCEG9:1; // 9 Receive Channel enable bit
Uint16 RCEG10:1; // 10 Receive Channel enable bit
Uint16 RCEG11:1; // 11 Receive Channel enable bit
Uint16 RCEG12:1; // 12 Receive Channel enable bit
Uint16 RCEG13:1; // 13 Receive Channel enable bit
Uint16 RCEG14:1; // 14 Receive Channel enable bit
Uint16 RCEG15:1; // 15 Receive Channel enable bit
};
union RCERG_REG {
Uint16 all;
struct RCERG_BITS bit;
};
// RCERH control register bit definitions:
struct RCERH_BITS { // bit description
Uint16 RCEH0:1; // 0 Receive Channel enable bit
Uint16 RCEH1:1; // 1 Receive Channel enable bit
Uint16 RCEH2:1; // 2 Receive Channel enable bit
Uint16 RCEH3:1; // 3 Receive Channel enable bit
Uint16 RCEH4:1; // 4 Receive Channel enable bit
Uint16 RCEH5:1; // 5 Receive Channel enable bit
Uint16 RCEH6:1; // 6 Receive Channel enable bit
Uint16 RCEH7:1; // 7 Receive Channel enable bit
Uint16 RCEH8:1; // 8 Receive Channel enable bit
Uint16 RCEH9:1; // 9 Receive Channel enable bit
Uint16 RCEH10:1; // 10 Receive Channel enable bit
Uint16 RCEH11:1; // 11 Receive Channel enable bit
Uint16 RCEH12:1; // 12 Receive Channel enable bit
Uint16 RCEH13:1; // 13 Receive Channel enable bit
Uint16 RCEH14:1; // 14 Receive Channel enable bit
Uint16 RCEH15:1; // 15 Receive Channel enable bit
};
union RCERH_REG {
Uint16 all;
struct RCERH_BITS bit;
};
//
// XCERG control register bit definitions
//
struct XCERG_BITS { // bit description
Uint16 XCERG0:1; // 0 Receive Channel enable bit
Uint16 XCERG1:1; // 1 Receive Channel enable bit
Uint16 XCERG2:1; // 2 Receive Channel enable bit
Uint16 XCERG3:1; // 3 Receive Channel enable bit
Uint16 XCERG4:1; // 4 Receive Channel enable bit
Uint16 XCERG5:1; // 5 Receive Channel enable bit
Uint16 XCERG6:1; // 6 Receive Channel enable bit
Uint16 XCERG7:1; // 7 Receive Channel enable bit
Uint16 XCERG8:1; // 8 Receive Channel enable bit
Uint16 XCERG9:1; // 9 Receive Channel enable bit
Uint16 XCERG10:1; // 10 Receive Channel enable bit
Uint16 XCERG11:1; // 11 Receive Channel enable bit
Uint16 XCERG12:1; // 12 Receive Channel enable bit
Uint16 XCERG13:1; // 13 Receive Channel enable bit
Uint16 XCERG14:1; // 14 Receive Channel enable bit
Uint16 XCERG15:1; // 15 Receive Channel enable bit
};
union XCERG_REG {
Uint16 all;
struct XCERG_BITS bit;
};
//
// XCERH control register bit definitions
//
struct XCERH_BITS { // bit description
Uint16 XCEH0:1; // 0 Receive Channel enable bit
Uint16 XCEH1:1; // 1 Receive Channel enable bit
Uint16 XCEH2:1; // 2 Receive Channel enable bit
Uint16 XCEH3:1; // 3 Receive Channel enable bit
Uint16 XCEH4:1; // 4 Receive Channel enable bit
Uint16 XCEH5:1; // 5 Receive Channel enable bit
Uint16 XCEH6:1; // 6 Receive Channel enable bit
Uint16 XCEH7:1; // 7 Receive Channel enable bit
Uint16 XCEH8:1; // 8 Receive Channel enable bit
Uint16 XCEH9:1; // 9 Receive Channel enable bit
Uint16 XCEH10:1; // 10 Receive Channel enable bit
Uint16 XCEH11:1; // 11 Receive Channel enable bit
Uint16 XCEH12:1; // 12 Receive Channel enable bit
Uint16 XCEH13:1; // 13 Receive Channel enable bit
Uint16 XCEH14:1; // 14 Receive Channel enable bit
Uint16 XCEH15:1; // 15 Receive Channel enable bit
};
union XCERH_REG {
Uint16 all;
struct XCERH_BITS bit;
};
//
// McBSP Interrupt enable register for RINT/XINT
//
struct MFFINT_BITS { // bits description
Uint16 XINT:1; // 0 XINT interrupt enable
Uint16 rsvd1:1; // 1 reserved
Uint16 RINT:1; // 2 RINT interrupt enable
Uint16 rsvd2:13; // 15:3 reserved
};
union MFFINT_REG {
Uint16 all;
struct MFFINT_BITS bit;
};
//
// McBSP Register File
//
struct MCBSP_REGS {
union DRR2_REG DRR2; // MCBSP Data receive register bits 31-16
union DRR1_REG DRR1; // MCBSP Data receive register bits 15-0
union DXR2_REG DXR2; // MCBSP Data transmit register bits 31-16
union DXR1_REG DXR1; // MCBSP Data transmit register bits 15-0
union SPCR2_REG SPCR2; // MCBSP control register bits 31-16
union SPCR1_REG SPCR1; // MCBSP control register bits 15-0
union RCR2_REG RCR2; // MCBSP receive control register bits 31-16
union RCR1_REG RCR1; // MCBSP receive control register bits 15-0
union XCR2_REG XCR2; // MCBSP transmit control register bits 31-16
union XCR1_REG XCR1; // MCBSP transmit control register bits 15-0
union SRGR2_REG SRGR2; // MCBSP sample rate gen register bits 31-16
union SRGR1_REG SRGR1; // MCBSP sample rate gen register bits 15-0
union MCR2_REG MCR2; // MCBSP multichannel register bits 31-16
union MCR1_REG MCR1; // MCBSP multichannel register bits 15-0
union RCERA_REG RCERA; // MCBSP Receive channel enable partition A
union RCERB_REG RCERB; // MCBSP Receive channel enable partition B
union XCERA_REG XCERA; // MCBSP Transmit channel enable partition A
union XCERB_REG XCERB; // MCBSP Transmit channel enable partition B
union PCR_REG PCR; // MCBSP Pin control register bits 15-0
union RCERC_REG RCERC; // MCBSP Receive channel enable partition C
union RCERD_REG RCERD; // MCBSP Receive channel enable partition D
union XCERC_REG XCERC; // MCBSP Transmit channel enable partition C
union XCERD_REG XCERD; // MCBSP Transmit channel enable partition D
union RCERE_REG RCERE; // MCBSP Receive channel enable partition E
union RCERF_REG RCERF; // MCBSP Receive channel enable partition F
union XCERE_REG XCERE; // MCBSP Transmit channel enable partition E
union XCERF_REG XCERF; // MCBSP Transmit channel enable partition F
union RCERG_REG RCERG; // MCBSP Receive channel enable partition G
union RCERH_REG RCERH; // MCBSP Receive channel enable partition H
union XCERG_REG XCERG; // MCBSP Transmit channel enable partition G
union XCERH_REG XCERH; // MCBSP Transmit channel enable partition H
Uint16 rsvd1[4]; // reserved
union MFFINT_REG MFFINT; // MCBSP Interrupt enable register for
// RINT/XINT
Uint16 rsvd2; // reserved
};
//
// McBSP External References & Function Declarations
//
extern volatile struct MCBSP_REGS McbspaRegs;
extern volatile struct MCBSP_REGS McbspbRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_MCBSP_H definition
//
// No more
//

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F28335/DSP2833x_PieCtrl.h
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//###########################################################################
//
// FILE: DSP2833x_PieCtrl.h
//
// TITLE: DSP2833x Device PIE Control Register Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_PIE_CTRL_H
#define DSP2833x_PIE_CTRL_H
#ifdef __cplusplus
extern "C" {
#endif
//
// PIE Control Register Bit Definitions
//
//
// PIECTRL: Register bit definitions
//
struct PIECTRL_BITS { // bits description
Uint16 ENPIE:1; // 0 Enable PIE block
Uint16 PIEVECT:15; // 15:1 Fetched vector address
};
union PIECTRL_REG {
Uint16 all;
struct PIECTRL_BITS bit;
};
//
// PIEIER: Register bit definitions
//
struct PIEIER_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIER_REG {
Uint16 all;
struct PIEIER_BITS bit;
};
//
// PIEIFR: Register bit definitions
//
struct PIEIFR_BITS { // bits description
Uint16 INTx1:1; // 0 INTx.1
Uint16 INTx2:1; // 1 INTx.2
Uint16 INTx3:1; // 2 INTx.3
Uint16 INTx4:1; // 3 INTx.4
Uint16 INTx5:1; // 4 INTx.5
Uint16 INTx6:1; // 5 INTx.6
Uint16 INTx7:1; // 6 INTx.7
Uint16 INTx8:1; // 7 INTx.8
Uint16 rsvd:8; // 15:8 reserved
};
union PIEIFR_REG {
Uint16 all;
struct PIEIFR_BITS bit;
};
//
// PIEACK: Register bit definitions
//
struct PIEACK_BITS { // bits description
Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1
Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2
Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3
Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4
Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5
Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6
Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7
Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8
Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9
Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10
Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11
Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12
Uint16 rsvd:4; // 15:12 reserved
};
union PIEACK_REG {
Uint16 all;
struct PIEACK_BITS bit;
};
//
// PIE Control Register File
//
struct PIE_CTRL_REGS {
union PIECTRL_REG PIECTRL; // PIE control register
union PIEACK_REG PIEACK; // PIE acknowledge
union PIEIER_REG PIEIER1; // PIE int1 IER register
union PIEIFR_REG PIEIFR1; // PIE int1 IFR register
union PIEIER_REG PIEIER2; // PIE INT2 IER register
union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register
union PIEIER_REG PIEIER3; // PIE INT3 IER register
union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register
union PIEIER_REG PIEIER4; // PIE INT4 IER register
union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register
union PIEIER_REG PIEIER5; // PIE INT5 IER register
union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register
union PIEIER_REG PIEIER6; // PIE INT6 IER register
union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register
union PIEIER_REG PIEIER7; // PIE INT7 IER register
union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register
union PIEIER_REG PIEIER8; // PIE INT8 IER register
union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register
union PIEIER_REG PIEIER9; // PIE INT9 IER register
union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register
union PIEIER_REG PIEIER10; // PIE int10 IER register
union PIEIFR_REG PIEIFR10; // PIE int10 IFR register
union PIEIER_REG PIEIER11; // PIE int11 IER register
union PIEIFR_REG PIEIFR11; // PIE int11 IFR register
union PIEIER_REG PIEIER12; // PIE int12 IER register
union PIEIFR_REG PIEIFR12; // PIE int12 IFR register
};
//
// Defines
//
#define PIEACK_GROUP1 0x0001
#define PIEACK_GROUP2 0x0002
#define PIEACK_GROUP3 0x0004
#define PIEACK_GROUP4 0x0008
#define PIEACK_GROUP5 0x0010
#define PIEACK_GROUP6 0x0020
#define PIEACK_GROUP7 0x0040
#define PIEACK_GROUP8 0x0080
#define PIEACK_GROUP9 0x0100
#define PIEACK_GROUP10 0x0200
#define PIEACK_GROUP11 0x0400
#define PIEACK_GROUP12 0x0800
//
// PIE Control Registers External References & Function Declarations
//
extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_PIE_CTRL_H definition
//
// End of file
//

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F28335/DSP2833x_PieVect.h
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//###########################################################################
//
// FILE: DSP2833x_PieVect.h
//
// TITLE: DSP2833x Devices PIE Vector Table Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_PIE_VECT_H
#define DSP2833x_PIE_VECT_H
#ifdef __cplusplus
extern "C" {
#endif
//
// PIE Interrupt Vector Table Definition
//
//
// Typedef used to create a user type called PINT (pointer to interrupt)
//
typedef interrupt void(*PINT)(void);
//
// Vector Table Define
//
struct PIE_VECT_TABLE {
//
// Reset is never fetched from this table. It will always be fetched from
// 0x3FFFC0 in boot ROM
//
PINT PIE1_RESERVED;
PINT PIE2_RESERVED;
PINT PIE3_RESERVED;
PINT PIE4_RESERVED;
PINT PIE5_RESERVED;
PINT PIE6_RESERVED;
PINT PIE7_RESERVED;
PINT PIE8_RESERVED;
PINT PIE9_RESERVED;
PINT PIE10_RESERVED;
PINT PIE11_RESERVED;
PINT PIE12_RESERVED;
PINT PIE13_RESERVED;
//
// Non-Peripheral Interrupts
//
PINT XINT13; // XINT13 / CPU-Timer1
PINT TINT2; // CPU-Timer2
PINT DATALOG; // Datalogging interrupt
PINT RTOSINT; // RTOS interrupt
PINT EMUINT; // Emulation interrupt
PINT XNMI; // Non-maskable interrupt
PINT ILLEGAL; // Illegal operation TRAP
PINT USER1; // User Defined trap 1
PINT USER2; // User Defined trap 2
PINT USER3; // User Defined trap 3
PINT USER4; // User Defined trap 4
PINT USER5; // User Defined trap 5
PINT USER6; // User Defined trap 6
PINT USER7; // User Defined trap 7
PINT USER8; // User Defined trap 8
PINT USER9; // User Defined trap 9
PINT USER10; // User Defined trap 10
PINT USER11; // User Defined trap 11
PINT USER12; // User Defined trap 12
//
// Group 1 PIE Peripheral Vectors
//
PINT SEQ1INT;
PINT SEQ2INT;
PINT rsvd1_3;
PINT XINT1;
PINT XINT2;
PINT ADCINT; // ADC
PINT TINT0; // Timer 0
PINT WAKEINT; // WD
//
// Group 2 PIE Peripheral Vectors
//
PINT EPWM1_TZINT; // EPWM-1
PINT EPWM2_TZINT; // EPWM-2
PINT EPWM3_TZINT; // EPWM-3
PINT EPWM4_TZINT; // EPWM-4
PINT EPWM5_TZINT; // EPWM-5
PINT EPWM6_TZINT; // EPWM-6
PINT rsvd2_7;
PINT rsvd2_8;
//
// Group 3 PIE Peripheral Vectors
//
PINT EPWM1_INT; // EPWM-1
PINT EPWM2_INT; // EPWM-2
PINT EPWM3_INT; // EPWM-3
PINT EPWM4_INT; // EPWM-4
PINT EPWM5_INT; // EPWM-5
PINT EPWM6_INT; // EPWM-6
PINT rsvd3_7;
PINT rsvd3_8;
//
// Group 4 PIE Peripheral Vectors
//
PINT ECAP1_INT; // ECAP-1
PINT ECAP2_INT; // ECAP-2
PINT ECAP3_INT; // ECAP-3
PINT ECAP4_INT; // ECAP-4
PINT ECAP5_INT; // ECAP-5
PINT ECAP6_INT; // ECAP-6
PINT rsvd4_7;
PINT rsvd4_8;
//
// Group 5 PIE Peripheral Vectors
//
PINT EQEP1_INT; // EQEP-1
PINT EQEP2_INT; // EQEP-2
PINT rsvd5_3;
PINT rsvd5_4;
PINT rsvd5_5;
PINT rsvd5_6;
PINT rsvd5_7;
PINT rsvd5_8;
//
// Group 6 PIE Peripheral Vectors
//
PINT SPIRXINTA; // SPI-A
PINT SPITXINTA; // SPI-A
PINT MRINTB; // McBSP-B
PINT MXINTB; // McBSP-B
PINT MRINTA; // McBSP-A
PINT MXINTA; // McBSP-A
PINT rsvd6_7;
PINT rsvd6_8;
//
// Group 7 PIE Peripheral Vectors
//
PINT DINTCH1; // DMA
PINT DINTCH2; // DMA
PINT DINTCH3; // DMA
PINT DINTCH4; // DMA
PINT DINTCH5; // DMA
PINT DINTCH6; // DMA
PINT rsvd7_7;
PINT rsvd7_8;
//
// Group 8 PIE Peripheral Vectors
//
PINT I2CINT1A; // I2C-A
PINT I2CINT2A; // I2C-A
PINT rsvd8_3;
PINT rsvd8_4;
PINT SCIRXINTC; // SCI-C
PINT SCITXINTC; // SCI-C
PINT rsvd8_7;
PINT rsvd8_8;
//
// Group 9 PIE Peripheral Vectors
//
PINT SCIRXINTA; // SCI-A
PINT SCITXINTA; // SCI-A
PINT SCIRXINTB; // SCI-B
PINT SCITXINTB; // SCI-B
PINT ECAN0INTA; // eCAN-A
PINT ECAN1INTA; // eCAN-A
PINT ECAN0INTB; // eCAN-B
PINT ECAN1INTB; // eCAN-B
//
// Group 10 PIE Peripheral Vectors
//
PINT rsvd10_1;
PINT rsvd10_2;
PINT rsvd10_3;
PINT rsvd10_4;
PINT rsvd10_5;
PINT rsvd10_6;
PINT rsvd10_7;
PINT rsvd10_8;
//
// Group 11 PIE Peripheral Vectors
//
PINT rsvd11_1;
PINT rsvd11_2;
PINT rsvd11_3;
PINT rsvd11_4;
PINT rsvd11_5;
PINT rsvd11_6;
PINT rsvd11_7;
PINT rsvd11_8;
//
// Group 12 PIE Peripheral Vectors
//
PINT XINT3; // External interrupt
PINT XINT4;
PINT XINT5;
PINT XINT6;
PINT XINT7;
PINT rsvd12_6;
PINT LVF; // Latched overflow
PINT LUF; // Latched underflow
};
//
// PIE Interrupt Vector Table External References & Function Declarations
//
extern volatile struct PIE_VECT_TABLE PieVectTable;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_PIE_VECT_H definition
//
// End of file
//

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//###########################################################################
//
// FILE: DSP2833x_Sci.h
//
// TITLE: DSP2833x Device SCI Register Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_SCI_H
#define DSP2833x_SCI_H
#ifdef __cplusplus
extern "C" {
#endif
//
// SCI Individual Register Bit Definitions
//
//
// SCICCR communication control register bit definitions
//
struct SCICCR_BITS { // bit description
Uint16 SCICHAR:3; // 2:0 Character length control
Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control
Uint16 LOOPBKENA:1; // 4 Loop Back enable
Uint16 PARITYENA:1; // 5 Parity enable
Uint16 PARITY:1; // 6 Even or Odd Parity
Uint16 STOPBITS:1; // 7 Number of Stop Bits
Uint16 rsvd1:8; // 15:8 reserved
};
union SCICCR_REG {
Uint16 all;
struct SCICCR_BITS bit;
};
//
// SCICTL1 control register 1 bit definitions
//
struct SCICTL1_BITS { // bit description
Uint16 RXENA:1; // 0 SCI receiver enable
Uint16 TXENA:1; // 1 SCI transmitter enable
Uint16 SLEEP:1; // 2 SCI sleep
Uint16 TXWAKE:1; // 3 Transmitter wakeup method
Uint16 rsvd:1; // 4 reserved
Uint16 SWRESET:1; // 5 Software reset
Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable
Uint16 rsvd1:9; // 15:7 reserved
};
union SCICTL1_REG {
Uint16 all;
struct SCICTL1_BITS bit;
};
//
// SCICTL2 control register 2 bit definitions
//
struct SCICTL2_BITS { // bit description
Uint16 TXINTENA:1; // 0 Transmit interrupt enable
Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable
Uint16 rsvd:4; // 5:2 reserved
Uint16 TXEMPTY:1; // 6 Transmitter empty flag
Uint16 TXRDY:1; // 7 Transmitter ready flag
Uint16 rsvd1:8; // 15:8 reserved
};
union SCICTL2_REG {
Uint16 all;
struct SCICTL2_BITS bit;
};
//
// SCIRXST Receiver status register bit definitions
//
struct SCIRXST_BITS { // bit description
Uint16 rsvd:1; // 0 reserved
Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag
Uint16 PE:1; // 2 Parity error flag
Uint16 OE:1; // 3 Overrun error flag
Uint16 FE:1; // 4 Framing error flag
Uint16 BRKDT:1; // 5 Break-detect flag
Uint16 RXRDY:1; // 6 Receiver ready flag
Uint16 RXERROR:1; // 7 Receiver error flag
};
union SCIRXST_REG {
Uint16 all;
struct SCIRXST_BITS bit;
};
//
// SCIRXBUF Receiver Data Buffer with FIFO bit definitions
//
struct SCIRXBUF_BITS { // bits description
Uint16 RXDT:8; // 7:0 Receive word
Uint16 rsvd:6; // 13:8 reserved
Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode
Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode
};
union SCIRXBUF_REG {
Uint16 all;
struct SCIRXBUF_BITS bit;
};
//
// SCIPRI Priority control register bit definitions
//
struct SCIPRI_BITS { // bit description
Uint16 rsvd:3; // 2:0 reserved
Uint16 FREE:1; // 3 Free emulation suspend mode
Uint16 SOFT:1; // 4 Soft emulation suspend mode
Uint16 rsvd1:3; // 7:5 reserved
};
union SCIPRI_REG {
Uint16 all;
struct SCIPRI_BITS bit;
};
//
// SCI FIFO Transmit register bit definitions
//
struct SCIFFTX_BITS { // bit description
Uint16 TXFFIL:5; // 4:0 Interrupt level
Uint16 TXFFIENA:1; // 5 Interrupt enable
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
Uint16 TXFFINT:1; // 7 INT flag
Uint16 TXFFST:5; // 12:8 FIFO status
Uint16 TXFIFOXRESET:1; // 13 FIFO reset
Uint16 SCIFFENA:1; // 14 Enhancement enable
Uint16 SCIRST:1; // 15 SCI reset rx/tx channels
};
union SCIFFTX_REG {
Uint16 all;
struct SCIFFTX_BITS bit;
};
//
// SCI FIFO recieve register bit definitions
//
struct SCIFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 Interrupt level
Uint16 RXFFIENA:1; // 5 Interrupt enable
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
Uint16 RXFFINT:1; // 7 INT flag
Uint16 RXFFST:5; // 12:8 FIFO status
Uint16 RXFIFORESET:1; // 13 FIFO reset
Uint16 RXFFOVRCLR:1; // 14 Clear overflow
Uint16 RXFFOVF:1; // 15 FIFO overflow
};
union SCIFFRX_REG {
Uint16 all;
struct SCIFFRX_BITS bit;
};
//
// SCI FIFO control register bit definitions
//
struct SCIFFCT_BITS { // bits description
Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay
Uint16 rsvd:5; // 12:8 reserved
Uint16 CDC:1; // 13 Auto baud mode enable
Uint16 ABDCLR:1; // 14 Auto baud clear
Uint16 ABD:1; // 15 Auto baud detect
};
union SCIFFCT_REG {
Uint16 all;
struct SCIFFCT_BITS bit;
};
//
// SCI Register File
//
struct SCI_REGS {
union SCICCR_REG SCICCR; // Communications control register
union SCICTL1_REG SCICTL1; // Control register 1
Uint16 SCIHBAUD; // Baud rate (high) register
Uint16 SCILBAUD; // Baud rate (low) register
union SCICTL2_REG SCICTL2; // Control register 2
union SCIRXST_REG SCIRXST; // Recieve status register
Uint16 SCIRXEMU; // Recieve emulation buffer register
union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer
Uint16 rsvd1; // reserved
Uint16 SCITXBUF; // Transmit data buffer
union SCIFFTX_REG SCIFFTX; // FIFO transmit register
union SCIFFRX_REG SCIFFRX; // FIFO recieve register
union SCIFFCT_REG SCIFFCT; // FIFO control register
Uint16 rsvd2; // reserved
Uint16 rsvd3; // reserved
union SCIPRI_REG SCIPRI; // FIFO Priority control
};
//
// SCI External References & Function Declarations
//
extern volatile struct SCI_REGS SciaRegs;
extern volatile struct SCI_REGS ScibRegs;
extern volatile struct SCI_REGS ScicRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SCI_H definition
//
// End of file
//

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//###########################################################################
//
// FILE: DSP2833x_Spi.h
//
// TITLE: DSP2833x Device SPI Register Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_SPI_H
#define DSP2833x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
//
// SPI Individual Register Bit Definitions
//
//
// SPI FIFO Transmit register bit definitions
//
struct SPIFFTX_BITS { // bit description
Uint16 TXFFIL:5; // 4:0 Interrupt level
Uint16 TXFFIENA:1; // 5 Interrupt enable
Uint16 TXFFINTCLR:1; // 6 Clear INT flag
Uint16 TXFFINT:1; // 7 INT flag
Uint16 TXFFST:5; // 12:8 FIFO status
Uint16 TXFIFO:1; // 13 FIFO reset
Uint16 SPIFFENA:1; // 14 Enhancement enable
Uint16 SPIRST:1; // 15 Reset SPI
};
union SPIFFTX_REG {
Uint16 all;
struct SPIFFTX_BITS bit;
};
//
// SPI FIFO recieve register bit definitions
//
struct SPIFFRX_BITS { // bits description
Uint16 RXFFIL:5; // 4:0 Interrupt level
Uint16 RXFFIENA:1; // 5 Interrupt enable
Uint16 RXFFINTCLR:1; // 6 Clear INT flag
Uint16 RXFFINT:1; // 7 INT flag
Uint16 RXFFST:5; // 12:8 FIFO status
Uint16 RXFIFORESET:1; // 13 FIFO reset
Uint16 RXFFOVFCLR:1; // 14 Clear overflow
Uint16 RXFFOVF:1; // 15 FIFO overflow
};
union SPIFFRX_REG {
Uint16 all;
struct SPIFFRX_BITS bit;
};
//
// SPI FIFO control register bit definitions
//
struct SPIFFCT_BITS { // bits description
Uint16 TXDLY:8; // 7:0 FIFO transmit delay
Uint16 rsvd:8; // 15:8 reserved
};
union SPIFFCT_REG {
Uint16 all;
struct SPIFFCT_BITS bit;
};
//
// SPI configuration register bit definitions
//
struct SPICCR_BITS { // bits description
Uint16 SPICHAR:4; // 3:0 Character length control
Uint16 SPILBK:1; // 4 Loop-back enable/disable
Uint16 rsvd1:1; // 5 reserved
Uint16 CLKPOLARITY:1; // 6 Clock polarity
Uint16 SPISWRESET:1; // 7 SPI SW Reset
Uint16 rsvd2:8; // 15:8 reserved
};
union SPICCR_REG {
Uint16 all;
struct SPICCR_BITS bit;
};
//
// SPI operation control register bit definitions
//
struct SPICTL_BITS { // bits description
Uint16 SPIINTENA:1; // 0 Interrupt enable
Uint16 TALK:1; // 1 Master/Slave transmit enable
Uint16 MASTER_SLAVE:1; // 2 Network control mode
Uint16 CLK_PHASE:1; // 3 Clock phase select
Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable
Uint16 rsvd:11; // 15:5 reserved
};
union SPICTL_REG {
Uint16 all;
struct SPICTL_BITS bit;
};
//
// SPI status register bit definitions
//
struct SPISTS_BITS { // bits description
Uint16 rsvd1:5; // 4:0 reserved
Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag
Uint16 INT_FLAG:1; // 6 SPI interrupt flag
Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag
Uint16 rsvd2:8; // 15:8 reserved
};
union SPISTS_REG {
Uint16 all;
struct SPISTS_BITS bit;
};
//
// SPI priority control register bit definitions
//
struct SPIPRI_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 FREE:1; // 4 Free emulation mode control
Uint16 SOFT:1; // 5 Soft emulation mode control
Uint16 rsvd2:1; // 6 reserved
Uint16 rsvd3:9; // 15:7 reserved
};
union SPIPRI_REG {
Uint16 all;
struct SPIPRI_BITS bit;
};
//
// SPI Register File
//
struct SPI_REGS {
union SPICCR_REG SPICCR; // Configuration register
union SPICTL_REG SPICTL; // Operation control register
union SPISTS_REG SPISTS; // Status register
Uint16 rsvd1; // reserved
Uint16 SPIBRR; // Baud Rate
Uint16 rsvd2; // reserved
Uint16 SPIRXEMU; // Emulation buffer
Uint16 SPIRXBUF; // Serial input buffer
Uint16 SPITXBUF; // Serial output buffer
Uint16 SPIDAT; // Serial data
union SPIFFTX_REG SPIFFTX; // FIFO transmit register
union SPIFFRX_REG SPIFFRX; // FIFO recieve register
union SPIFFCT_REG SPIFFCT; // FIFO control register
Uint16 rsvd3[2]; // reserved
union SPIPRI_REG SPIPRI; // FIFO Priority control
};
//
// SPI External References & Function Declarations
//
extern volatile struct SPI_REGS SpiaRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SPI_H definition
//
// End of file
//

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//###########################################################################
//
// FILE: DSP2833x_SysCtrl.h
//
// TITLE: DSP2833x Device System Control Register Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_SYS_CTRL_H
#define DSP2833x_SYS_CTRL_H
#ifdef __cplusplus
extern "C" {
#endif
//
// System Control Individual Register Bit Definitions
//
//
// PLL Status Register
//
struct PLLSTS_BITS { // bits description
Uint16 PLLLOCKS:1; // 0 PLL lock status
Uint16 rsvd1:1; // 1 reserved
Uint16 PLLOFF:1; // 2 PLL off bit
Uint16 MCLKSTS:1; // 3 Missing clock status bit
Uint16 MCLKCLR:1; // 4 Missing clock clear bit
Uint16 OSCOFF:1; // 5 Oscillator clock off
Uint16 MCLKOFF:1; // 6 Missing clock detect
Uint16 DIVSEL:2; // 7 Divide Select
Uint16 rsvd2:7; // 15:7 reserved
};
union PLLSTS_REG {
Uint16 all;
struct PLLSTS_BITS bit;
};
//
// High speed peripheral clock register bit definitions
//
struct HISPCP_BITS { // bits description
Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union HISPCP_REG {
Uint16 all;
struct HISPCP_BITS bit;
};
//
// Low speed peripheral clock register bit definitions
//
struct LOSPCP_BITS { // bits description
Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT
Uint16 rsvd1:13; // 15:3 reserved
};
union LOSPCP_REG {
Uint16 all;
struct LOSPCP_BITS bit;
};
//
// Peripheral clock control register 0 bit definitions
//
struct PCLKCR0_BITS { // bits description
Uint16 rsvd1:2; // 1:0 reserved
Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync
Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC
Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A
Uint16 SCICENCLK:1; // 5 Enalbe low speed clk to SCI-C
Uint16 rsvd2:2; // 7:6 reserved
Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A
Uint16 rsvd3:1; // 9 reserved
Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A
Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B
Uint16 MCBSPAENCLK:1; // 12 Enable low speed clk to McBSP-A
Uint16 MCBSPBENCLK:1; // 13 Enable low speed clk to McBSP-B
Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A
Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B
};
union PCLKCR0_REG {
Uint16 all;
struct PCLKCR0_BITS bit;
};
//
// Peripheral clock control register 1 bit definitions
//
struct PCLKCR1_BITS { // bits description
Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1
Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2
Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3
Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4
Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5
Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6
Uint16 rsvd1:2; // 7:6 reserved
Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1
Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2
Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3
Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4
Uint16 ECAP5ENCLK:1; // 12 Enable SYSCLKOUT to ECAP5
Uint16 ECAP6ENCLK:1; // 13 Enable SYSCLKOUT to ECAP6
Uint16 EQEP1ENCLK:1; // 14 Enable SYSCLKOUT to EQEP1
Uint16 EQEP2ENCLK:1; // 15 Enable SYSCLKOUT to EQEP2
};
union PCLKCR1_REG {
Uint16 all;
struct PCLKCR1_BITS bit;
};
//
// Peripheral clock control register 2 bit definitions
//
struct PCLKCR3_BITS { // bits description
Uint16 rsvd1:8; // 7:0 reserved
Uint16 CPUTIMER0ENCLK:1; // 8 Enable SYSCLKOUT to CPU-Timer 0
Uint16 CPUTIMER1ENCLK:1; // 9 Enable SYSCLKOUT to CPU-Timer 1
Uint16 CPUTIMER2ENCLK:1; // 10 Enable SYSCLKOUT to CPU-Timer 2
Uint16 DMAENCLK:1; // 11 Enable the DMA clock
Uint16 XINTFENCLK:1; // 12 Enable SYSCLKOUT to XINTF
Uint16 GPIOINENCLK:1; // Enable GPIO input clock
Uint16 rsvd2:2; // 15:14 reserved
};
union PCLKCR3_REG {
Uint16 all;
struct PCLKCR3_BITS bit;
};
//
// PLL control register bit definitions
//
struct PLLCR_BITS { // bits description
Uint16 DIV:4; // 3:0 Set clock ratio for the PLL
Uint16 rsvd1:12; // 15:4 reserved
};
union PLLCR_REG {
Uint16 all;
struct PLLCR_BITS bit;
};
//
// Low Power Mode 0 control register bit definitions
//
struct LPMCR0_BITS { // bits description
Uint16 LPM:2; // 1:0 Set the low power mode
Uint16 QUALSTDBY:6; // 7:2 Qualification
Uint16 rsvd1:7; // 14:8 reserved
Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY
};
union LPMCR0_REG {
Uint16 all;
struct LPMCR0_BITS bit;
};
//
// Dual-mapping configuration register bit definitions
//
struct MAPCNF_BITS { // bits description
Uint16 MAPEPWM:1; // 0 EPWM dual-map enable
Uint16 rsvd1:15; // 15:1 reserved
};
union MAPCNF_REG {
Uint16 all;
struct MAPCNF_BITS bit;
};
//
// System Control Register File
//
struct SYS_CTRL_REGS {
Uint16 rsvd1; // 0
union PLLSTS_REG PLLSTS; // 1
Uint16 rsvd2[8]; // 2-9
//
// 10: High-speed peripheral clock pre-scaler
//
union HISPCP_REG HISPCP;
union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler
union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register
union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register
union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0
Uint16 rsvd3; // 15: reserved
union PCLKCR3_REG PCLKCR3; // 16: Peripheral clock control register
union PLLCR_REG PLLCR; // 17: PLL control register
//
// No bit definitions are defined for SCSR because
// a read-modify-write instruction can clear the WDOVERRIDE bit
//
Uint16 SCSR; // 18: System control and status register
Uint16 WDCNTR; // 19: WD counter register
Uint16 rsvd4; // 20
Uint16 WDKEY; // 21: WD reset key register
Uint16 rsvd5[3]; // 22-24
//
// No bit definitions are defined for WDCR because
// the proper value must be written to the WDCHK field
// whenever writing to this register.
//
Uint16 WDCR; // 25: WD timer control register
Uint16 rsvd6[4]; // 26-29
union MAPCNF_REG MAPCNF; // 30: Dual-mapping configuration register
Uint16 rsvd7[1]; // 31
};
//
// CSM Registers
//
//
// CSM Status & Control register bit definitions
//
struct CSMSCR_BITS { // bit description
Uint16 SECURE:1; // 0 Secure flag
Uint16 rsvd1:14; // 14-1 reserved
Uint16 FORCESEC:1; // 15 Force Secure control bit
};
//
// Allow access to the bit fields or entire register
//
union CSMSCR_REG {
Uint16 all;
struct CSMSCR_BITS bit;
};
//
// CSM Register File
//
struct CSM_REGS {
Uint16 KEY0; // KEY reg bits 15-0
Uint16 KEY1; // KEY reg bits 31-16
Uint16 KEY2; // KEY reg bits 47-32
Uint16 KEY3; // KEY reg bits 63-48
Uint16 KEY4; // KEY reg bits 79-64
Uint16 KEY5; // KEY reg bits 95-80
Uint16 KEY6; // KEY reg bits 111-96
Uint16 KEY7; // KEY reg bits 127-112
Uint16 rsvd1; // reserved
Uint16 rsvd2; // reserved
Uint16 rsvd3; // reserved
Uint16 rsvd4; // reserved
Uint16 rsvd5; // reserved
Uint16 rsvd6; // reserved
Uint16 rsvd7; // reserved
union CSMSCR_REG CSMSCR; // CSM Status & Control register
};
//
// Password locations
//
struct CSM_PWL {
Uint16 PSWD0; // PSWD bits 15-0
Uint16 PSWD1; // PSWD bits 31-16
Uint16 PSWD2; // PSWD bits 47-32
Uint16 PSWD3; // PSWD bits 63-48
Uint16 PSWD4; // PSWD bits 79-64
Uint16 PSWD5; // PSWD bits 95-80
Uint16 PSWD6; // PSWD bits 111-96
Uint16 PSWD7; // PSWD bits 127-112
};
//
// Defines for Flash Registers
//
#define FLASH_SLEEP 0x0000;
#define FLASH_STANDBY 0x0001;
#define FLASH_ACTIVE 0x0003;
//
// Flash Option Register bit definitions
//
struct FOPT_BITS { // bit description
Uint16 ENPIPE:1; // 0 Enable Pipeline Mode
Uint16 rsvd:15; // 1-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FOPT_REG {
Uint16 all;
struct FOPT_BITS bit;
};
//
// Flash Power Modes Register bit definitions
//
struct FPWR_BITS { // bit description
Uint16 PWR:2; // 0-1 Power Mode bits
Uint16 rsvd:14; // 2-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FPWR_REG {
Uint16 all;
struct FPWR_BITS bit;
};
//
// Flash Status Register bit definitions
//
struct FSTATUS_BITS { // bit description
Uint16 PWRS:2; // 0-1 Power Mode Status bits
Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits
Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits
Uint16 rsvd1:4; // 4-7 reserved
Uint16 V3STAT:1; // 8 VDD3V Status Latch bit
Uint16 rsvd2:7; // 9-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FSTATUS_REG {
Uint16 all;
struct FSTATUS_BITS bit;
};
//
// Flash Sleep to Standby Wait Counter Register bit definitions
//
struct FSTDBYWAIT_BITS { // bit description
//
// 0-8 Bank/Pump Sleep to Standby Wait Count bits
//
Uint16 STDBYWAIT:9;
Uint16 rsvd:7; // 9-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FSTDBYWAIT_REG {
Uint16 all;
struct FSTDBYWAIT_BITS bit;
};
//
// Flash Standby to Active Wait Counter Register bit definitions
//
struct FACTIVEWAIT_BITS { // bit description
//
// 0-8 Bank/Pump Standby to Active Wait Count bits
//
Uint16 ACTIVEWAIT:9;
Uint16 rsvd:7; // 9-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FACTIVEWAIT_REG {
Uint16 all;
struct FACTIVEWAIT_BITS bit;
};
//
// Bank Read Access Wait State Register bit definitions
//
struct FBANKWAIT_BITS { // bit description
Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits
Uint16 rsvd1:4; // 4-7 reserved
Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits
Uint16 rsvd2:4; // 12-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FBANKWAIT_REG {
Uint16 all;
struct FBANKWAIT_BITS bit;
};
//
// OTP Read Access Wait State Register bit definitions
//
struct FOTPWAIT_BITS { // bit description
Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits
Uint16 rsvd:11; // 5-15 reserved
};
//
// Allow access to the bit fields or entire register
//
union FOTPWAIT_REG {
Uint16 all;
struct FOTPWAIT_BITS bit;
};
struct FLASH_REGS {
union FOPT_REG FOPT; // Option Register
Uint16 rsvd1; // reserved
union FPWR_REG FPWR; // Power Modes Register
union FSTATUS_REG FSTATUS; // Status Register
//
// Pump/Bank Sleep to Standby Wait State Register
//
union FSTDBYWAIT_REG FSTDBYWAIT;
//
// Pump/Bank Standby to Active Wait State Register
//
union FACTIVEWAIT_REG FACTIVEWAIT;
union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register
union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register
};
//
// System Control External References & Function Declarations
//
extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
extern volatile struct CSM_REGS CsmRegs;
extern volatile struct CSM_PWL CsmPwl;
extern volatile struct FLASH_REGS FlashRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_SYS_CTRL_H definition
//
// End of file
//

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F28335/DSP2833x_XIntrupt.h
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//###########################################################################
//
// FILE: DSP2833x_XIntrupt.h
//
// TITLE: DSP2833x Device External Interrupt Register Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_XINTRUPT_H
#define DSP2833x_XINTRUPT_H
#ifdef __cplusplus
extern "C" {
#endif
struct XINTCR_BITS {
Uint16 ENABLE:1; // 0 enable/disable
Uint16 rsvd1:1; // 1 reserved
Uint16 POLARITY:2; // 3:2 pos/neg, both triggered
Uint16 rsvd2:12; //15:4 reserved
};
union XINTCR_REG {
Uint16 all;
struct XINTCR_BITS bit;
};
struct XNMICR_BITS {
Uint16 ENABLE:1; // 0 enable/disable
Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13
Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered
Uint16 rsvd2:12; // 15:4 reserved
};
union XNMICR_REG {
Uint16 all;
struct XNMICR_BITS bit;
};
//
// External Interrupt Register File
//
struct XINTRUPT_REGS {
union XINTCR_REG XINT1CR;
union XINTCR_REG XINT2CR;
union XINTCR_REG XINT3CR;
union XINTCR_REG XINT4CR;
union XINTCR_REG XINT5CR;
union XINTCR_REG XINT6CR;
union XINTCR_REG XINT7CR;
union XNMICR_REG XNMICR;
Uint16 XINT1CTR;
Uint16 XINT2CTR;
Uint16 rsvd[5];
Uint16 XNMICTR;
};
//
// External Interrupt References & Function Declarations
//
extern volatile struct XINTRUPT_REGS XIntruptRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_XINTF_H definition
//
// End of file
//

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F28335/DSP2833x_Xintf.h
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//###########################################################################
//
// FILE: DSP2833x_Xintf.h
//
// TITLE: DSP2833x Device External Interface Register Definitions.
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP2833x_XINTF_H
#define DSP2833x_XINTF_H
#ifdef __cplusplus
extern "C" {
#endif
//
// XINTF timing register bit definitions
//
struct XTIMING_BITS { // bits description
Uint16 XWRTRAIL:2; // 1:0 Write access trail timing
Uint16 XWRACTIVE:3; // 4:2 Write access active timing
Uint16 XWRLEAD:2; // 6:5 Write access lead timing
Uint16 XRDTRAIL:2; // 8:7 Read access trail timing
Uint16 XRDACTIVE:3; // 11:9 Read access active timing
Uint16 XRDLEAD:2; // 13:12 Read access lead timing
Uint16 USEREADY:1; // 14 Extend access using HW waitstates
Uint16 READYMODE:1; // 15 Ready mode
Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b
Uint16 rsvd1:4; // 21:18 reserved
Uint16 X2TIMING:1; // 22 Double lead/active/trail timing
Uint16 rsvd3:9; // 31:23 reserved
};
union XTIMING_REG {
Uint32 all;
struct XTIMING_BITS bit;
};
//
// XINTF control register bit definitions
//
struct XINTCNF2_BITS { // bits description
Uint16 WRBUFF:2; // 1:0 Write buffer depth
Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK
Uint16 CLKOFF:1; // 3 Disable XCLKOUT
Uint16 rsvd1:2; // 5:4 reserved
Uint16 WLEVEL:2; // 7:6 Current level of the write buffer
Uint16 rsvd2:1; // 8 reserved
Uint16 HOLD:1; // 9 Hold enable/disable
Uint16 HOLDS:1; // 10 Current state of HOLDn input
Uint16 HOLDAS:1; // 11 Current state of HOLDAn output
Uint16 rsvd3:4; // 15:12 reserved
Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK
Uint16 rsvd4:13; // 31:19 reserved
};
union XINTCNF2_REG {
Uint32 all;
struct XINTCNF2_BITS bit;
};
//
// XINTF bank switching register bit definitions
//
struct XBANK_BITS { // bits description
Uint16 BANK:3; // 2:0 Zone for which banking is enabled
Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add
Uint16 rsvd:10; // 15:6 reserved
};
union XBANK_REG {
Uint16 all;
struct XBANK_BITS bit;
};
struct XRESET_BITS {
Uint16 XHARDRESET:1;
Uint16 rsvd1:15;
};
union XRESET_REG {
Uint16 all;
struct XRESET_BITS bit;
};
//
// XINTF Register File
//
struct XINTF_REGS {
union XTIMING_REG XTIMING0;
Uint32 rsvd1[5];
union XTIMING_REG XTIMING6;
union XTIMING_REG XTIMING7;
Uint32 rsvd2[2];
union XINTCNF2_REG XINTCNF2;
Uint32 rsvd3;
union XBANK_REG XBANK;
Uint16 rsvd4;
Uint16 XREVISION;
Uint16 rsvd5[2];
union XRESET_REG XRESET;
};
//
// XINTF External References & Function Declarations
//
extern volatile struct XINTF_REGS XintfRegs;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // end of DSP2833x_XINTF_H definition
//
// End of File
//

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F28335/DSP28x_Project.h
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//###########################################################################
//
// FILE: DSP28x_Project.h
//
// TITLE: DSP28x Project Headerfile and Examples Include File
//
//###########################################################################
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: November 1, 2016 $
// $Copyright: Copyright (C) 2007-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
#ifndef DSP28x_PROJECT_H
#define DSP28x_PROJECT_H
#include "F28335/DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "F28335/DSP2833x_Examples.h" // DSP2833x Examples Include File
#endif // end of DSP28x_PROJECT_H definition

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F28335/Flash2833x_API_Config.h
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// TI File $Revision: /main/2 $
// Checkin $Date: June 22, 2007 13:11:24 $
//###########################################################################
//
// FILE: Flash2833x_API_Config.h
//
// TITLE: F2833x Flash Algo's - User Settings
//
// NOTE: This file contains user defined settings that
// are used by the F2833x Flash APIs.
//
//###########################################################################
// $TI Release:$
// $Release Date:$
//###########################################################################
#ifndef FLASH2833X_API_CONFIG_H
#define FLASH2833X_API_CONFIG_H
#ifdef __cplusplus
extern "C" {
#endif
// Variables that can be configured by the user.
/*-----------------------------------------------------------------------------
1. Specify the device.
Define the device to be programmed as "1" (no quotes).
Define all other devices as "0" (no quotes).
-----------------------------------------------------------------------------*/
#define FLASH_F28335 1
#define FLASH_F28334 0
#define FLASH_F28332 0
/*-----------------------------------------------------------------------------
2. Specify the clock rate of the CPU (SYSCLKOUT) in nS.
Take into account the input clock frequency and the PLL multiplier
that your application will use.
Use one of the values provided, or define your own.
The trailing L is required tells the compiler to treat
the number as a 64-bit value.
Only one statement should be uncommented.
Example: CLKIN is a 30MHz crystal.
If the application will set PLLCR = 0xA then the CPU clock
will be 150Mhz (SYSCLKOUT = 150MHz).
In this case, the CPU_RATE will be 6.667L
Uncomment the line: #define CPU_RATE 6.667L
-----------------------------------------------------------------------------*/
#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT)
//#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT)
//----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// **** DO NOT modify the code below this line ****
//-----------------------------------------------------------------------------
#define SCALE_FACTOR 1048576.0L*( (200L/CPU_RATE) ) // IQ20
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // -- end FLASH2833X_API_CONFIG_H

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F28335/Flash2833x_API_Library.h
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// TI File $Revision: /main/3 $
// Checkin $Date: February 5, 2008 11:10:02 $
//###########################################################################
//
// FILE: Flash2833x_API_Library.h
//
// TITLE: F2833x Flash Algo's main include file
//
// DESCRIPTION:
//
// This file should be included in any project that uses any of the
// the F2833x flash APIs.
//
//###########################################################################
// $TI Release:$
// $Release Date:$
//###########################################################################
#ifndef FLASH2833X_API_LIBRARY_H
#define FLASH2833X_API_LIBRARY_H
#include "F28335/Flash2833x_API_Config.h"
#ifdef __cplusplus
extern "C" {
#endif
/*---------------------------------------------------------------------------
28x Datatypes
For Portability, User Is Recommended To Use Following Data Type Size
Definitions For 16/32/64-Bit Signed/Unsigned Integers and floating point
variables:
---------------------------------------------------------------------------*/
#ifndef DSP28_DATA_TYPES
#define DSP28_DATA_TYPES
typedef int int16;
typedef long int32;
typedef long long int64;
typedef unsigned int Uint16;
typedef unsigned long Uint32;
typedef unsigned long long Uint64;
typedef float float32;
typedef long double float64;
#endif
/*---------------------------------------------------------------------------
API Status Messages
The following status values are returned from the API to the calling
program. These can be used to determine if the API function passed
or failed.
---------------------------------------------------------------------------*/
// Operation passed, no errors were flagged
#define STATUS_SUCCESS 0
// The CSM is preventing the function from performing its operation
#define STATUS_FAIL_CSM_LOCKED 10
// Device REVID does not match that required by the API
#define STATUS_FAIL_REVID_INVALID 11
// Invalid address passed to the API
#define STATUS_FAIL_ADDR_INVALID 12
// Incorrect PARTID
// For example the F2806 API was used on a F2808 device.
#define STATUS_FAIL_INCORRECT_PARTID 13
// API/Silicon missmatch. An old version of the
// API is being used on silicon it is not valid for
// Please update to the latest API.
#define STATUS_FAIL_API_SILICON_MISMATCH 14
// ---- Erase Specific errors ----
#define STATUS_FAIL_NO_SECTOR_SPECIFIED 20
#define STATUS_FAIL_PRECONDITION 21
#define STATUS_FAIL_ERASE 22
#define STATUS_FAIL_COMPACT 23
#define STATUS_FAIL_PRECOMPACT 24
// ---- Program Specific errors ----
#define STATUS_FAIL_PROGRAM 30
#define STATUS_FAIL_ZERO_BIT_ERROR 31
// ---- Verify Specific errors ----
#define STATUS_FAIL_VERIFY 40
// Busy is set by each API function before it determines
// a pass or fail condition for that operation.
// The calling function will will not receive this
// status condition back from the API
#define STATUS_BUSY 999
/*---------------------------------------------------------------------------
Flash sector mask definitions
The following macros can be used to form a mask specifying which sectors
will be erased by the erase API function.
Bit0 = Sector A
Bit1 = Sector B
Bit2 = Sector C
Bit3 = Sector D
Bit4 = Sector E
Bit5 = Sector F
Bit6 = Sector G
Bit7 = Sector H
---------------------------------------------------------------------------*/
#define SECTORA (Uint16)0x0001
#define SECTORB (Uint16)0x0002
#define SECTORC (Uint16)0x0004
#define SECTORD (Uint16)0x0008
#define SECTORE (Uint16)0x0010
#define SECTORF (Uint16)0x0020
#define SECTORG (Uint16)0x0040
#define SECTORH (Uint16)0x0080
#if FLASH_F28335
// All sectors on an F28335 - Sectors A - H
#define SECTOR_F28335 (SECTORA|SECTORB|SECTORC|\
SECTORD|SECTORE|SECTORF|\
SECTORG|SECTORH)
#endif // -- end FLASH_F28335
#if FLASH_F28334
// All sectors on an F28334 - Sectors A - H
#define SECTOR_F28334 (SECTORA|SECTORB|SECTORC|\
SECTORD|SECTORE|SECTORF|\
SECTORG|SECTORH)
#endif // -- end FLASH_F28334
#if FLASH_F28332
// All sectors on an F28332 - Sectors A - D
#define SECTOR_F28332 (SECTORA|SECTORB|SECTORC|\
SECTORD)
#endif // -- end FLASH_F28332
/*---------------------------------------------------------------------------
API Status Structure
This structure is used to pass debug data back to the calling routine.
Note that the Erase API function has 3 parts: precondition, erase and
and compaction. Erase and compaction failures will not populate
the expected and actual data fields.
---------------------------------------------------------------------------*/
typedef struct {
Uint32 FirstFailAddr;
Uint16 ExpectedData;
Uint16 ActualData;
}FLASH_ST;
/*---------------------------------------------------------------------------
Interface Function prototypes
For each 28x Flash API library, the function names are of the form:
Flash<DeviceNum>_<Operation>()
Where <DeviceNum> is the device: ie 2808, 2806, 2801
<Operation> is the operation such as Erase, Program...
For portability for users who may move between the F2808, F2806 and
F2801, the following macro definitions are supplied.
Using these macro definitions, the user can use instead make a generic
call: Flash_<Operation> and the macro will map the call to the proper
device function
Note except for the toggle test function, all of the function prototypes
are compatible with F281x devices as well.
---------------------------------------------------------------------------*/
#if FLASH_F28335
#define Flash_Erase(a,b) Flash28335_Erase(a,b)
#define Flash_Program(a,b,c,d) Flash28335_Program(a,b,c,d)
#define Flash_Verify(a,b,c,d) Flash28335_Verify(a,b,c,d)
#define Flash_ToggleTest(a,b) Flash28335_ToggleTest(a,b)
#define Flash_DepRecover() Flash28335_DepRecover()
#define Flash_APIVersionHex() Flash28335_APIVersionHex()
#define Flash_APIVersion() Flash28335_APIVersion()
#endif
#if FLASH_F28334
#define Flash_Erase(a,b) Flash28334_Erase(a,b)
#define Flash_Program(a,b,c,d) Flash28334_Program(a,b,c,d)
#define Flash_Verify(a,b,c,d) Flash28334_Verify(a,b,c,d)
#define Flash_ToggleTest(a,b) Flash28334_ToggleTest(a,b)
#define Flash_DepRecover() Flash28334_DepRecover()
#define Flash_APIVersionHex() Flash28334_APIVersionHex()
#define Flash_APIVersion() Flash28334_APIVersion()
#endif
#if FLASH_F28332
#define Flash_Erase(a,b) Flash28332_Erase(a,b)
#define Flash_Program(a,b,c,d) Flash28332_Program(a,b,c,d)
#define Flash_Verify(a,b,c,d) Flash28332_Verify(a,b,c,d)
#define Flash_ToggleTest(a,b) Flash28332_ToggleTest(a,b)
#define Flash_DepRecover() Flash28332_DepRecover()
#define Flash_APIVersionHex() Flash28332_APIVersionHex()
#define Flash_APIVersion() Flash28332_APIVersion()
#endif
extern Uint16 Flash_Erase(Uint16 SectorMask, FLASH_ST *FEraseStat);
extern Uint16 Flash_Program(Uint16 *FlashAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FProgStatus);
extern Uint16 Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FVerifyStat);
extern void Flash_ToggleTest(volatile Uint32 *ToggleReg, Uint32 Mask);
extern Uint16 Flash_DepRecover();
extern float32 Flash_APIVersion();
extern Uint16 Flash_APIVersionHex();
/*---------------------------------------------------------------------------
Frequency Scale factor:
The calling program must provide this global parameter used
for frequency scaling the algo's.
----------------------------------------------------------------------------*/
extern Uint32 Flash_CPUScaleFactor;
/*---------------------------------------------------------------------------
Callback Function Pointer:
A callback function can be specified. This function will be called
at safe times during erase, program and verify. This function can
then be used to service an external watchdog or send a communications
packet.
Note:
THE FLASH AND OTP ARE NOT AVAILABLE DURING THIS FUNCTION CALL.
THE FLASH/OTP CANNOT BE READ NOR CAN CODE EXECUTE FROM IT DURING THIS CALL
DO NOT CALL ANY OF THE THE FLASH API FUNCTIONS DURING THIS CALL
----------------------------------------------------------------------------*/
extern void (*Flash_CallbackPtr) (void);
/*---------------------------------------------------------------------------
API load/run symbols:
These symbols are defined by the linker during the link. Refer to the
Flash28_API section in the example .cmd file:
Flash28_API:
{
Flash28335_API_Library.lib(.econst)
Flash28335_API_Library.lib(.text)
} LOAD = FLASH,
RUN = SARAM,
LOAD_START(_Flash28_API_LoadStart),
LOAD_END(_Flash28_API_LoadEnd),
RUN_START(_Flash28_API_RunStart),
PAGE = 0
These are used to copy the flash API from flash to SARAM
----------------------------------------------------------------------------*/
extern Uint16 Flash28_API_LoadStart;
extern Uint16 Flash28_API_LoadEnd;
extern Uint16 Flash28_API_RunStart;
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif // -- end FLASH2833x_API_LIBRARY_H
// --------- END OF FILE ----------------------------------

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MODBUSRTU/ModbusRTUCRC.cpp
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/*
* ModbusRTUCRC.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "MODBUSRTU/ModbusRTUCRC.h"
namespace MODBUSRTU
{
const uint16_t ModbusRTUCRC::m_table[256] = {0x0000, 0xC1C0, 0x81C1, 0x4001, 0x01C3, 0xC003, 0x8002, 0x41C2,
0x01C6, 0xC006, 0x8007, 0x41C7, 0x0005, 0xC1C5, 0x81C4, 0x4004,
0x01CC, 0xC00C, 0x800D, 0x41CD, 0x000F, 0xC1CF, 0x81CE, 0x400E,
0x000A, 0xC1CA, 0x81CB, 0x400B, 0x01C9, 0xC009, 0x8008, 0x41C8,
0x01D8, 0xC018, 0x8019, 0x41D9, 0x001B, 0xC1DB, 0x81DA, 0x401A,
0x001E, 0xC1DE, 0x81DF, 0x401F, 0x01DD, 0xC01D, 0x801C, 0x41DC,
0x0014, 0xC1D4, 0x81D5, 0x4015, 0x01D7, 0xC017, 0x8016, 0x41D6,
0x01D2, 0xC012, 0x8013, 0x41D3, 0x0011, 0xC1D1, 0x81D0, 0x4010,
0x01F0, 0xC030, 0x8031, 0x41F1, 0x0033, 0xC1F3, 0x81F2, 0x4032,
0x0036, 0xC1F6, 0x81F7, 0x4037, 0x01F5, 0xC035, 0x8034, 0x41F4,
0x003C, 0xC1FC, 0x81FD, 0x403D, 0x01FF, 0xC03F, 0x803E, 0x41FE,
0x01FA, 0xC03A, 0x803B, 0x41FB, 0x0039, 0xC1F9, 0x81F8, 0x4038,
0x0028, 0xC1E8, 0x81E9, 0x4029, 0x01EB, 0xC02B, 0x802A, 0x41EA,
0x01EE, 0xC02E, 0x802F, 0x41EF, 0x002D, 0xC1ED, 0x81EC, 0x402C,
0x01E4, 0xC024, 0x8025, 0x41E5, 0x0027, 0xC1E7, 0x81E6, 0x4026,
0x0022, 0xC1E2, 0x81E3, 0x4023, 0x01E1, 0xC021, 0x8020, 0x41E0,
0x01A0, 0xC060, 0x8061, 0x41A1, 0x0063, 0xC1A3, 0x81A2, 0x4062,
0x0066, 0xC1A6, 0x81A7, 0x4067, 0x01A5, 0xC065, 0x8064, 0x41A4,
0x006C, 0xC1AC, 0x81AD, 0x406D, 0x01AF, 0xC06F, 0x806E, 0x41AE,
0x01AA, 0xC06A, 0x806B, 0x41AB, 0x0069, 0xC1A9, 0x81A8, 0x4068,
0x0078, 0xC1B8, 0x81B9, 0x4079, 0x01BB, 0xC07B, 0x807A, 0x41BA,
0x01BE, 0xC07E, 0x807F, 0x41BF, 0x007D, 0xC1BD, 0x81BC, 0x407C,
0x01B4, 0xC074, 0x8075, 0x41B5, 0x0077, 0xC1B7, 0x81B6, 0x4076,
0x0072, 0xC1B2, 0x81B3, 0x4073, 0x01B1, 0xC071, 0x8070, 0x41B0,
0x0050, 0xC190, 0x8191, 0x4051, 0x0193, 0xC053, 0x8052, 0x4192,
0x0196, 0xC056, 0x8057, 0x4197, 0x0055, 0xC195, 0x8194, 0x4054,
0x019C, 0xC05C, 0x805D, 0x419D, 0x005F, 0xC19F, 0x819E, 0x405E,
0x005A, 0xC19A, 0x819B, 0x405B, 0x0199, 0xC059, 0x8058, 0x4198,
0x0188, 0xC048, 0x8049, 0x4189, 0x004B, 0xC18B, 0x818A, 0x404A,
0x004E, 0xC18E, 0x818F, 0x404F, 0x018D, 0xC04D, 0x804C, 0x418C,
0x0044, 0xC184, 0x8185, 0x4045, 0x0187, 0xC047, 0x8046, 0x4186,
0x0182, 0xC042, 0x8043, 0x4183, 0x0041, 0xC181, 0x8180, 0x4040};
//CONSTRUCTOR
ModbusRTUCRC::ModbusRTUCRC():
m_crc_calculate(),
m_table_crc_index(0),
m_table_crc_value(),
m_start(0),
m_end(0)
{}//CONSTRUCTOR
// #pragma CODE_SECTION("ramfuncs");
uint16_t ModbusRTUCRC::calculate(uint16_t *start, uint16_t length)
{
m_crc_calculate.all = 0x0ffFF;
m_start = start;
m_end = start + length - 1;
_while_cycle();
return m_crc_calculate.all;
}//
//
// #pragma CODE_SECTION("ramfuncs");
uint16_t ModbusRTUCRC::calculate(uint16_t *start, uint16_t *end)
{
m_crc_calculate.all = 0x0ffFF;
m_start = start;
m_end = end;
_while_cycle();
return m_crc_calculate.all;
}//
//
// #pragma CODE_SECTION("ramfuncs");
uint16_t ModbusRTUCRC::calculate(uint16_t databyte, uint16_t crc)
{
m_crc_calculate.all = crc;
m_table_crc_index = m_crc_calculate.byte.low ^ databyte;
m_table_crc_value.all = m_table[m_table_crc_index];
m_crc_calculate.byte.low = m_crc_calculate.byte.high ^ m_table_crc_value.byte.high;
m_crc_calculate.byte.high = m_table_crc_value.byte.low;
return m_crc_calculate.all;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
inline void ModbusRTUCRC::_while_cycle()
{
while(m_start <= m_end)
{
m_table_crc_index = m_crc_calculate.byte.low ^ (*m_start++);
m_table_crc_value.all = m_table[m_table_crc_index];
m_crc_calculate.byte.low = m_crc_calculate.byte.high ^ m_table_crc_value.byte.high;
m_crc_calculate.byte.high = m_table_crc_value.byte.low;
//
}//while
//
}//
//
} /* namespace MODBUSRTU */

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MODBUSRTU/ModbusRTUCRC.h
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/*
* ModbusRTUCRC.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#ifndef MODBUSRTU_MODBUSRTUCRC_H_
#define MODBUSRTU_MODBUSRTUCRC_H_
struct Uint16ByteField
{
uint16_t low: 8;
uint16_t high: 8;
};//Uint16ByteField
union Uint16Register
{
uint16_t all;
Uint16ByteField byte;
Uint16Register():
all(0)
{}
};//
namespace MODBUSRTU
{
class ModbusRTUCRC
{
private:
static const uint16_t m_table[256];
private:
Uint16Register m_crc_calculate;
uint16_t m_table_crc_index;
Uint16Register m_table_crc_value;
uint16_t *m_start;
uint16_t *m_end;
public:
ModbusRTUCRC();
public:
uint16_t calculate(uint16_t *start, uint16_t length);
uint16_t calculate(uint16_t *start, uint16_t *end);
uint16_t calculate(uint16_t databyte, uint16_t crc);
private:
inline void _while_cycle();
};
} /* namespace MODBUSRTU */
#endif /* MODBUSRTU_MODBUSRTUCRC_H_ */

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/*
* ModbusRTUCRCTable.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <stdint.h>
#ifndef MODBUSRTU_MODBUSRTUCRCTABLE_H_
#define MODBUSRTU_MODBUSRTUCRCTABLE_H_
struct Uint16ByteField
{
uint16_t low: 8;
uint16_t high: 8;
};//Uint16ByteField
union Uint16Register
{
uint16_t all;
Uint16ByteField byte;
Uint16Register():
all(0)
{}
};//
static const uint16_t TABLE_CRC_16[] =
{
0x0000, 0xC1C0, 0x81C1, 0x4001, 0x01C3, 0xC003, 0x8002, 0x41C2,
0x01C6, 0xC006, 0x8007, 0x41C7, 0x0005, 0xC1C5, 0x81C4, 0x4004,
0x01CC, 0xC00C, 0x800D, 0x41CD, 0x000F, 0xC1CF, 0x81CE, 0x400E,
0x000A, 0xC1CA, 0x81CB, 0x400B, 0x01C9, 0xC009, 0x8008, 0x41C8,
0x01D8, 0xC018, 0x8019, 0x41D9, 0x001B, 0xC1DB, 0x81DA, 0x401A,
0x001E, 0xC1DE, 0x81DF, 0x401F, 0x01DD, 0xC01D, 0x801C, 0x41DC,
0x0014, 0xC1D4, 0x81D5, 0x4015, 0x01D7, 0xC017, 0x8016, 0x41D6,
0x01D2, 0xC012, 0x8013, 0x41D3, 0x0011, 0xC1D1, 0x81D0, 0x4010,
0x01F0, 0xC030, 0x8031, 0x41F1, 0x0033, 0xC1F3, 0x81F2, 0x4032,
0x0036, 0xC1F6, 0x81F7, 0x4037, 0x01F5, 0xC035, 0x8034, 0x41F4,
0x003C, 0xC1FC, 0x81FD, 0x403D, 0x01FF, 0xC03F, 0x803E, 0x41FE,
0x01FA, 0xC03A, 0x803B, 0x41FB, 0x0039, 0xC1F9, 0x81F8, 0x4038,
0x0028, 0xC1E8, 0x81E9, 0x4029, 0x01EB, 0xC02B, 0x802A, 0x41EA,
0x01EE, 0xC02E, 0x802F, 0x41EF, 0x002D, 0xC1ED, 0x81EC, 0x402C,
0x01E4, 0xC024, 0x8025, 0x41E5, 0x0027, 0xC1E7, 0x81E6, 0x4026,
0x0022, 0xC1E2, 0x81E3, 0x4023, 0x01E1, 0xC021, 0x8020, 0x41E0,
0x01A0, 0xC060, 0x8061, 0x41A1, 0x0063, 0xC1A3, 0x81A2, 0x4062,
0x0066, 0xC1A6, 0x81A7, 0x4067, 0x01A5, 0xC065, 0x8064, 0x41A4,
0x006C, 0xC1AC, 0x81AD, 0x406D, 0x01AF, 0xC06F, 0x806E, 0x41AE,
0x01AA, 0xC06A, 0x806B, 0x41AB, 0x0069, 0xC1A9, 0x81A8, 0x4068,
0x0078, 0xC1B8, 0x81B9, 0x4079, 0x01BB, 0xC07B, 0x807A, 0x41BA,
0x01BE, 0xC07E, 0x807F, 0x41BF, 0x007D, 0xC1BD, 0x81BC, 0x407C,
0x01B4, 0xC074, 0x8075, 0x41B5, 0x0077, 0xC1B7, 0x81B6, 0x4076,
0x0072, 0xC1B2, 0x81B3, 0x4073, 0x01B1, 0xC071, 0x8070, 0x41B0,
0x0050, 0xC190, 0x8191, 0x4051, 0x0193, 0xC053, 0x8052, 0x4192,
0x0196, 0xC056, 0x8057, 0x4197, 0x0055, 0xC195, 0x8194, 0x4054,
0x019C, 0xC05C, 0x805D, 0x419D, 0x005F, 0xC19F, 0x819E, 0x405E,
0x005A, 0xC19A, 0x819B, 0x405B, 0x0199, 0xC059, 0x8058, 0x4198,
0x0188, 0xC048, 0x8049, 0x4189, 0x004B, 0xC18B, 0x818A, 0x404A,
0x004E, 0xC18E, 0x818F, 0x404F, 0x018D, 0xC04D, 0x804C, 0x418C,
0x0044, 0xC184, 0x8185, 0x4045, 0x0187, 0xC047, 0x8046, 0x4186,
0x0182, 0xC042, 0x8043, 0x4183, 0x0041, 0xC181, 0x8180, 0x4040
};
#endif /* MODBUSRTU_MODBUSRTUCRCTABLE_H_ */

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MODBUSRTU/ModbusRTUDefines.h
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/*
* ModbusRTUDefines.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include "F28335/DSP28x_Project.h"
#include "F28335/DSP2833x_Examples.h"
#include "DSP28335/GPIO.h"
#include "DSP28335/SCIBase.h"
#include "MODBUSRTU/ModbusRTUVariant.h"
#ifndef SCIRS485_BAUDRATE_DEFAULT
//#define SCIRS485_BAUDRATE_DEFAULT (DSP28335::BR2400)
//#define SCIRS485_BAUDRATE_DEFAULT (DSP28335::BR4800)
#define SCIRS485_BAUDRATE_DEFAULT (DSP28335::BR9600)
//#define SCIRS485_BAUDRATE_DEFAULT (DSP28335::BR14400)
//#define SCIRS485_BAUDRATE_DEFAULT (DSP28335::BR19200)
//#define SCIRS485_BAUDRATE_DEFAULT (DSP28335::BR38400)
#endif
#ifndef SCIRS485_PARITY_DEFAULT
#define SCIRS485_PARITY_DEFAULT (DSP28335::NO)
//#define SCIRS485_PARITY_DEFAULT (MODBUSRTU::ODD)
//#define SCIRS485_PARITY_DEFAULT (MODBUSRTU::EVEN)
#endif
#ifndef SCIRS485_STOPBITS_DEFAULT
#define SCIRS485_STOPBITS_DEFAULT (DSP28335::ONE)
//#define SCIRS485_STOPBITS_DEFAULT (DSP28335::ODD)
//#define SCIRS485_STOPBITS_DEFAULT (DSP28335::EVEN)
#endif
#ifndef SCIRS485_LENGHT_DEFAULT
#define SCIRS485_LENGHT_DEFAULT (DSP28335::LEN8)
#endif
#ifndef SCIRS485_GPIO_SETUP_DEFAULT
#define SCIRS485_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_scib_setup)
#endif
#ifndef SCIRS485_GPIO_DE_DEFAULT
#define SCIRS485_GPIO_DE_DEFAULT (&DSP28335::GPIO::gpio_scib_re_de_set)
#endif
#ifndef SCIRS485_GPIO_RE_DEFAULT
#define SCIRS485_GPIO_RE_DEFAULT (&DSP28335::GPIO::gpio_scib_re_de_clear)
#endif
#ifndef NOP
#define NOP asm(" NOP")
#endif
#ifndef MODBUSRTU_FUNCTION_BROADCAST
#define MODBUSRTU_FUNCTION_BROADCAST (uint16_t) 00
#endif
#ifndef MODBUSRTU_FUNCTION_READ_COIL_STATUS
#define MODBUSRTU_FUNCTION_READ_COIL_STATUS (uint16_t) 01
#endif
#ifndef MODBUSRTU_FUNCTION_READ_INPUT_STATUS
#define MODBUSRTU_FUNCTION_READ_INPUT_STATUS (uint16_t) 02
#endif
#ifndef MODBUSRTU_FUNCTION_READ_HOLDING_REGISTERS
#define MODBUSRTU_FUNCTION_READ_HOLDING_REGISTERS (uint16_t) 03
#endif
#ifndef MODBUSRTU_FUNCTION_READ_INPUT_REGISTERS
#define MODBUSRTU_FUNCTION_READ_INPUT_REGISTERS (uint16_t) 04
#endif
#ifndef MODBUSRTU_FUNCTION_FORCE_SINGLE_COIL
#define MODBUSRTU_FUNCTION_FORCE_SINGLE_COIL (uint16_t) 05
#endif
#ifndef MODBUSRTU_FUNCTION_PRESET_SINGLE_REGISTER
#define MODBUSRTU_FUNCTION_PRESET_SINGLE_REGISTER (uint16_t) 06
#endif
#ifndef MODBUSRTU_FUNCTION_FORCE_MULTIPLE_COILS
#define MODBUSRTU_FUNCTION_FORCE_MULTIPLE_COILS (uint16_t) 15
#endif
#ifndef MODBUSRTU_FUNCTION_PRESET_MULTIPLE_REGISTERS
#define MODBUSRTU_FUNCTION_PRESET_MULTIPLE_REGISTERS (uint16_t) 16
#endif
#ifndef DEFAULT_MODBUSRTU_INPUT_REGISTERS_SIZE
#define DEFAULT_MODBUSRTU_INPUT_REGISTERS_SIZE (uint16_t)10
#endif
#ifndef DEFAULT_MODBUSRTU_OUTPUT_REGISTERS_SIZE
#define DEFAULT_MODBUSRTU_OUTPUT_REGISTERS_SIZE (uint16_t)10
#endif
#ifndef DEFAULT_MODBUSRTU_INPUT_COILS_SIZE
#define DEFAULT_MODBUSRTU_INPUT_COILS_SIZE (uint16_t)10
#endif
#ifndef DEFAULT_MODBUSRTU_OUTPUT_COILS_SIZE
#define DEFAULT_MODBUSRTU_OUTPUT_COILS_SIZE (uint16_t)10
#endif
#ifndef MODBUSRTU_INPUT_REGISTERS_SIZE
#define MODBUSRTU_INPUT_REGISTERS_SIZE DEFAULT_MODBUSRTU_INPUT_REGISTERS_SIZE
#endif
#ifndef MODBUSRTU_OUTPUT_REGISTERS_SIZE
#define MODBUSRTU_OUTPUT_REGISTERS_SIZE DEFAULT_MODBUSRTU_OUTPUT_REGISTERS_SIZE
#endif
#ifndef MODBUSRTU_INPUT_COILS_SIZE
#define MODBUSRTU_INPUT_COILS_SIZE DEFAULT_MODBUSRTU_INPUT_COILS_SIZE
#endif
#ifndef MODBUSRTU_OUTPUT_COILS_SIZE
#define MODBUSRTU_OUTPUT_COILS_SIZE DEFAULT_MODBUSRTU_OUTPUT_COILS_SIZE
#endif
#ifndef MODBUSRTU_MODBUSRTUDEFINES_H_
#define MODBUSRTU_MODBUSRTUDEFINES_H_
namespace MODBUSRTU
{
enum buffer_type_t {OUTPUTCOILS, INPUTCOILS, OUTPUTREGISTERS, INPUTREGISTERS};
enum transceiver_state_machine_t {SCAN, RECEIVE, WAIT_RESPONSE, TRANSMIT, BREAK};
enum transceiver_event_t {ENTRY, RXREADY, TXREADY, TXWAIT};
enum modbusrtu_register_16_bit_t { REG16_BIT0,
REG16_BIT1,
REG16_BIT2,
REG16_BIT3,
REG16_BIT4,
REG16_BIT5,
REG16_BIT6,
REG16_BIT7,
REG16_BIT8,
REG16_BIT9,
REG16_BIT10,
REG16_BIT11,
REG16_BIT12,
REG16_BIT13,
REG16_BIT14,
REG16_BIT15};
//struct ModbusRTUDataByteField
//{
// uint16_t low :8;
// uint16_t high :8;
//};//ModbusRTUDataByteField
//union ModbusRTUDataRegister
//{
// uint16_t all;
// ModbusRTUDataByteField byte;
// ModbusRTUDataRegister():
// all(0)
// {}
//};//ModbusRTUDataRegister
//enum ModbusRTUEventRS
//{
// ENTRY, // state entry event
// EXIT, // state exit event
// TIMEOUT3_5CHAR, // All datagram have been received
// TIMEOUT1_5CHAR, // Interval time of each byte in datagram. Not used
// RX_READY, // SCIRXST.bit.RXRDY. Serial port received a serial data (one byte)
// TX_READY, // All datagram have been sent
// TX_WAIT // Wait for the datagram to be sent
//};//
/*
enum ModbusRTUReceiveEvent
{
ENTRY,
RECEIVE,
EXIT,
TIMEOUT355CHAR,
TIMEOUT155CHAR,
FRAMEREADY,
WAIT
};//
*/
//struct ModbusRTUTimerStateBitField
//{
// uint16_t time_over_1_5_char :1;
// uint16_t time_over_3_5_char :1;
//};//ModbusRTUTimerStateBitField
//union ModbusRTUTimerState
//{
// uint16_t all;
// ModbusRTUTimerStateBitField bit;
// ModbusRTUTimerState():
// all((uint16_t)0)
// {}
//};//ModbusRTUTimerState
//struct ModbusRTUTimer
//{
// uint32_t counter;
// uint32_t start;
// uint32_t interval;
// uint32_t period_1_5_char;
// uint32_t period_3_5_char;
// ModbusRTUTimerState flag;
// ModbusRTUTimer():
// counter((uint32_t)0),
// start((uint32_t)0),
// interval((uint32_t)0),
// period_1_5_char((uint32_t)0),
// period_3_5_char((uint32_t)0),
// flag()
// {}
//};//
} /* namespace MODBUSRTU */
#endif /* MODBUSRTU_MODBUSRTUDEFINES_H_ */

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MODBUSRTU/ModbusRTUTransceiver.cpp
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/*
* ModbusRTUTransceiver.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "MODBUSRTU/ModbusRTUTransceiver.h"
namespace MODBUSRTU
{
//CONSTRUCTOR
//ModbusRTUTransceiver::ModbusRTUTransceiver(DSP28335::SCIBase& sciport, DSP28335::CPUTimers& cputimer, MODBUSRTU::ModbusRTUCRC& crc):
ModbusRTUTransceiver::ModbusRTUTransceiver(DSP28335::SCIBase& sciport, DSP28335::MeasureTimeInterval& interval_measure, MODBUSRTU::ModbusRTUCRC& crc):
m_sci_port(sciport),
m_sci_config(),
m_node_id(0),
//
m_state_machine(MODBUSRTU::SCAN),
m_event(MODBUSRTU::ENTRY),
//
//m_interval(cputimer.CPUTimer),
m_interval_measure(interval_measure),
m_interval_pause((Uint32)0),
m_interval_b5((Uint32)0),
m_interval_b75((Uint32)0),
m_interval_1b((Uint32)0),
m_interval_1b25((Uint32)0),
m_interval_1b5((Uint32)0),
m_interval_1b75((Uint32)0),
m_interval_3b5((Uint32)0),
m_interval_freeze((Uint32)0),
m_interval_current((Uint32)0),
//
m_rx_buffer(),
m_tx_buffer(),
m_rx_count(0),
m_tx_count(0),
m_tx_length(0),
//
m_aux_rx_buf(0),
m_aux_rx_count(0),
m_aux_tx_buf(0),
m_aux_tx_count(0),
//
m_crc_status(false),
m_crc(crc),
m_crc_rx_frame(0),
m_crc_tx_frame(0),
//
m_rx_external_buffer(m_rx_buffer),
m_tx_external_buffer(m_tx_buffer),
m_rx_messaage_length(&m_rx_count),
m_tx_message_length(&m_tx_count),
//
m_destination(0),
m_source_start(0),
m_source_end(0),
m_copy_length(0),
//
_execute(&ModbusRTUTransceiver::_execute_transceiver),
_frame_transceiver(&ModbusRTUTransceiver::_frame_receive_node_id),
//
_re_de_setup(&DSP28335::GPIO::gpio_scib_re_de_setup),
_driver_enable(&DSP28335::GPIO::gpio_scib_re_de_set),
_receiver_enable(&DSP28335::GPIO::gpio_scib_re_de_clear)
//
{}//CONSTRUCTOR
void ModbusRTUTransceiver::setup(ModbusRTUTransceiverSetup& setup)
{
//m_interval.setup();
_re_de_setup = setup.gpio_re_de_setup;
_driver_enable = setup.gpio_driver_enable;
_receiver_enable = setup.gpio_receiver_enable;
(*_re_de_setup)();
_set_receive_node_id();
//
}//
//
void ModbusRTUTransceiver::configure(ModbusRTUTransceiverConfiguration& config)
{
m_sci_config = config.config;
m_node_id = config.node_id;
if(!m_sci_port.compare_configuration(m_sci_config))
{
m_sci_port.set_configuration(m_sci_config);
//
}//if
switch(m_sci_config.baudrate)
{
case DSP28335::BR2400: {m_interval_b5 = (Uint32)250000; m_interval_b75 = (Uint32)375000; m_interval_1b = (Uint32)500000; m_interval_1b25 = (Uint32)625000; m_interval_1b5 = (Uint32)750000; m_interval_1b75 = (Uint32)875000; m_interval_3b5 = (Uint32)1750000; m_interval_freeze = (Uint32)2000000; break;}
case DSP28335::BR4800: {m_interval_b5 = (Uint32)125000; m_interval_b75 = (Uint32)187500; m_interval_1b = (Uint32)250000; m_interval_1b25 = (Uint32)312500; m_interval_1b5 = (Uint32)375000; m_interval_1b75 = (Uint32)250000; m_interval_3b5 = (Uint32) 875000; m_interval_freeze = (Uint32)1000000; break;}
case DSP28335::BR9600: {m_interval_b5 = (Uint32) 62500; m_interval_b75 = (Uint32) 93750; m_interval_1b = (Uint32)125000; m_interval_1b25 = (Uint32)156250; m_interval_1b5 = (Uint32)187500; m_interval_1b75 = (Uint32)218750; m_interval_3b5 = (Uint32) 437500; m_interval_freeze = (Uint32) 500000; break;}
case DSP28335::BR19200: {m_interval_b5 = (Uint32) 31250; m_interval_b75 = (Uint32) 46875; m_interval_1b = (Uint32) 62500; m_interval_1b25 = (Uint32)78125; m_interval_1b5 = (Uint32) 93750; m_interval_1b75 = (Uint32)109375; m_interval_3b5 = (Uint32) 218750; m_interval_freeze = (Uint32) 250000; break;}
case DSP28335::BR38400: {m_interval_b5 = (Uint32)15625; m_interval_b75 = (Uint32)23437; m_interval_1b = (Uint32) 31250; m_interval_1b25 = (Uint32)39062; m_interval_1b5 = (Uint32) 46875; m_interval_1b75 = (Uint32) 54687; m_interval_3b5 = (Uint32) 109375; m_interval_freeze = (Uint32) 125000; break;}
default: {m_interval_b5 = (Uint32)62500; m_interval_b75 = (Uint32)93750; m_interval_1b = (Uint32)125000; m_interval_1b25 = (Uint32)156250; m_interval_1b5 = (Uint32)187500; m_interval_1b75 = (Uint32)218750; m_interval_3b5 = (Uint32) 437500; m_interval_freeze = (Uint32) 500000; break;}
}//switch
m_interval_pause = m_interval_1b * 0.1;
//m_interval_pause = m_interval_1b * 0.2;
_set_receive_node_id();
//
}//
//
void ModbusRTUTransceiver::port_reset()
{
m_sci_port.set_configuration(m_sci_config);
_set_receive_node_id();
//
}//
//
bool ModbusRTUTransceiver::compare_state(MODBUSRTU::transceiver_state_machine_t state_machine)
{
return m_state_machine == state_machine;
//
}//
//
void ModbusRTUTransceiver::execute()
{
(this->*_execute)();
//
}//
//
void ModbusRTUTransceiver::_execute_transceiver()
{
if(m_sci_port.SciRegs.SCIRXST.bit.BRKDT)
{
_set_break_condition();
//
}//if
//
(this->*_frame_transceiver)();
//
}//
//
void ModbusRTUTransceiver::_execute_break()
{
//m_interval_current = m_interval.interval();
//
}//
//
void ModbusRTUTransceiver::setRXBuffer(uint16_t *bufferStart, uint16_t *messageLen)
{
m_rx_external_buffer = bufferStart;
m_rx_messaage_length = messageLen;
//
}//
//
void ModbusRTUTransceiver::setTXBuffer(uint16_t *bufferStart, uint16_t *messageLen)
{
m_tx_external_buffer = bufferStart;
m_tx_message_length = messageLen;
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_set_receive_node_id()
{
m_state_machine = MODBUSRTU::SCAN;
_frame_transceiver = &ModbusRTUTransceiver::_frame_receive_node_id;
_execute = &ModbusRTUTransceiver::_execute_transceiver;
(*_receiver_enable)();
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_set_receive_function()
{
m_state_machine = MODBUSRTU::RECEIVE;
_frame_transceiver = &ModbusRTUTransceiver::_frame_receive_function;
_execute = &ModbusRTUTransceiver::_execute_transceiver;
(*_receiver_enable)();
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_set_receive_data()
{
m_state_machine = MODBUSRTU::RECEIVE;
_frame_transceiver = &ModbusRTUTransceiver::_frame_receive_data;
_execute = &ModbusRTUTransceiver::_execute_transceiver;
(*_receiver_enable)();
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_set_wait_response()
{
m_state_machine = MODBUSRTU::WAIT_RESPONSE;
_frame_transceiver = &ModbusRTUTransceiver::_frame_wait_response;
_execute = &ModbusRTUTransceiver::_execute_transceiver;
(*_receiver_enable)();
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_set_transmit_data()
{
m_state_machine = MODBUSRTU::TRANSMIT;
_frame_transceiver = &ModbusRTUTransceiver::_frame_transmit_data;
_execute = &ModbusRTUTransceiver::_execute_transceiver;
(*_driver_enable)();
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_set_break_condition()
{
m_state_machine = MODBUSRTU::BREAK;
_frame_transceiver = &ModbusRTUTransceiver::_frame_break_condition;
_execute = &ModbusRTUTransceiver::_execute_break;
(*_receiver_enable)();
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_frame_receive_node_id()
{
if(m_sci_port.SciRegs.SCIRXST.bit.RXRDY)
{
m_aux_rx_buf = m_sci_port.SciRegs.SCIRXBUF.bit.RXDT;
while(m_sci_port.SciRegs.SCIRXST.bit.RXRDY){}
if((m_node_id == m_aux_rx_buf)||(MODBUSRTU_FUNCTION_BROADCAST == m_aux_rx_buf))
{
m_rx_buffer[0] = m_aux_rx_buf;
m_aux_rx_count = 1;
m_interval_measure.start();
_set_receive_function();
//
}//if
}
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_frame_receive_function()
{
if(m_sci_port.SciRegs.SCIRXST.bit.RXRDY)
{
m_aux_rx_buf = m_sci_port.SciRegs.SCIRXBUF.bit.RXDT;
while(m_sci_port.SciRegs.SCIRXST.bit.RXRDY){}
if(//(MODBUSRTU_FUNCTION_BROADCAST == m_aux_rx_buf)||
(MODBUSRTU_FUNCTION_READ_COIL_STATUS == m_aux_rx_buf)||
//(MODBUSRTU_FUNCTION_READ_INPUT_STATUS == m_aux_rx_buf)||
(MODBUSRTU_FUNCTION_READ_HOLDING_REGISTERS == m_aux_rx_buf)||
//(MODBUSRTU_FUNCTION_READ_INPUT_REGISTERS == m_aux_rx_buf)||
(MODBUSRTU_FUNCTION_FORCE_SINGLE_COIL == m_aux_rx_buf)||
(MODBUSRTU_FUNCTION_PRESET_SINGLE_REGISTER == m_aux_rx_buf)||
(MODBUSRTU_FUNCTION_FORCE_MULTIPLE_COILS == m_aux_rx_buf)||
(MODBUSRTU_FUNCTION_PRESET_MULTIPLE_REGISTERS == m_aux_rx_buf))
{
m_rx_buffer[1] = m_aux_rx_buf;
m_aux_rx_count = 2;
m_interval_measure.start();
_set_receive_data();
//
}
else
{
// wrong function, break receive
m_interval_measure.stop();
_set_receive_node_id();
//
}//if else
//
}
else
{
m_interval_current = m_interval_measure.interval();
if(m_interval_current > m_interval_1b5)
{
// exceed time interval, break receive
m_interval_measure.stop();
_set_receive_node_id();
//
}//if
//
}//if else
//
}//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_frame_receive_data()
{
if(m_sci_port.SciRegs.SCIRXST.bit.RXRDY)
{
m_aux_rx_buf = m_sci_port.SciRegs.SCIRXBUF.bit.RXDT;
while(m_sci_port.SciRegs.SCIRXST.bit.RXRDY){}
m_rx_buffer[m_aux_rx_count] = m_aux_rx_buf;
m_aux_rx_count++;
m_interval_measure.start();
if(m_aux_rx_count >= 256)
{
// exceed count, break receive
m_interval_measure.stop();
_set_receive_node_id();
//
}//if
//
}
else
{
m_interval_current = m_interval_measure.interval();
if(m_interval_current >= m_interval_1b5)
{
//
// count must be more then 4
if(m_aux_rx_count > 4)
{
// stop receive, frame is ended
// check message
m_rx_count = m_aux_rx_count;
m_crc_calculate = m_crc.calculate(m_rx_buffer, m_rx_count - 2);
m_crc_rx_frame = (m_rx_buffer[m_rx_count - 1] << 8) | m_rx_buffer[m_rx_count - 2];
m_crc_status = m_crc_calculate == m_crc_rx_frame ? true : false;
if(m_crc_status)
{
m_destination = m_rx_external_buffer;
m_source_start = m_rx_buffer;
m_source_end = m_rx_buffer + m_rx_count - 1;
m_copy_length = m_rx_count;
*m_rx_messaage_length = m_rx_count;
m_event = MODBUSRTU::RXREADY;
//_frame_copy();
_frame_copy_erase();
_set_wait_response();
//
}
else
{
m_interval_measure.stop();
_set_receive_node_id();
//
}//if else
//
}//
else
{
m_interval_measure.stop();
_set_receive_node_id();
//
}// if else
//
}//if
//
}//if else
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_frame_wait_response()
{
if(m_sci_port.SciRegs.SCIRXST.bit.RXRDY)
{
m_aux_rx_buf = m_sci_port.SciRegs.SCIRXBUF.bit.RXDT;
while(m_sci_port.SciRegs.SCIRXST.bit.RXRDY){}
// error protocol, reset message
m_interval_measure.stop();
_set_receive_node_id();
//
}
else
{
m_interval_current = m_interval_measure.interval();
if(m_interval_current >= m_interval_3b5)
{
m_interval_measure.stop();
_set_receive_node_id();
//
}
else
{
if(*m_tx_message_length != 0)
{
// copy external tx buffer
m_tx_length = *m_tx_message_length;
m_source_start = m_tx_external_buffer;
m_source_end = m_tx_external_buffer + m_tx_length - 1;
m_destination = m_tx_buffer;
//_frame_copy_erase();
_frame_copy();
*m_tx_message_length = 0;
m_tx_count = 0;
_set_transmit_data();
_frame_transmit_data();
m_interval_measure.stop();
//
}//if
//
}//if else
//
}//if else
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_frame_transmit_data()
{
if(m_sci_port.SciRegs.SCICTL2.bit.TXRDY & m_sci_port.SciRegs.SCICTL2.bit.TXEMPTY)
{
// data was transmitted
if(m_tx_count >= m_tx_length)
{
// all message was transmitted
// break transmit mode, go to the receive mode
_set_receive_node_id();
//
}
else
{
m_sci_port.SciRegs.SCITXBUF = m_tx_buffer[m_tx_count];
while(m_sci_port.SciRegs.SCICTL2.bit.TXEMPTY == 1){}
m_tx_count++;
//
}//if else
//
}// if
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_frame_break_condition()
{
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
inline void ModbusRTUTransceiver::_frame_copy()
{
while(m_source_start <= m_source_end)
{
*m_destination++ = *m_source_start++;
//
}//while
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
inline void ModbusRTUTransceiver::_frame_copy_erase()
{
while(m_source_start <= m_source_end)
{
*m_destination++ = *m_source_start;
*m_source_start++ = 0;
//
}//while
//
}//
//
// #pragma CODE_SECTION("ramfuncs");
void ModbusRTUTransceiver::_frame_copy(uint16_t *source, uint16_t length, uint16_t *destination)
{
m_destination = destination;
m_source_start = source;
m_source_end = destination + length - 1;
m_copy_length = length;
while(m_source_start <= m_source_end)
{
*m_destination++ = *m_source_start++;
//
}//while
//
}//
//
} /* namespace MODBUSRTU */

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MODBUSRTU/ModbusRTUTransceiver.h
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/*
* ModbusRTUTransceiver.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include <DSP28x_Project.h>
#include "DSP28335/GPIO.h"
#include "DSP28335/CPUTimers.h"
#include "DSP28335/MeasureTimeInterval.h"
#include "DSP28335/SCIA.h"
#include "DSP28335/SCIB.h"
#include "DSP28335/SCIBase.h"
#include "DSP28335/SCIC.h"
#include "MODBUSRTU/ModbusRTUTransceiverBase.h"
#include "MODBUSRTU/ModbusRTUCRC.h"
#include "MODBUSRTU/ModbusRTUDefines.h"
#include "MODBUSRTU/ModbusRTUVariant.h"
#ifndef MODBUSRTU_MODBUSRTUTRANSCEIVER_H_
#define MODBUSRTU_MODBUSRTUTRANSCEIVER_H_
namespace MODBUSRTU
{
class ModbusRTUTransceiver
{
private:
DSP28335::SCIBase& m_sci_port;
DSP28335::SCIConfiguration m_sci_config;
uint16_t m_node_id;
private:
MODBUSRTU::transceiver_state_machine_t m_state_machine;
MODBUSRTU::transceiver_event_t m_event;
private:
DSP28335::MeasureTimeInterval& m_interval_measure;
Uint32 m_interval_pause;
Uint32 m_interval_b5;
Uint32 m_interval_b75;
Uint32 m_interval_1b;
Uint32 m_interval_1b25;
Uint32 m_interval_1b5;
Uint32 m_interval_1b75;
Uint32 m_interval_3b5;
Uint32 m_interval_freeze;
Uint32 m_interval_current;
private:
uint16_t m_rx_buffer[256];
uint16_t m_tx_buffer[256];
uint16_t m_rx_count;
uint16_t m_tx_count;
uint16_t m_tx_length;
//
private:
uint16_t m_aux_rx_buf;
uint16_t m_aux_rx_count;
uint16_t m_aux_tx_buf;
uint16_t m_aux_tx_count;
private:
bool m_crc_status;
MODBUSRTU::ModbusRTUCRC& m_crc;
uint16_t m_crc_calculate;
uint16_t m_crc_rx_frame;
uint16_t m_crc_tx_frame;
private:
uint16_t *m_rx_external_buffer;
uint16_t *m_tx_external_buffer;
uint16_t *m_rx_messaage_length;
uint16_t *m_tx_message_length;
private:
uint16_t *m_destination;
uint16_t *m_source_start;
uint16_t *m_source_end;
uint16_t m_copy_length;
public:
ModbusRTUTransceiver(DSP28335::SCIBase& sciport, DSP28335::MeasureTimeInterval& interval_measure, MODBUSRTU::ModbusRTUCRC& crc);
void setup(ModbusRTUTransceiverSetup& setup);
void configure(ModbusRTUTransceiverConfiguration& config);
void port_reset();
bool compare_state(MODBUSRTU::transceiver_state_machine_t state_machine);
public:
void execute();
public:
void setRXBuffer(uint16_t *bufferStart, uint16_t *messageLen);
void setTXBuffer(uint16_t *bufferStart, uint16_t *messageLen);
private:
void _set_receive_node_id();
void _set_receive_function();
void _set_receive_data();
void _set_wait_response();
void _set_transmit_data();
void _set_break_condition();
private:
void (ModbusRTUTransceiver::*_execute)();
void (ModbusRTUTransceiver::*_frame_transceiver)();
void _execute_transceiver();
void _execute_break();
void _frame_receive_node_id();
void _frame_receive_function();
void _frame_receive_data();
void _frame_wait_response();
void _frame_transmit_data();
void _frame_break_condition();
private:
inline void _frame_copy();
inline void _frame_copy_erase();
void _frame_copy(uint16_t *source, uint16_t length, uint16_t *destination);
private:
void (*_re_de_setup)();
void (*_driver_enable)();
void (*_receiver_enable)();
};
} /* namespace MODBUSRTU */
#endif /* MODBUSRTU_MODBUSRTUTRANSCEIVER_H_ */

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MODBUSRTU/ModbusRTUTransceiverBase.cpp
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/*
* ModbusRTUTransceiverBase.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "MODBUSRTU/ModbusRTUTransceiverBase.h"
namespace MODBUSRTU
{
//CONSTRUCTOR
ModbusRTUTransceiverBase::ModbusRTUTransceiverBase(DSP28335::SCIBase& sciport, DSP28335::CPUTimers& cputimer, MODBUSRTU::ModbusRTUCRC& crc):
m_sci_port(sciport),
m_sci_config(),
m_node_id(0),
//
m_state_machine(MODBUSRTU::SCAN),
m_event(MODBUSRTU::ENTRY)
//
{}//CONSTRUCTOR
} /* namespace MODBUSRTU */

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MODBUSRTU/ModbusRTUTransceiverBase.h
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/*
* ModbusRTUTransceiverBase.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include "F28335/DSP28x_Project.h"
#include "DSP28335/GPIO.h"
#include "DSP28335/CPUTimers.h"
#include "DSP28335/SCIA.h"
#include "DSP28335/SCIB.h"
#include "DSP28335/SCIBase.h"
#include "DSP28335/SCIC.h"
#include "MODBUSRTU/ModbusRTUCRC.h"
#include "MODBUSRTU/ModbusRTUDefines.h"
#include "MODBUSRTU/ModbusRTUVariant.h"
#ifndef MODBUSRTU_MODBUSRTUTRANSCEIVERBASE_H_
#define MODBUSRTU_MODBUSRTUTRANSCEIVERBASE_H_
namespace MODBUSRTU
{
struct ModbusRTUTransceiverSetup
{
pGPIO_FUNCTION gpio_re_de_setup;
pGPIO_FUNCTION gpio_driver_enable;
pGPIO_FUNCTION gpio_receiver_enable;
ModbusRTUTransceiverSetup():
gpio_re_de_setup(0),
gpio_driver_enable(0),
gpio_receiver_enable(0)
{
//gpio_re_de_setup = &DSP28335::GPIO::gpio_scib_re_de_setup;
//gpio_driver_enable = &DSP28335::GPIO::gpio_scib_re_de_set;
//gpio_receiver_enable = &DSP28335::GPIO::gpio_scib_re_de_clear;
}
};//ModbusRTUTransceiverSetup
struct ModbusRTUTransceiverConfiguration
{
uint16_t node_id;
DSP28335::SCIConfiguration config;
ModbusRTUTransceiverConfiguration():
node_id(0),
config()
{
//config.baudrate = SCIRS485_BAUDRATE_DEFAULT;
//config.parity = SCIRS485_PARITY_DEFAULT;
//config.stopbits = SCIRS485_STOPBITS_DEFAULT;
//config.lenght = SCIRS485_LENGHT_DEFAULT;
}
};//ModbusRTUTransceiverConfiguration
class ModbusRTUTransceiverBase
{
protected:
DSP28335::SCIBase& m_sci_port;
DSP28335::SCIConfiguration m_sci_config;
uint16_t m_node_id;
protected:
MODBUSRTU::transceiver_state_machine_t m_state_machine;
MODBUSRTU::transceiver_event_t m_event;
public:
ModbusRTUTransceiverBase(DSP28335::SCIBase& sciport, DSP28335::CPUTimers& cputimer, MODBUSRTU::ModbusRTUCRC& crc);
};
} /* namespace MODBUSRTU */
#endif /* MODBUSRTU_MODBUSRTUTRANSCEIVERBASE_H_ */

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MODBUSRTU/ModbusRTUVariant.cpp
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/*
* ModbusRTUVariant.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "MODBUSRTU/ModbusRTUVariant.h"
namespace MODBUSRTU
{
//CONSTRUCTOR
ModbusRTUVariant::ModbusRTUVariant():
t(MODBUSRTU::VARIANT_UINT32),
u32((uint32_t)0)
{}//CONSTRUCTOR
MODBUSRTU::modbus_variant_type_t ModbusRTUVariant::get_type() const
{
return t;
//
}//
//
void ModbusRTUVariant::set_float(float value)
{
f = value;
t = MODBUSRTU::VARIANT_FLOAT;
//
}//
//
void ModbusRTUVariant::set_int16(int16_t value)
{
i16 = value;
t = MODBUSRTU::VARIANT_INT16;
//
}//
//
void ModbusRTUVariant::set_int32(int32_t value)
{
i32 = value;
t = MODBUSRTU::VARIANT_INT32;
//
}//
//
void ModbusRTUVariant::set_uint16(uint16_t value)
{
u16 = value;
t = MODBUSRTU::VARIANT_UINT16;
//
}//
//
void ModbusRTUVariant::set_uint32(uint32_t value)
{
u32 = value;
t = MODBUSRTU::VARIANT_UINT32;
//
}//
//
void ModbusRTUVariant::set_bool(bool value)
{
b = value;
t = MODBUSRTU::VARIANT_BOOL;
//
}//
//
float ModbusRTUVariant::get_float() const
{
return f;
//
}//
//
int16_t ModbusRTUVariant::get_int16() const
{
return i16;
//
}//
//
int32_t ModbusRTUVariant::get_int32() const
{
return i32;
//
}//
//
uint16_t ModbusRTUVariant::get_uint16() const
{
return u16;
//
}//
//
uint32_t ModbusRTUVariant::get_uint32() const
{
return u32;
//
}//
//
bool ModbusRTUVariant::get_bool() const
{
return b;
}//
//
} /* namespace MODBUSRTU */

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MODBUSRTU/ModbusRTUVariant.h
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/*
* ModbusRTUVariant.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include "RUDRIVEFRAMEWORK/DataTypesDefinitions.h"
#ifndef MODBUSRTU_MODBUSRTUVARIANT_H_
#define MODBUSRTU_MODBUSRTUVARIANT_H_
namespace MODBUSRTU
{
enum modbus_variant_type_t {VARIANT_FLOAT, VARIANT_INT16, VARIANT_INT32, VARIANT_UINT16, VARIANT_UINT32, VARIANT_BOOL};
class ModbusRTUVariant
{
private:
union
{
float f;
int16_t i16;
int32_t i32;
uint16_t u16;
uint32_t u32;
bool b;
};
modbus_variant_type_t t;
public:
ModbusRTUVariant();
modbus_variant_type_t get_type() const;
//setters
void set_float (float v);
void set_int16 (int16_t v);
void set_int32 (int32_t v);
void set_uint16 (uint16_t v);
void set_uint32 (uint32_t v);
void set_bool (bool v);
//getters
float get_float() const;
int16_t get_int16() const;
int32_t get_int32() const;
uint16_t get_uint16() const;
uint32_t get_uint32() const;
bool get_bool() const;
//
};
} /* namespace MODBUSRTU */
#endif /* MODBUSRTU_MODBUSRTUVARIANT_H_ */

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PERIPHERY/AnalogFault.cpp
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/*
* AnalogFault.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/AnalogFault.h"
namespace PERIPHERY
{
//CONSTRUCTOR
AnalogFault::AnalogFault():
m_fault(0),
_gpio_analog_fault_setup(&DSP28335::GPIO::gpio_analog_fault_setup),
_analog_fault_read(&DSP28335::GPIO::gpio_analog_fault_read)
{}//CONSTRUCTOR
void AnalogFault::setup(const AnaloFaultSetup& setup)
{
_gpio_analog_fault_setup = setup.p_gpio_analog_fault_setup;
_analog_fault_read = setup.p_analog_fault_read;
//
}//
//
void AnalogFault::get_hard_code_setup(AnaloFaultSetup& hsetup)
{
hsetup.set_default();
//
}//
//
void AnalogFault::get_fault(uint16_t& analog_fault)
{
(*_analog_fault_read)(m_fault);
analog_fault = m_fault;
//
}//
//
} /* namespace PERIPHERY */

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PERIPHERY/AnalogFault.h
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/*
* AnalogFault.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include "DSP28335/GPIO.h"
#include "PERIPHERY/PeripheryMap.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef PERIPHERY_ANALOGFAULT_H_
#define PERIPHERY_ANALOGFAULT_H_
namespace PERIPHERY
{
struct AnaloFaultSetup
{
pGPIO_FUNCTION p_gpio_analog_fault_setup;
pGPIO_FUNCTION_UINT p_analog_fault_read;
void set_default()
{
p_gpio_analog_fault_setup = &DSP28335::GPIO::gpio_analog_fault_setup;
p_analog_fault_read = &DSP28335::GPIO::gpio_analog_fault_read;
};
AnaloFaultSetup():
p_gpio_analog_fault_setup(&DSP28335::GPIO::gpio_analog_fault_setup),
p_analog_fault_read(&DSP28335::GPIO::gpio_analog_fault_read)
{}
};//AnaloFaultSetup
class AnalogFault
{
private:
uint16_t m_fault;
public:
AnalogFault();
public:
void setup(const AnaloFaultSetup& setup);
void get_hard_code_setup(AnaloFaultSetup& hsetup);
public:
void get_fault(uint16_t& analog_fault);
private:
void (*_gpio_analog_fault_setup)();
void (*_analog_fault_read)(uint16_t& data);
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_ANALOGFAULT_H_ */

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PERIPHERY/DigitalIO.cpp
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/*
* DigitalIO.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/DigitalIO.h"
namespace PERIPHERY
{
//CONSRUCTOR
DigitalIO::DigitalIO():
m_pointer(0)
{}//CONSRUCTOR
//#pragma CODE_SECTION("ramfuncs");
void DigitalIO::setup(uint16_t *memzone)
{
m_pointer = memzone + OFFSET_DATA_DISCRETE_IO;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void DigitalIO::readDigitalIO(uint16_t& data)
{
NOP;
NOP;
NOP;
data = *m_pointer;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void DigitalIO::writeDigitalIO(uint16_t data)
{
NOP;
NOP;
NOP;
*m_pointer = data;
NOP;
NOP;
NOP;
//
}//
//
} /* namespace PERIPHERY */

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PERIPHERY/DigitalIO.h
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/*
* DigitalIO.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <math.h>
#include <stdint.h>
#include "PERIPHERY/PeripheryMap.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef PERIPHERY_DIGITALIO_H_
#define PERIPHERY_DIGITALIO_H_
namespace PERIPHERY
{
struct DigitalIODataBitField
{
uint16_t b00: 1;
uint16_t b01: 1;
uint16_t b02: 1;
uint16_t b03: 1;
uint16_t b04: 1;
uint16_t b05: 1;
uint16_t b06: 1;
uint16_t b07: 1;
uint16_t b08: 1;
uint16_t b09: 1;
uint16_t b10: 1;
uint16_t b11: 1;
uint16_t b12: 1;
uint16_t b13: 1;
uint16_t b14: 1;
uint16_t b15: 1;
};//
union DigitalIODataRegister
{
uint16_t all;
DigitalIODataBitField bit;
DigitalIODataRegister():
all(0)
{}
};//
struct DigitalIOData
{
DigitalIODataRegister input;
DigitalIODataRegister output;
DigitalIOData():
input(),
output()
{}
};//
class DigitalIO
{
private:
uint16_t *m_pointer;
public:
DigitalIO();
void setup(uint16_t *memzone);
public:
void readDigitalIO(uint16_t& data);
void writeDigitalIO(uint16_t data);
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_DIGITALIO_H_ */

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PERIPHERY/ExtADC.cpp
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/*
* ExtADC.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/ExtADC.h"
namespace PERIPHERY
{
//CONSTRUCTOR
ExtADC::ExtADC():
p_channel_00(0),
p_channel_01(0),
p_channel_02(0),
p_channel_03(0),
p_channel_04(0),
p_channel_05(0),
p_channel_06(0),
p_channel_07(0),
p_channel_08(0),
p_channel_09(0),
p_channel_10(0),
p_channel_11(0),
p_channel_12(0),
p_channel_13(0),
p_channel_14(0),
p_channel_15(0),
p_channel_16(0),
p_channel_17(0),
_gpio_setup(&DSP28335::GPIO::ext_adc_start_convertion_setup),
_start_convertion(&DSP28335::GPIO::set_ext_adc_start_convertion),
_stop_convertion(&DSP28335::GPIO::clear_ext_adc_start_convertion)
//
{}//CONSTRUCTOR
void ExtADC::setup(uint16_t *memzone)
{
p_channel_00 = memzone + OFFSET_ADC_0_CHANNEL_0;
p_channel_01 = memzone + OFFSET_ADC_0_CHANNEL_1;
p_channel_02 = memzone + OFFSET_ADC_0_CHANNEL_2;
p_channel_03 = memzone + OFFSET_ADC_0_CHANNEL_3;
p_channel_04 = memzone + OFFSET_ADC_0_CHANNEL_4;
p_channel_05 = memzone + OFFSET_ADC_0_CHANNEL_5;
p_channel_06 = memzone + OFFSET_ADC_1_CHANNEL_0;
p_channel_07 = memzone + OFFSET_ADC_1_CHANNEL_1;;
p_channel_08 = memzone + OFFSET_ADC_1_CHANNEL_2;
p_channel_09 = memzone + OFFSET_ADC_1_CHANNEL_3;
p_channel_10 = memzone + OFFSET_ADC_1_CHANNEL_4;
p_channel_11 = memzone + OFFSET_ADC_1_CHANNEL_5;
p_channel_12 = memzone + OFFSET_ADC_2_CHANNEL_0;
p_channel_13 = memzone + OFFSET_ADC_2_CHANNEL_1;
p_channel_14 = memzone + OFFSET_ADC_2_CHANNEL_2;
p_channel_15 = memzone + OFFSET_ADC_2_CHANNEL_3;
p_channel_16 = memzone + OFFSET_ADC_2_CHANNEL_4;
p_channel_17 = memzone + OFFSET_ADC_2_CHANNEL_5;
(*_gpio_setup)();
//
}//
//
void ExtADC::setup(uint16_t *memzone, const ExtADCSetup& setup)
{
p_channel_00 = memzone + OFFSET_ADC_0_CHANNEL_0;
p_channel_01 = memzone + OFFSET_ADC_0_CHANNEL_1;
p_channel_02 = memzone + OFFSET_ADC_0_CHANNEL_2;
p_channel_03 = memzone + OFFSET_ADC_0_CHANNEL_3;
p_channel_04 = memzone + OFFSET_ADC_0_CHANNEL_4;
p_channel_05 = memzone + OFFSET_ADC_0_CHANNEL_5;
p_channel_06 = memzone + OFFSET_ADC_1_CHANNEL_0;
p_channel_07 = memzone + OFFSET_ADC_1_CHANNEL_1;;
p_channel_08 = memzone + OFFSET_ADC_1_CHANNEL_2;
p_channel_09 = memzone + OFFSET_ADC_1_CHANNEL_3;
p_channel_10 = memzone + OFFSET_ADC_1_CHANNEL_4;
p_channel_11 = memzone + OFFSET_ADC_1_CHANNEL_5;
p_channel_12 = memzone + OFFSET_ADC_2_CHANNEL_0;
p_channel_13 = memzone + OFFSET_ADC_2_CHANNEL_1;
p_channel_14 = memzone + OFFSET_ADC_2_CHANNEL_2;
p_channel_15 = memzone + OFFSET_ADC_2_CHANNEL_3;
p_channel_16 = memzone + OFFSET_ADC_2_CHANNEL_4;
p_channel_17 = memzone + OFFSET_ADC_2_CHANNEL_5;
_gpio_setup = setup.p_gpio_setup;
_start_convertion = setup.p_start_convertion;
_stop_convertion = setup.p_stop_convertion;
(*_gpio_setup)();
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void ExtADC::read_adc(ADC_RESULT& adc_result)
{
NOP;
NOP;
adc_result.channel_00 = *p_channel_00;
adc_result.channel_01 = *p_channel_01;
adc_result.channel_02 = *p_channel_02;
adc_result.channel_03 = *p_channel_03;
adc_result.channel_04 = *p_channel_04;
adc_result.channel_05 = *p_channel_05;
adc_result.channel_06 = *p_channel_06;
adc_result.channel_07 = *p_channel_07;
adc_result.channel_08 = *p_channel_08;
adc_result.channel_09 = *p_channel_09;
adc_result.channel_10 = *p_channel_10;
adc_result.channel_11 = *p_channel_11;
adc_result.channel_12 = *p_channel_12;
adc_result.channel_13 = *p_channel_13;
adc_result.channel_14 = *p_channel_14;
adc_result.channel_15 = *p_channel_15;
adc_result.channel_16 = *p_channel_16;
adc_result.channel_17 = *p_channel_17;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void ExtADC::read_adc(uint16_t adc_result[18])
{
NOP;
NOP;
adc_result[0] = *p_channel_00;
adc_result[1] = *p_channel_01;
adc_result[2] = *p_channel_02;
adc_result[3] = *p_channel_03;
adc_result[4] = *p_channel_04;
adc_result[5] = *p_channel_05;
adc_result[6] = *p_channel_06;
adc_result[7] = *p_channel_07;
adc_result[8] = *p_channel_08;
adc_result[9] = *p_channel_09;
adc_result[10] = *p_channel_10;
adc_result[11] = *p_channel_11;
adc_result[12] = *p_channel_12;
adc_result[13] = *p_channel_13;
adc_result[14] = *p_channel_14;
adc_result[15] = *p_channel_15;
adc_result[16] = *p_channel_16;
adc_result[17] = *p_channel_17;
NOP;
NOP;
NOP;
}//
//
#pragma CODE_SECTION("ramfuncs");
void ExtADC::start_convertion()
{
(*_start_convertion)();
//
}//
//
#pragma CODE_SECTION("ramfuncs");
void ExtADC::stop_convertion()
{
(*_stop_convertion)();
//
}//
//
} /* namespace PERIPHERY */

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/*
* ExtADC.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "DSP28335/GPIO.h"
#include "PERIPHERY/PeripheryMap.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef PERIPHERY_EXTADC_H_
#define PERIPHERY_EXTADC_H_
namespace PERIPHERY
{
struct ExtADCSetup
{
pGPIO_FUNCTION p_gpio_setup;
pGPIO_FUNCTION p_start_convertion;
pGPIO_FUNCTION p_stop_convertion;
void set_default()
{
p_gpio_setup = &DSP28335::GPIO::ext_adc_start_convertion_setup;
p_start_convertion = &DSP28335::GPIO::set_ext_adc_start_convertion;
p_stop_convertion = &DSP28335::GPIO::clear_ext_adc_start_convertion;
};
ExtADCSetup():
p_gpio_setup(&DSP28335::GPIO::ext_adc_start_convertion_setup),
p_start_convertion(&DSP28335::GPIO::set_ext_adc_start_convertion),
p_stop_convertion(&DSP28335::GPIO::clear_ext_adc_start_convertion)
{}
//
};//
struct ExtADCStatusBitField
{
uint16_t busy: 1;
uint16_t read: 1;
uint16_t ready: 1;
};//ExtADCStatus
union ExtADCStatusRegister
{
uint16_t all;
ExtADCStatusBitField bit;
ExtADCStatusRegister():
all(0)
{}
};//
union ADC_RESULT_TYPE
{
uint16_t u16;
int16_t i16;
ADC_RESULT_TYPE():
u16(0)
{}
};//ADC_RESULT_TYPE
struct ADC_RESULT
{
int16_t channel_00;
int16_t channel_01;
int16_t channel_02;
int16_t channel_03;
int16_t channel_04;
int16_t channel_05;
int16_t channel_06;
int16_t channel_07;
int16_t channel_08;
int16_t channel_09;
int16_t channel_10;
int16_t channel_11;
int16_t channel_12;
int16_t channel_13;
int16_t channel_14;
int16_t channel_15;
int16_t channel_16;
int16_t channel_17;
ADC_RESULT():
channel_00(0),
channel_01(0),
channel_02(0),
channel_03(0),
channel_04(0),
channel_05(0),
channel_06(0),
channel_07(0),
channel_08(0),
channel_09(0),
channel_10(0),
channel_11(0),
channel_12(0),
channel_13(0),
channel_14(0),
channel_15(0),
channel_16(0),
channel_17(0)
{}
};//
class ExtADC
{
private:
uint16_t *p_channel_00;
uint16_t *p_channel_01;
uint16_t *p_channel_02;
uint16_t *p_channel_03;
uint16_t *p_channel_04;
uint16_t *p_channel_05;
uint16_t *p_channel_06;
uint16_t *p_channel_07;
uint16_t *p_channel_08;
uint16_t *p_channel_09;
uint16_t *p_channel_10;
uint16_t *p_channel_11;
uint16_t *p_channel_12;
uint16_t *p_channel_13;
uint16_t *p_channel_14;
uint16_t *p_channel_15;
uint16_t *p_channel_16;
uint16_t *p_channel_17;
public:
ExtADC();
void setup(uint16_t *memzone);
void setup(uint16_t *memzone, const ExtADCSetup& setup);
public:
void read_adc(ADC_RESULT& adc_result);
void read_adc(uint16_t adc_result[18]);
void start_convertion();
void stop_convertion();
private:
void (*_gpio_setup)();
void (*_start_convertion)();
void (*_stop_convertion)();
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_EXTADC_H_ */

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/*
* ExtDAC.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/ExtDAC.h"
namespace PERIPHERY
{
//CONSTRUCTOR
ExtDAC::ExtDAC():
p_channel_a(0),
p_channel_b(0),
p_channel_c(0),
p_channel_d(0)
{}//CONSTRUCTOR
//
//
void ExtDAC::setup(uint16_t *memzone)
{
p_channel_a = memzone + OFFSET_DAC_CHANNEL_A;
p_channel_b = memzone + OFFSET_DAC_CHANNEL_B;
p_channel_c = memzone + OFFSET_DAC_CHANNEL_C;
p_channel_d = memzone + OFFSET_DAC_CHANNEL_D;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void ExtDAC::write_data(int16_t data_a, int16_t data_b, int16_t data_c, int16_t data_d)
{
NOP;
NOP;
*p_channel_a = data_a;
*p_channel_b = data_b;
*p_channel_c = data_c;
*p_channel_d = data_d;
NOP;
NOP;
NOP;
//
}//
//
} /* namespace PERIPHERAL */

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/*
* ExtDAC.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PeripheryMap.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef PERIPHERY_EXTDAC_H_
#define PERIPHERY_EXTDAC_H_
namespace PERIPHERY
{
struct DataDACCreator
{
int16_t offset_a;
int16_t offset_b;
int16_t offset_c;
int16_t offset_d;
int16_t channel_a;
int16_t channel_b;
int16_t channel_c;
int16_t channel_d;
DataDACCreator():
offset_a((int16_t)2048),
offset_b((int16_t)2048),
offset_c((int16_t)2048),
offset_d((int16_t)2048),
channel_a((int16_t)0),
channel_b((int16_t)0),
channel_c((int16_t)0),
channel_d((int16_t)0)
{}
};//DataDACCreator
class ExtDAC
{
private:
uint16_t *p_channel_a;
uint16_t *p_channel_b;
uint16_t *p_channel_c;
uint16_t *p_channel_d;
public:
ExtDAC();
void setup(uint16_t *memzone);
public:
void write_data(int16_t data_a, int16_t data_b, int16_t data_c, int16_t data_d);
public:
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_EXTDAC_H_ */

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PERIPHERY/FRAMInterface.h
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/*
* FRAMInterface.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include <stdint.h>
#include "F28335/DSP28x_Project.h"
#include "DSP28335/GPIO.h"
#include "RUDRIVEFRAMEWORK/DataType.h"
#include "RUDRIVEFRAMEWORK/SystemDefinitions.h"
#ifndef PERIPHERY_FRAM_H_
#define PERIPHERY_FRAM_H_
#ifndef SPIA_GPIO_SETUP_DEFAULT_DEFINES
#define SPIA_GPIO_SETUP_DEFAULT (&DSP28335::GPIO::gpio_spia_setup)
#define SPIA_GPIO_SETUP_DEFAULT_DEFINES
#endif
#ifndef SPIA_GPIO_WRITE_PROTECT_SET_DEFINES
#define SPIA_GPIO_WRITE_PROTECT_SET (&DSP28335::GPIO::gpio_spia_write_protect_set)
#define SPIA_GPIO_WRITE_PROTECT_SET_DEFINES
#endif
//
#ifndef SPIA_GPIO_WRITE_PROTECT_CLEAR_DEFINES
#define SPIA_GPIO_WRITE_PROTECT_CLEAR (&DSP28335::GPIO::gpio_spia_write_protect_clear)
#define SPIA_GPIO_WRITE_PROTECT_CLEAR_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WREN_DEFINES
#define FRAM_OPCODE_WREN (uint16_t)0x0600
#define FRAM_OPCODE_WREN_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRDI_DEFINES
#define FRAM_OPCODE_WRDI (uint16_t)0x0400
#define FRAM_OPCODE_WRDI_DEFINES
#endif
//
#ifndef FRAM_OPCODE_RDSR_DEFINES
#define FRAM_OPCODE_RDSR (uint16_t)0x0500
#define FRAM_OPCODE_RDSR_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRSR_DEFINES
#define FRAM_OPCODE_WRSR (uint16_t)0x0100
#define FRAM_OPCODE_WRSR_DEFINES
#endif
//
#ifndef FRAM_OPCODE_READ_DEFINES
#define FRAM_OPCODE_READ (uint16_t)0x0300
#define FRAM_OPCODE_READ_DEFINES
#endif
//
#ifndef FRAM_OPCODE_WRITE_DEFINES
#define FRAM_OPCODE_WRITE (uint16_t)0x0200
#define FRAM_OPCODE_WRITE_DEFINES
#endif
//
#ifndef FRAM_OPCODE_DUMMY_DEFINES
#define FRAM_OPCODE_DUMMY (uint16_t)0x5500
#define FRAM_OPCODE_DUMMY_DEFINES
#endif
//
#ifndef FRAM_OPCODE_ERASE_DEFINES
#define FRAM_OPCODE_ERASE (uint16_t)0xFF00
#define FRAM_OPCODE_ERASE_DEFINES
#endif
//
namespace PERIPHERY
{
struct FRAMSetup
{
pGPIO_FUNCTION gpio_setup;
pGPIO_FUNCTION write_protect_set;
pGPIO_FUNCTION write_protect_clear;
FRAMSetup():
gpio_setup(SPIA_GPIO_SETUP_DEFAULT),
write_protect_set(SPIA_GPIO_WRITE_PROTECT_SET),
write_protect_clear(SPIA_GPIO_WRITE_PROTECT_CLEAR)
{}
};//
struct FRAMDATAWordField
{
uint16_t low :8;
uint16_t high :8;
};//
union FRAMDATAWord
{
uint16_t all;
FRAMDATAWordField byte;
};//
struct FRAMDATALongWord
{
FRAMDATAWord wL;
FRAMDATAWord wH;
};//
union FRAMDataVariant
{
int16_t i16;
uint16_t u16;
int32_t i32;
uint32_t u32;
float f;
bool b;
FRAMDATALongWord lw;
FRAMDataVariant():
u32((uint32_t)0)
{}
};//
class FRAMInterface
{
public:
enum mode_t {WAIT, READ, WRITE, ERASE, VERIFY, READY, RESTORE};
protected:
mode_t m_mode;
private:
//Uint16 m_fifo_tx_status;
//Uint16 m_fifo_rx_status;
private:
Uint16 m_fifo_tx[16];
Uint16 m_fifo_rx[16];
private:
uint16_t *m_buffer_pointer;
uint16_t m_buffer_size;
uint16_t m_buffer_index;
uint16_t m_fram_start_addr;
uint16_t m_fram_addr;
uint16_t m_data_fram;
uint16_t m_data_buffer;
FRAMDataVariant m_data_variant;
bool m_verify_status;
bool *m_p_verify_status;
uint16_t m_delay;
void *m_destination;
public:
FRAMInterface();
void setup();
public:
FRAMInterface::mode_t get_mode();
bool compare_mode(FRAMInterface::mode_t mode);
public:
void break_fram();
void write_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
void read_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
void erase_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
void verify_buffer(uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size, bool *verify_status);
public:
void write_slow_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
void read_slow_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
void erase_slow_buffer (uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
public:
void write_int16 (uint16_t addr, int16_t data);
void write_uint16(uint16_t addr, uint16_t data);
void write_int32 (uint16_t addr, int32_t data);
void write_uint32(uint16_t addr, uint32_t data);
void write_float (uint16_t addr, float data);
void write_bool (uint16_t addr, bool data);
public:
void read_int16 (uint16_t addr, int16_t *destination);
void read_uint16(uint16_t addr, uint16_t *destination);
void read_int32 (uint16_t addr, int32_t *destination);
void read_uint32(uint16_t addr, uint32_t *destination);
void read_float (uint16_t addr, float *destination);
void read_bool (uint16_t addr, bool *destination);
private:
void (*_gpio_setup)();
public:
void set_wp();
void clear_wp();
private:
void (*_set_wp)();
void (*_clear_wp)();
public:
void execute();
private:
void (FRAMInterface::*_execute)();
void _execute_free();
void _execute_ready();
void _execute_read_buffer_get_data();
void _execute_read_status_register();
void _write_buffer();
void _read_buffer_send_opcode();
void _erase_buffer();
void _verify_buffer_send_opcode();
void _execute_verify_buffer_data();
inline void _break_fram();
private:
void _execute_ready_wren_write_buffer();
void _execute_ready_wren_erase_buffer();
void _execute_ready_write_buffer();
void _execute_ready_erase_buffer();
private:
void _execute_ready_wren_write_int16();
void _execute_ready_wren_write_uint16();
void _execute_ready_wren_write_int32();
void _execute_ready_wren_write_uint32();
void _execute_ready_wren_write_float();
void _execute_ready_wren_write_bool();
private:
void _execute_ready_write_int16();
void _execute_ready_write_uint16();
void _execute_ready_write_int32();
void _execute_ready_write_uint32();
void _execute_ready_write_float();
void _execute_ready_write_bool();
private:
void _execute_ready_read_buffer();
void _execute_ready_read_int16();
void _execute_ready_read_uint16();
void _execute_ready_read_int32();
void _execute_ready_read_uint32();
void _execute_ready_read_float();
void _execute_ready_read_bool();
private:
void _execute_write_register();
void _execute_write_16();
void _execute_ready_opcode_wren();
void _execute_ready_opcode_wrsr();
private:
inline void _prepare_execute(uint16_t addr, uint16_t *buffer_pointer, uint16_t buffer_size);
//
inline void _spi_opcode_wren();
inline void _spi_opcode_wrsr();
//
inline void _spi_write_16();
inline void _spi_erase_16();
inline void _spi_read_16();
//
inline void _spi_write_32();
inline void _spi_erase_32();
inline void _spi_read_32();
//
inline void _spi_get_read_data_16();
inline void _spi_get_read_data_32();
inline void _spi_get_status_register();
inline uint16_t _spi_get_fifo_tx_status();
//
};//
} /* namespace PERIPHERY */
#endif /* PERIPHERY_FRAM_H_ */

57
PERIPHERY/IIIPeriphery.cpp
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/*
* IIIPeriphery.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/IIIPeriphery.h"
namespace PERIPHERY
{
//CONSTRUCTOR
IIIPeriphery::IIIPeriphery():
Periphery(),
pwm_brd()
{}//CONSTRUCTOR
//
void IIIPeriphery::setup(uint16_t *memzone)
{
p_memzone = memzone;
dio.setup(p_memzone);
adc.setup(p_memzone);
dac.setup(p_memzone);
fram.setup();
pwm_brd.setup(p_memzone);
//
}//
//
void IIIPeriphery::setup(uint16_t *memzone, const IIIPeripherySetup& setup)
{
p_memzone = memzone;
dio.setup(p_memzone);
adc.setup(p_memzone, setup.extadc);
dac.setup(p_memzone);
fram.setup();
analog_faults.setup(setup.analog_faults);
pwm_brd.setup(p_memzone, setup.pwm_brd);
//
}//
//
//void IIIPeriphery::configure(IIIPeripheryConfiguration& config)
//{
//pwm_brd.configure(config.pwm_brd);
//
//}//
void IIIPeriphery::get_hard_code_setup(IIIPeripherySetup& hsetup)
{
hsetup.pwm_brd.set_default();
hsetup.extadc.set_default();
hsetup.analog_faults.set_default();
//
}//
//
} /* namespace PERIPHERY */

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PERIPHERY/IIIPeriphery.h
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/*
* IIIPeriphery.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/Periphery.h"
#ifndef PERIPHERY_IIIPERIPHERY_H_
#define PERIPHERY_IIIPERIPHERY_H_
namespace PERIPHERY
{
struct IIIPeripherySetup: public PeripherySetup
{
PWMStructureSetup pwm_brd;
IIIPeripherySetup():
PeripherySetup(),
pwm_brd()
{}
};//
//struct IIIPeripheryConfiguration
//{
//PWMABCInterfaceConfiguration pwm_brd;
// IIIPeripheryConfiguration()
// pwm_brd()
// {}
//};//PeripheryConfiguration
class IIIPeriphery: public Periphery
{
public:
PERIPHERY::PWMABCInterace pwm_brd;
public:
IIIPeriphery();
void setup(uint16_t *memzone);
void setup(uint16_t *memzone, const IIIPeripherySetup& setup);
//void configure(IIIPeripheryConfiguration& config);
void get_hard_code_setup(IIIPeripherySetup& hsetup);
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_IIIPERIPHERY_H_ */

54
PERIPHERY/IPeriphery.cpp
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/*
* IPeriphery.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/IPeriphery.h"
namespace PERIPHERY
{
//CONSTRUCTOR
IPeriphery::IPeriphery():
Periphery()
// pwm_brd()
{}//CONSTRUCTOR
//
void IPeriphery::setup(uint16_t *memzone)
{
// p_memzone = memzone;
// dio.setup(p_memzone);
// adc.setup(p_memzone);
// dac.setup(p_memzone);
// fram.setup();
// pwm_brd.setup(p_memzone);
}//
//
void IPeriphery::setup(uint16_t *memzone, const IPeripherySetup& setup)
{
// p_memzone = memzone;
// dio.setup(p_memzone);
// adc.setup(p_memzone, setup.extadc);
// dac.setup(p_memzone);
// fram.setup();
// analog_faults.setup(setup.analog_faults);
// pwm_brd.setup(p_memzone, setup.pwm_brd);
}//
//
//void IPeriphery::configure(IPeripheryConfiguration& config)
//{
// pwm_brd.configure(config.pwm_brd);
//
//}//
//
void IPeriphery::get_hard_code_setup(IPeripherySetup& hsetup)
{
// hsetup.pwm_brd.set_default();
// hsetup.extadc.set_default();
// hsetup.analog_faults.set_default();
//
}//
//
} /* namespace PERIPHERY */

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PERIPHERY/IPeriphery.h
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/*
* IPeriphery.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/Periphery.h"
#ifndef PERIPHERY_IPERIFHERY_H_
#define PERIPHERY_IPERIFHERY_H_
namespace PERIPHERY
{
struct IPeripherySetup: public PeripherySetup
{
PWMStructureSetup pwm_brd;
IPeripherySetup():
PeripherySetup(),
pwm_brd()
{}
};//
struct IPeripheryConfiguration
{
PWMSInterfaceConfiguration pwm_brd;
IPeripheryConfiguration():
pwm_brd()
{}
};//PeripheryConfiguration
class IPeriphery: public Periphery
{
public:
// PERIPHERY::PWMSInterace pwm_brd;
public:
IPeriphery();
void setup(uint16_t *memzone);
void setup(uint16_t *memzone, const IPeripherySetup& setup);
// void configure(IPeripheryConfiguration& config);
void get_hard_code_setup(IPeripherySetup& hsetup);
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_IPERIFHERY_H_ */

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PERIPHERY/PWMABCInterace.cpp
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/*
* PWMInterace.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PWMABCInterace.h"
namespace PERIPHERY
{
//CONSTRUCTOR
PWMABCInterace::PWMABCInterace():
PWMInterface(),
m_counter_phase(0),
m_telemetry_phase_counter(0),
m_telemetry_phase_quantity(3),
m_phase(),
_telemetry_execute(&PWMABCInterace::_telemetry_sequence_one)
//
{}//CONSTRUCTOR
//
void PWMABCInterace::setup(uint16_t *memzone)
{
_setup_phase(m_phase[0], memzone + OFFSET_PWM_PHASE_A);
_setup_phase(m_phase[1], memzone + OFFSET_PWM_PHASE_B);
_setup_phase(m_phase[2], memzone + OFFSET_PWM_PHASE_C);
m_broadcast.p_order = memzone + OFFSET_BROADCAST_ORDER;
m_broadcast.p_cell_quantity_in_phase = memzone + OFFSET_BROADCAST_CELLNUMBER;
m_broadcast.p_freq = memzone + OFFSET_BROADCAST_FREQ;
//
_gpio_hard_fault_setup = &DSP28335::GPIO::gpio_hard_fault_setup;
_hard_fault_read = &DSP28335::GPIO::gpio_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
void PWMABCInterace::setup(const PWMStructureSetup& setup)
{
_gpio_hard_fault_setup = setup.p_gpio_hard_fault_setup;
_hard_fault_read = setup.p_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
void PWMABCInterace::setup(uint16_t *memzone, const PWMStructureSetup& setup)
{
_setup_phase(m_phase[0], memzone + OFFSET_PWM_PHASE_A);
_setup_phase(m_phase[1], memzone + OFFSET_PWM_PHASE_B);
_setup_phase(m_phase[2], memzone + OFFSET_PWM_PHASE_C);
m_broadcast.p_order = memzone + OFFSET_BROADCAST_ORDER;
m_broadcast.p_cell_quantity_in_phase = memzone + OFFSET_BROADCAST_CELLNUMBER;
m_broadcast.p_freq = memzone + OFFSET_BROADCAST_FREQ;
//
_gpio_hard_fault_setup = setup.p_gpio_hard_fault_setup;
_hard_fault_read = setup.p_hard_fault_read;
(*_gpio_hard_fault_setup)();
set_telemetry_sequence_one();
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::initialization(PWMABCInterfaceConfiguration& config)
{
//set_frequency((uint16_t)config.pwm_frequency);
set_cell_quantity_phase(config.cell_quantity[0], config.cell_quantity[1], config.cell_quantity[2]);
set_cmp(0, 0, 0);
set_order(0);
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::_setup_phase(PWMPhaseStructure& phase, uint16_t *base)
{
phase.p_pwm_frequency = base + OFFSET_FREQ_PWM;
phase.p_cell_quantity_in_phase = base + OFFSET_CQ_IN_PHASE;
phase.p_compare = base + OFFSET_CMP;
phase.p_order = base + OFFSET_ORDER;
phase.p_pwm_state = base + OFFSET_PWM_STATE;
phase.p_pwm_version = base + OFFSET_PWM_VERSION;
phase.a_cell_quantity_in_cascade[0] = base + OFFSET_CQ_IN_CASC_00;
phase.a_cell_quantity_in_cascade[1] = base + OFFSET_CQ_IN_CASC_01;
phase.a_cell_quantity_in_cascade[2] = base + OFFSET_CQ_IN_CASC_02;
phase.a_cell_quantity_in_cascade[3] = base + OFFSET_CQ_IN_CASC_03;
phase.a_cell_quantity_in_cascade[4] = base + OFFSET_CQ_IN_CASC_04;
phase.a_cell_quantity_in_cascade[5] = base + OFFSET_CQ_IN_CASC_05;
phase.a_cell_quantity_in_cascade[6] = base + OFFSET_CQ_IN_CASC_06;
phase.a_cell_quantity_in_cascade[7] = base + OFFSET_CQ_IN_CASC_07;
phase.a_cell_quantity_in_cascade[8] = base + OFFSET_CQ_IN_CASC_08;
phase.a_cell_quantity_in_cascade[9] = base + OFFSET_CQ_IN_CASC_09;
phase.a_cell_quantity_in_cascade[10] = base + OFFSET_CQ_IN_CASC_10;
phase.a_cell_quantity_in_cascade[11] = base + OFFSET_CQ_IN_CASC_11;
phase.a_cell_quantity_in_cascade[12] = base + OFFSET_CQ_IN_CASC_12;
phase.a_cell_quantity_in_cascade[13] = base + OFFSET_CQ_IN_CASC_13;
phase.a_cell_quantity_in_cascade[14] = base + OFFSET_CQ_IN_CASC_14;
phase.a_cell_quantity_in_cascade[15] = base + OFFSET_CQ_IN_CASC_15;
phase.a_cell_quantity_in_cascade[16] = base + OFFSET_CQ_IN_CASC_16;
phase.a_cell_quantity_in_cascade[17] = base + OFFSET_CQ_IN_CASC_17;
phase.p_telemetry_box = base + OFFSET_TELEMETRY;
phase.p_breakdown_cell_state = base + OFFSET_CELL_BREAKDOWN;
phase.p_breakdown_cell_address = base + OFFSET_CELL_BREAKDOWN_ADR;
phase.a_cascade_pointers[0] = base + OFFSET_CASCADE_00;
phase.a_cascade_pointers[1] = base + OFFSET_CASCADE_01;
phase.a_cascade_pointers[2] = base + OFFSET_CASCADE_02;
phase.a_cascade_pointers[3] = base + OFFSET_CASCADE_03;
phase.a_cascade_pointers[4] = base + OFFSET_CASCADE_04;
phase.a_cascade_pointers[5] = base + OFFSET_CASCADE_05;
phase.a_cascade_pointers[6] = base + OFFSET_CASCADE_06;
phase.a_cascade_pointers[7] = base + OFFSET_CASCADE_07;
phase.a_cascade_pointers[8] = base + OFFSET_CASCADE_08;
phase.a_cascade_pointers[9] = base + OFFSET_CASCADE_09;
phase.a_cascade_pointers[10] = base + OFFSET_CASCADE_10;
phase.a_cascade_pointers[11] = base + OFFSET_CASCADE_11;
phase.a_cascade_pointers[12] = base + OFFSET_CASCADE_12;
phase.a_cascade_pointers[13] = base + OFFSET_CASCADE_13;
phase.a_cascade_pointers[14] = base + OFFSET_CASCADE_14;
phase.a_cascade_pointers[15] = base + OFFSET_CASCADE_15;
phase.a_cascade_pointers[16] = base + OFFSET_CASCADE_16;
phase.a_cascade_pointers[17] = base + OFFSET_CASCADE_17;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_frequency(uint16_t freq)
{
NOP;
NOP;
NOP;
*m_phase[0].p_pwm_frequency = freq;
*m_phase[1].p_pwm_frequency = freq;
*m_phase[2].p_pwm_frequency = freq;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cascade_quantity()
{
//m_config.cascade_quantity[0] = quant_a;
//m_config.cascade_quantity[1] = quant_b;
//m_config.cascade_quantity[2] = quant_c;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cell_quantity_phase(uint16_t quant_a, uint16_t quant_b, uint16_t quant_c)
{
// m_config.cell_quantity[0]= quant_a;
// m_config.cell_quantity[1]= quant_b;
// m_config.cell_quantity[2]= quant_c;
NOP;
NOP;
NOP;
*m_phase[0].p_cell_quantity_in_phase = quant_a;
*m_phase[1].p_cell_quantity_in_phase = quant_b;
*m_phase[2].p_cell_quantity_in_phase = quant_c;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cmp(uint16_t cmpra, uint16_t cmprb, uint16_t cmprc)
{
NOP;
NOP;
NOP;
*m_phase[0].p_compare = cmpra;
*m_phase[1].p_compare = cmprb;
*m_phase[2].p_compare = cmprc;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_order(uint16_t order)
{
NOP;
NOP;
NOP;
*m_phase[0].p_order = order;
*m_phase[1].p_order = order;
*m_phase[2].p_order = order;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_board_state(uint16_t& state_pwm_a, uint16_t& state_pwm_b, uint16_t& state_pwm_c)
{
NOP;
NOP;
NOP;
state_pwm_a = *m_phase[0].p_pwm_state;
state_pwm_b = *m_phase[1].p_pwm_state;
state_pwm_c = *m_phase[2].p_pwm_state;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_sw_version(uint16_t& version_pwm_a, uint16_t& version_pwm_b, uint16_t& version_pwm_c)
{
NOP;
NOP;
NOP;
version_pwm_a = *m_phase[0].p_pwm_version;
version_pwm_b = *m_phase[1].p_pwm_version;
version_pwm_c = *m_phase[2].p_pwm_version;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_breakdown_cell_state(uint16_t& cellstate_pwm_a, uint16_t& cellstate_pwm_b, uint16_t& cellstate_pwm_c)
{
NOP;
NOP;
NOP;
cellstate_pwm_a = *m_phase[0].p_breakdown_cell_state;
cellstate_pwm_b = *m_phase[1].p_breakdown_cell_state;
cellstate_pwm_c = *m_phase[2].p_breakdown_cell_state;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_breakdown_cell_index(uint16_t& cellindex_pwm_a, uint16_t& cellindex_pwm_b, uint16_t& cellindex_pwm_c)
{
NOP;
NOP;
NOP;
cellindex_pwm_a = *m_phase[0].p_breakdown_cell_address;
cellindex_pwm_b = *m_phase[1].p_breakdown_cell_address;
cellindex_pwm_c = *m_phase[2].p_breakdown_cell_address;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_cell_quantity_cascade(uint16_t phase_index, uint16_t cascadenum, uint16_t quant)
{
// m_config.cell_quantity_in_cascade[phase_index][cascadenum] = quant;
NOP;
NOP;
NOP;
*m_phase[phase_index].a_cell_quantity_in_cascade[cascadenum] = quant;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::broadcast_order(uint16_t order)
{
NOP;
NOP;
NOP;
*m_broadcast.p_order = order;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::broadcast_cell_quantity_phase(uint16_t quant)
{
// m_config.cell_quantity[0]= quant;
// m_config.cell_quantity[1]= quant;
// m_config.cell_quantity[2]= quant;
NOP;
NOP;
NOP;
*m_broadcast.p_cell_quantity_in_phase = quant;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::broadcast_freq(uint16_t freq)
{
// m_config.pwm_frequency = freq;
NOP;
NOP;
NOP;
*m_broadcast.p_freq = freq;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_hard_fault(uint16_t& hard_fault)
{
(*_hard_fault_read)(m_hard_fault.all);
hard_fault = m_hard_fault.all;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::get_indirect_access(uint16_t phase, uint16_t cascade, uint16_t cell, uint16_t offset, uint16_t& telemetry)
{
m_aux_pointer = m_phase[phase].a_cascade_pointers[cascade] + m_offset_cells.cell_offset[cell];
NOP;
NOP;
NOP;
*m_phase[phase].p_telemetry_box = offset;
telemetry = *m_aux_pointer;
NOP;
NOP;
NOP;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::telemetry_execute(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3])
{
(this->*_telemetry_execute)(config, telemetry_phase);
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::reset_telemetry()
{
m_telemetry_phase_counter = 0;
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_telemetry_sequence_one()
{
m_telemetry_phase_counter = 0;
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
_telemetry_execute = &PWMABCInterace::_telemetry_sequence_one;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::set_telemetry_sequence_two()
{
m_telemetry_phase_counter = 0;
m_telemetry_function_counter = 0;
m_telemetry_cascade_counter = 0;
m_telemetry_cell_counter = 0;
//
_telemetry_execute = &PWMABCInterace::_telemetry_sequence_two;
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::_telemetry_sequence_one(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3])
{
//
m_telemetry_function_quantity = 11;
m_telemetry_cascade_quantity = config.cascade_quantity[m_telemetry_phase_counter];
m_telemetry_cell_quantity = config.cell_quantity_in_cascade[m_telemetry_phase_counter][m_telemetry_cascade_counter];
//
switch(m_telemetry_function_counter)
{
case 0:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.state, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].state);
break;
}
case 1:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.saw_init_val, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].saw_init_val);
break;
}
case 2:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.version, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].version);
break;
}
case 3:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.t_pcb, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].t_pcb);
break;
}
case 4:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.ctrl_faults, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].ctrl_faults);
break;
}
case 5:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.int_bd_l, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].int_bd_l);
break;
}
case 6:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.voltage, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].voltage);
break;
}
case 7:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.freq_pwm, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].freq_pwm);
break;
}
case 8:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.time_cntr, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].time_cntr);
break;
}
case 9:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.t_rad, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].t_rad);
break;
}
case 10:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.sync_faults, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].sync_faults);
break;
}
case 11:
{
get_indirect_access( m_telemetry_phase_counter, m_telemetry_cascade_counter, m_telemetry_cell_counter, m_telemetry_fields_offset.int_bd_h, telemetry_phase[m_telemetry_phase_counter].cascade[m_telemetry_cascade_counter].cell[m_telemetry_cell_counter].int_bd_h);
break;
}
default:{}
}//switch
m_telemetry_cell_counter++;
if(m_telemetry_cell_counter >= m_telemetry_cell_quantity)
{
m_telemetry_cell_counter = 0;
m_telemetry_cascade_counter++;
if(m_telemetry_cascade_counter >= m_telemetry_cascade_quantity)
{
m_telemetry_cascade_counter = 0;
m_telemetry_function_counter++;
if(m_telemetry_function_counter > m_telemetry_function_quantity)
{
m_telemetry_function_counter = 0;
m_telemetry_phase_counter++;
if(m_telemetry_phase_counter >= m_telemetry_phase_quantity)
{
m_telemetry_phase_counter = 0;
//
}//if
}//if
//
}//if
//
}//if
//
//
}//
//
//#pragma CODE_SECTION("ramfuncs");
void PWMABCInterace::_telemetry_sequence_two(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3])
{
//
}//
//
//
} /* namespace PERIPHERAL */

133
PERIPHERY/PWMABCInterace.h
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/*
* PWMABCInterace.h
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PWMInterface.h"
#ifndef PERIPHERY_PWMABCINTERACE_H_
#define PERIPHERY_PWMABCINTERACE_H_
namespace PERIPHERY
{
struct PWMABCInterfaceConfiguration: public PWMInterfaceConfiguration
{
uint16_t cascade_quantity[3];
uint16_t cell_quantity[3];
uint16_t cell_quantity_in_cascade[3][18];
PWMABCInterfaceConfiguration():
PWMInterfaceConfiguration(),
cascade_quantity(),
cell_quantity(),
cell_quantity_in_cascade()
{}
};//PWMInterfaceConfiguration
struct PWMABCPhaseValueStructure
{
uint16_t pwm_frequency;
uint16_t adc_isr_multiplier;
uint16_t cascade_quantity[3];
uint16_t cell_quantity_in_phase[3];
uint16_t cmp[3];
uint16_t order;
uint16_t pwm_state[3];
uint16_t pwm_version[3];
uint16_t cell_quantity_in_cascade[3][18];
uint16_t breakdown_cell_state[3];
PWMBreakdownCellAddressRegister breakdown_cell_address[3];
PWMABCPhaseValueStructure():
pwm_frequency(0),
adc_isr_multiplier(1),
cascade_quantity(),
cell_quantity_in_phase(),
cmp(),
order(0),
pwm_state(),
pwm_version(),
cell_quantity_in_cascade(),
breakdown_cell_state(),
breakdown_cell_address()
{}
};//PWMABCPhaseValueStructure
struct PWMABCStructureReference: public PWMABCPhaseValueStructure
{
uint16_t broadcast_order;
uint16_t broadcast_cell_quantity;
uint16_t broadcast_freq;
PWMHardFaultRegister hard_fault;
PWMABCStructureReference():
PWMABCPhaseValueStructure(),
broadcast_order(),
broadcast_cell_quantity(),
broadcast_freq(),
hard_fault()
{}
};//PWMABCStructureReference
class PWMABCInterace: public PWMInterface
{
private:
uint16_t m_counter_phase;
private:
uint16_t m_telemetry_phase_counter;
uint16_t m_telemetry_phase_quantity;
private:
PWMPhaseStructure m_phase[3];
public:
PWMABCInterace();
public:
void setup(uint16_t *memzone);
void setup(const PWMStructureSetup& setup);
void setup(uint16_t *memzone, const PWMStructureSetup& setup);
public:
void initialization(PWMABCInterfaceConfiguration& config);
private:
void _setup_phase(PWMPhaseStructure& phase, uint16_t *base);
//
public:
void set_frequency(uint16_t freq);
void set_cascade_quantity();
void set_cell_quantity_phase(uint16_t quant_a, uint16_t quant_b, uint16_t quant_c);
void set_cmp(uint16_t cmpra, uint16_t cmprb, uint16_t cmprc);
void set_order(uint16_t order);
void get_board_state(uint16_t& state_pwm_a, uint16_t& state_pwm_b, uint16_t& state_pwm_c);
void get_sw_version(uint16_t& version_pwm_a, uint16_t& version_pwm_b, uint16_t& version_pwm_c);
void get_breakdown_cell_state(uint16_t& cellstate_pwm_a, uint16_t& cellstate_pwm_b, uint16_t& cellstate_pwm_c);
void get_breakdown_cell_index(uint16_t& cellindex_pwm_a, uint16_t& cellindex_pwm_b, uint16_t& cellindex_pwm_c);
void set_cell_quantity_cascade(uint16_t phase_index, uint16_t cascadenum, uint16_t quant);
//
void broadcast_order(uint16_t order);
void broadcast_cell_quantity_phase(uint16_t quant);
void broadcast_freq(uint16_t freq);
//
void get_hard_fault(uint16_t& hard_fault);
//
void get_indirect_access(uint16_t phase, uint16_t cascade, uint16_t cell, uint16_t offset, uint16_t& telemetry);
//
void telemetry_execute(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3]);
void reset_telemetry();
void set_telemetry_sequence_one();
void set_telemetry_sequence_two();
//
private:
void (PWMABCInterace::*_telemetry_execute)(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3]);
void _telemetry_sequence_one(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3]);
void _telemetry_sequence_two(PWMABCInterfaceConfiguration& config, PWMPhaseTelemetryValue telemetry_phase[3]);
//
};
} /* namespace PERIPHERY */
#endif /* PERIPHERY_PWMABCINTERACE_H_ */

37
PERIPHERY/PWMInterface.cpp
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/*
* PWMInterface.cpp
*
* Author: Aleksey Gerasimenko
* gerasimenko.aleksey.n@gmail.com
*/
#include "PERIPHERY/PWMInterface.h"
namespace PERIPHERY
{
//CONSTRUCTOR
PWMInterface::PWMInterface():
m_counter_cascade(0),
m_counter_cells(0),
m_aux_offset(0),
m_aux_cell_quantity(0),
m_aux_pointer(0),
//
m_telemetry_function_counter(0),
m_telemetry_cascade_counter (0),
m_telemetry_cell_counter (0),
//
m_telemetry_function_quantity(0),
m_telemetry_cascade_quantity (0),
m_telemetry_cell_quantity (0),
//
m_broadcast(),
m_telemetry_fields_offset(0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x011, 0x012, 0x013, 0x014, 0x015, 0x016),
m_offset_cells(),
m_hard_fault(),
_gpio_hard_fault_setup(&DSP28335::GPIO::gpio_hard_fault_setup),
_hard_fault_read(&DSP28335::GPIO::gpio_hard_fault_read)
{}//CONSTRUCTOR
} /* namespace PERIPHERY */

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